ELPIDA EDS6432AFBH, EDS6432CFBH DATA SHEET
DATA SHEET
64M bits SDRAM
EDS6432AFBH, EDS6432CFBH
(2M words × 32 bits)
Description
The EDS6432AFBH, EDS6432CFBH are 64M bits
SDRAMs organized as 524,288 words × 32 bits × 4
banks. All inputs and outputs are synchronized with
the positive edge of the clock.
Supply voltages are 3.3V (EDS6432AFBH) and 2.5V
(EDS6432CFBH).
They are packaged in 90-ball FBGA.
Features
• 3.3V and 2.5V power supply
• Clock frequency: 166MHz/133MHz (max.)
• Single pulsed /RAS
• ×32 organization
• 4 banks can operate simultaneously and
independently
• Burst read/write operation and burst read/single
write operation capability
• Programmable burst length (BL): 1, 2, 4, 8, full page
• 2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8, full page)
Interleave (BL = 1, 2, 4, 8)
• Programmable /CAS latency (CL): 2, 3
• Byte control by DQM
• Refresh cycles: 4096 refresh cycles/64ms
• 2 variations of refresh
Auto refresh
Self refresh
Pin Configurations
/xxx indicate active low signal.
90-ball FBGA
23456789
1
A
DQ26
B
DQ28
C
VSSQ
D
VSSQ
E
VDDQ
F
VSS
G
A4
H
A7
J
CLK
K
DQM1 NC NC /CAS /WE DQM0
L
VDDQ DQ8 VSS VDD DQ7 VSSQ
M
VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ
N
VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ
P
DQ11 VDDQ VSSQ VDDQ VSSQ DQ4
R
DQ13 DQ15 VSS VDD DQ0 DQ2
DQ24
VDDQ
DQ27
DQ29
DQ31
DQM3
A5
A8
CKE
VSS
VSSQ
DQ25
DQ30
NC
A3
A6
NC
A9
(Top view)
VDD
VDDQ
DQ22
DQ17
NC
A2
A10
NC
BA0
DQ23
VSSQ
DQ20
DQ18
DQ16
DQM2
A0
BA1
/CS
DQ21
DQ19
VDDQ
VDDQ
VSSQ
VDD
A1
NC
/RAS
• FBGA package with lead free solder (Sn-Ag-Cu)
RoHS compliant
A0 to A10
BA0, BA1
DQ0 to DQ31
/CS
/RAS
/CAS
/WE
DQM0 to DQM3
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Address inputs
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
DQ mask enable
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0497E20 (Ver. 2.0)
Date Published July 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004-2005
Ordering Information
Part number
EDS6432AFBH-6B-E 3.3V 2M × 32 4
EDS6432AFBH-75-E
EDS6432CFBH-75-E 2.5V 2M × 32 4
Supply
voltage
Organization
(words × bits)
Internal Banks
Part Number
E D S 64 32 A F BH - 6B - E
EDS6432AFBH, EDS6432CFBH
Clock frequency
MHz (max.)
166
100
133
100
133
100
/CAS latency Package
3
2
3
2
3
2
90-ball FBGA
Elpida Memory
Type
D: Monolithic Device
Product Family
S: SDRAM
Density / Bank
64: 64M/4-bank
Organization
32: x32
Power Supply, Interface
A: 3.3V, LVTTL
C: 2.5V, LVTTL
Die Rev.
Environment Code
E: Lead Free
Speed
6B: 166MHz/CL3
100MHz/CL2
75: 133MHz/CL3
100MHz/CL2
Package
BH: FBGA (Board Type)
Data Sheet E0497E20 (Ver. 2.0)
2
CONTENTS
EDS6432AFBH, EDS6432CFBH
Description.....................................................................................................................................................1
Features.........................................................................................................................................................1
Pin Configurations .........................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Electrical Specifications.................................................................................................................................4
Block Diagram .............................................................................................................................................10
Pin Function.................................................................................................................................................11
Command Operation ...................................................................................................................................12
Simplified State Diagram .............................................................................................................................20
Mode Register Configuration.......................................................................................................................21
Power-up Sequence ....................................................................................................................................23
Operation of the SDRAM.............................................................................................................................24
Timing Waveforms.......................................................................................................................................40
Package Drawing ........................................................................................................................................46
Recommended Soldering Conditions..........................................................................................................47
Data Sheet E0497E20 (Ver. 2.0)
3
EDS6432AFBH, EDS6432CFBH
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, execute power up sequence and initialization sequence before proper device operation is achieved
(refer to the Power up sequence).
Absolute Maximum Ratings
Parameter Symbol Rating Unit Note
Voltage on any pin relative to VSS
[EDS6432AF]
[EDS6432CF] VT –0.5 to VDD + 0.5 (≤ 3.6 (max.)) V
Supply voltage relative to VSS
[EDS6432AF]
[EDS6432CF] VDD –0.5 to +3.6 V
Short circuit output current IOS 50 mA
Power dissipation PD 1.0 W
Operating ambient temperature TA 0 to +70 °C
Storage temperature Tstg –55 to +125 °C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0°C to +70°C)
[EDS6432AF]
Parameter Symbol min. max. Unit Notes
Supply voltage VDD, VDDQ 3.0 3.6 V 1
VSS, VSSQ 0 0 V 2
Input high voltage VIH 2.0 VDD + 0.3 V 3
Input low voltage VIL –0.3 0.8 V 4
Notes: 1. The supply voltage with all VDD and VDDQ pins must be on the same level.
2. The supply voltage with all VSS and VSSQ pins must be on the same level.
3. VIH (max.) = VDD + 1.5V (pulse width ≤ 5ns).
4. VIL (min.) = VSS – 1.5V (pulse width ≤ 5ns).
[EDS6432CF]
Parameter Symbol min. max. Unit Notes
Supply voltage VDD, VDDQ 2.3 2.7 V 1
VSS, VSSQ 0 0 V 2
Input high voltage VIH 1.7 VDD + 0.3 V 3
Input low voltage VIL –0.3 0.7 V 4
Notes: 1. The supply voltage with all VDD and VDDQ pins must be on the same level.
2. The supply voltage with all VSS and VSSQ pins must be on the same level.
3. VIH (max.) = VDD + 1.5V (pulse width ≤ 5ns).
4. VIL (min.) = VSS – 1.5V (pulse width ≤ 5ns).
VT –0.5 to VDD + 0.5 (≤ 4.6 (max.)) V
VDD –0.5 to +4.6 V
Data Sheet E0497E20 (Ver. 2.0)
4
EDS6432AFBH, EDS6432CFBH
DC Characteristics 1 (TA = 0°C to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V) [EDS6432AF]
(TA = 0°C to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [EDS6432CF]
EDS6432AF EDS6432CF
Parameter Symbol Grade max. max. Unit Test condition Notes
Operating current IDD1
Standby current in power
down
Standby current in power
down (input signal stable)
Standby current in non power
down
Standby current in non power
down (input signal stable)
Active standby current in
power down
Active standby current in
power down (input signal
stable)
Active standby current in non
power down
Active standby current in non
power down (input signal
stable)
Burst operating current IDD4
Refresh current IDD5
Self refresh current IDD6 1.5 1.5 mA
IDD2P 3 3 mA
IDD2PS 2 2 mA CKE = VIL, tCK = ∞ 7
IDD2N 20 20 mA
IDD2NS 9 9 mA
IDD3P 4 4 mA
IDD3PS 3 3 mA CKE = VIL, tCK = ∞ 2, 7
IDD3N 40 40 mA
IDD3NS 30 30 mA
-6B
-75
-6B
-75
-6B
-75
120
100
150
130
260
220
120
100
150
130
260
220
mA
mA
mA tRC = tRC (min.) 3
Notes: 1. IDD depends on output load condition when the device is selected. IDD (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
Burst length = 1
tRC = tRC (min.)
CKE = VIL,
tCK = tCK (min.)
CKE, /CS = VIH,
tCK = tCK (min.)
CKE = VIH, tCK = ∞,
/CS = VIH
CKE = VIL,
tCK = tCK (min.)
CKE, /CS = VIH,
tCK = tCK (min.)
CKE = VIH, tCK = ∞,
/CS = VIH
tCK = tCK (min.),
BL = 4
VIH ≥ VDD – 0.2V
VIL ≤ 0.2V
1, 2, 3
6
4
8
1, 2, 6
1, 2, 4
2, 8
1, 2, 5
Data Sheet E0497E20 (Ver. 2.0)
5
EDS6432AFBH, EDS6432CFBH
DC Characteristics 2 (TA = 0°C to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V) [EDS6432AF]
(TA = 0°C to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [EDS6432CF]
[EDS6432AF]
Parameter Symbol min. max. Unit Test condition Note
Input leakage current ILI –1 1 µA 0 ≤ VIN ≤ VDD
Output leakage current ILO –1.5 1.5 µA 0 ≤ VOUT ≤ VDD, DQ = disable
Output high voltage VOH 2.4 — V IOH = –2 mA
Output low voltage VOL — 0.4 V IOL = 2 mA
[EDS6432CF]
Parameter Symbol min. max. Unit Test condition Note
Input leakage current ILI –1 1 µA 0 ≤ VIN ≤ VDD
Output leakage current ILO –1.5 1.5 µA 0 ≤ VOUT ≤ VDD, DQ = disable
Output high voltage VOH 2.0 — V IOH = –1 mA
Output low voltage VOL — 0.4 V IOL = 1 mA
Pin Capacitance (TA = 25°C, VDD, VDDQ = 3.3V ± 0.3V) [EDS6432AF]
(TA = 25°C, VDD, VDDQ = 2.5V ± 0.2V) [EDS6432CF]
Parameter Symbol Pins min. typ. max. Unit Notes
Input capacitance CI1 CLK 1.5 — 3.5 pF 1, 2, 4
Address, CKE, /CS,
CI2
Data input/output
capacitance
CI/O DQ 3.0 — 6.5 pF 1, 2, 3, 4
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. Measurement condition: f = 1MHz, 1.4V(EDS6432AFBH) and 1.2V (EDS6432CFBH) bias, 200mV swing.
3. DQM = VIH to disable DOUT.
4. This parameter is sampled and not 100% tested.
/RAS, /CAS, /WE,
DQM
1.5 — 3.8 pF 1, 2, 4
Data Sheet E0497E20 (Ver. 2.0)
6
EDS6432AFBH, EDS6432CFBH
AC Characteristics (TA = 0°C to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V) [EDS6432AF]
(TA = 0°C to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [EDS6432CF]
-6B -75
Parameter Symbol min. max. min. max. Unit Notes
System clock cycle time
(CL = 2)
(CL = 3) tCK 6 — 7.5 — ns 1
CLK high pulse width tCH 2.5 — 2.5 — ns 1
CLK low pulse width tCL 2.5 — 2.5 — ns 1
Access time from CLK tAC — 5.4 — 5.4 ns 1, 2
Data-out hold time tOH 2 — 2 — ns 1, 2
CLK to Data-out low impedance tLZ 0 — 0 — ns 1, 2, 3
CLK to Data-out high impedance tHZ — 5.4 — 5.4 ns 1, 4
Input setup time tSI 1.5 — 1.5 — ns 1
Input hold time tHI 0.8 — 0.8 — ns 1
Ref/Active to Ref/Active command period tRC 60 — 67.5 — ns 1
Active to Precharge command period tRAS 42 120000 45 120000 ns 1
Active command to column command
(same bank)
Precharge to active command period tRP 18 — 20 — ns 1
Write recovery or data-in to precharge lead
time
Last data into active latency tDAL
Active (a) to Active (b) command period tRRD 12 — 15 — ns 1
Transition time (rise and fall) tT 0.5 5 0.5 5 ns
Refresh period
(4096 refresh cycles)
Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V(EDS6432AF)
and 1.2V (EDS6432CF).
2. Access time is measured at 1.4V(EDS6432AF) and 1.2V (EDS6432CF). Load condition is CL = 30pF.
3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.
tCK 10 — 10 — ns 1
tRCD 18 — 20 — ns 1
tDPL 12 — 15 — ns 1
2CLK +
18ns
tREF — 64 — 64 ms
—
2CLK +
20ns
—
Data Sheet E0497E20 (Ver. 2.0)
7
Test Conditions
[EDS6432AF]
• AC high level voltage/low level input voltage: 2.4V/0.4V
• Input and output timing reference levels: 1.4V
• Output timing measurement reference level: 1.4V
• Input waveform and output load: See following figures
2.4 V
input
[EDS6432CF]
• AC high level voltage/low level input voltage: 2.1V/0.3V
• Input and output timing reference levels: 1.2V
• Output timing measurement reference level: 1.2V
• Input waveform and output load: See following figures
input
2.0 V
0.8 V
0.4 V
t
T
Input waveform and Output load [EDS6432AF]
2.1 V
1.7 V
0.7 V
0.3 V
EDS6432AFBH, EDS6432CFBH
I/O
CL
tT
I/O
CL
t
T
Input waveform and Output load [EDS6432CF]
tT
Data Sheet E0497E20 (Ver. 2.0)
8
EDS6432AFBH, EDS6432CFBH
Relationship Between Frequency and Minimum Latency
Parameter -6B -75
Frequency (MHz) 166 100 133 100
tCK (ns) Symbol 6 10 7.5 10 Unit Notes
Active command to column command
(same bank)
Active command to active command
(same bank)
Active command to precharge command
(same bank)
Precharge command to active command
(same bank)
Write recovery or data-in to precharge
command (same bank)
Active command to active command
(different bank)
Self refresh exit time lSREX 1 1 1 1 tCK 2
Last data in to active command
(Auto precharge, same bank)
Self refresh exit to command input lSEC 10 7 9 7 tCK
Precharge command to high impedance
(CL = 2)
(CL = 3) lHZP 3 3 3 3 tCK
Last data out to active command
(Auto precharge, same bank)
Last data out to precharge (early precharge)
(CL = 2)
(CL = 3) lEP –2 –2 –2 –2 tCK
Column command to column command lCCD 1 1 1 1 tCK
Write command to data in latency lWCD 0 0 0 0 tCK
DQM to data in lDID 0 0 0 0 tCK
DQM to data out lDOD 2 2 2 2 tCK
CKE to CLK disable lCLE 1 1 1 1 tCK
Register set to active command lMRD 2 2 2 2 tCK
/CS to command disable lCDD 0 0 0 0 tCK
Power down exit to command input lPEC 1 1 1 1 tCK
lRCD 3 2 3 2 tCK 1
lRC 10 7 9 7 tCK 1
lRAS 7 5 6 5 tCK 1
lRP 3 2 3 2 tCK 1
lDPL 2 2 2 2 tCK 1
lRRD 2 2 2 2 tCK 1
lDAL 5 4 5 4 tCK = [lDPL + lRP]
lHZP 2 2 tCK
lAPR 1 1 1 1 tCK
lEP –1 –1 tCK
Notes: 1. lRCD to lRRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
= [lRC]
3
Data Sheet E0497E20 (Ver. 2.0)
9
Block Diagram
CLK
CKE
Address
/CS
/RAS
/CAS
/WE
Clock
Generator
Mode
Register
Control Logic
Command Decoder
Row
Address
Buffer
&
Refresh
Counter
Column
Address
Buffer
&
Burst
Counter
EDS6432AFBH, EDS6432CFBH
Bank 3
Bank 2
Bank 1
Bank 0
Row Decoder
Sense Amplifier
Column Decoder &
Latch Circuit
Data Control Circuit
Latch Circuit
DQM
DQ
Input & Output
Buffer
Data Sheet E0497E20 (Ver. 2.0)
10
EDS6432AFBH, EDS6432CFBH
Pin Function
CLK (input pin)
CLK is the master clock input. Other inputs signals are referenced to the CLK rising edge.
CKE (input pins)
CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge is valid; otherwise it is
invalid. If the CLK rising edge is invalid, the internal clock is not issued and the Synchronous DRAM suspends
operation.
When the Synchronous DRAM is not in burst mode and CKE is negated, the device enters power down mode.
During power down mode, CKE must remain low.
/CS (input pins)
/CS low starts the command input cycle. When /CS is high, commands are ignored but operations continue.
/RAS, /CAS, and /WE (input pins)
/RAS, /CAS and /WE have the same symbols on conventional DRAM but different functions. For details, refer to the
command table.
A0 to A10 (input pins)
Row Address is determined by A0 to A10 at the CLK (clock) rising edge in the active command cycle.
Column Address is determined by A0 to A7 at the CLK rising edge in the read or write command cycle.
A10 defines the precharge mode. When A10 is high in the precharge command cycle, all banks are precharged;
when A10 is low, only the bank selected by BA0 and BA1 is precharged.
When A10 is high in read or write command cycle, the precharge starts automatically after the burst access.
BA0 and BA1 (input pin)
BA0 and BA1 are bank select signal (BS). (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0 BA1
Bank 0 L L
Bank 1 H L
Bank 2 L H
Bank 3 H H
Remark: H: VIH. L: VIL.
DQM (input pins)
DQM controls I/O buffers. DQM0 controls DQ0 to DQ7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to
DQ23, DQM3 controls DQ24 to DQ31. In read mode, DQM controls the output buffers like a conventional /OE pin.
DQM high and DQM low turn the output buffers off and on, respectively. The DQM latency for the read is two clocks.
In write mode, DQM controls the word mask. Input data is written to the memory cell if DQM is low but not if DQM is
high. The DQM latency for the write is zero.
DQ0 to DQ31 (input/output pins)
DQ pins have the same function as I/O pins on a conventional DRAM.
VDD, VSS, VDDQ, VSSQ (Power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
buffers.
Data Sheet E0497E20 (Ver. 2.0)
11
EDS6432AFBH, EDS6432CFBH
Command Operation
Command Truth Table
The SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins.
CKE
A0 to
Function Symbol n – 1 n /CS /RAS /CAS /WE BA1 BA0 A10
Device deselect DESL H × H × × × × × × ×
No operation NOP H × L H H H × × × ×
Burst stop BST H × L H H L × × × ×
Read READ H × L H L H V V L V
Read with auto precharge READA H × L H L H V V H V
Write WRIT H × L H L L V V L V
Write with auto precharge WRITA H × L H L L V V H V
Bank activate ACT H × L L H H V V V V
Precharge select bank PRE H × L L H L V V L ×
Precharge all banks PALL H × L L H L × × H ×
Mode register set MRS H × L L L L L L L V
Remark: H: VIH. L: VIL. ×: VIH or VIL. V: Valid address input.
Device deselect command [DESL]
When this command is set (/CS is High), the SDRAM ignore command input at the clock. However, the internal
status is held.
No operation [NOP]
This command is not an execution command. However, the internal operations continue.
Burst stop command [BST]
This command can stop the current burst operation.
Column address strobe and read command [READ]
This command starts a read operation. In addition, the start address of burst read is determined by the column
address (see Address Pins Table in Pin Function) and the bank select address (BA0, BA1). After the read operation,
the output buffer becomes High-Z.
Read with auto-precharge [READA]
This command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4 or 8.
Column address strobe and write command [WRIT]
This command starts a write operation. When the burst write mode is selected, the column address (see Address
Pins Table in Pin Function) and the bank select address (BA0, BA1) become the burst write start address. When the
single write mode is selected, data is only written to the location specified by the column address (see Address Pins
Table in Pin Function) and the bank select address (BA0, BA1).
Write with auto-precharge [WRITA]
This command automatically performs a precharge operation after a burst write with a length of 1, 2, 4 or 8, or after a
single write operation.
A10
Data Sheet E0497E20 (Ver. 2.0)
12
EDS6432AFBH, EDS6432CFBH
Row address strobe and bank activate [ACT]
This command activates the bank that is selected by BA0, BA1 and determines the row address (A0 to A10). (See
Bank Select Signal Table)
Precharge selected bank [PRE]
This command starts precharge operation for the bank selected by BA0, BA1. (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0 BA1
Bank 0 L L
Bank 1 H L
Bank 2 L H
Bank 3 H H
Remark: H: VIH. L: VIL.
Precharge all banks [PALL]
This command starts a precharge operation for all banks.
Refresh [REF/SELF]
This command starts the refresh operation. There are two types of refresh operation, the one is auto-refresh, and
the other is self-refresh. For details, refer to the CKE truth table section.
Mode register set [MRS]
The SDRAM has a mode register that defines how it operates. The mode register is specified by the address pins
(A0 to BA0 and BA1) at the mode register set cycle. For details, refer to the Mode Register Configuration. After
power on, the contents of the mode register are undefined, execute the mode register set command to set up the
mode register.
Data Sheet E0497E20 (Ver. 2.0)
13
EDS6432AFBH, EDS6432CFBH
DQM Truth Table
CKE DQM
Function Symbol n – 1 n
Data write / output enable ENB H × L L L L
Data mask / output disable MASK H × H H H H
DQ0 to DQ7 write enable/output enable ENB0 H × L × × ×
DQ8 to DQ15 write enable/output enable ENB1 H × × L × ×
DQ16 to DQ23 write enable/output enable ENB2 H × × × L ×
DQ24 to DQ31 write enable/output enable ENB3 H × × × × L
DQ0 to DQ7 write inhibit/output disable MASK0 H × H × × ×
DQ8 to DQ15 write inhibit/output disable MASK 1 H × × H × ×
DQ16 to DQ23 write inhibit/output disable MASK 2 H × × × H ×
DQ24 to DQ31 write inhibit/output disable MASK 3 H × × × × H
Remark: H: VIH. L: VIL. ×: VIH or VIL
Write: lDID is needed.
Read: lDOD is needed.
CKE Truth Table
CKE
Current state Function Symbol n – 1 n /CS /RAS /CAS /WE Address
Activating Clock suspend mode entry H L × × × × ×
Any Clock suspend mode L L × × × × ×
Clock suspend Clock suspend mode exit L H × × × × ×
Idle CBR (auto) refresh command REF H H L L L H ×
Idle Self refresh entry SELF H L L L L H ×
Self refresh Self refresh exit L H L H H H ×
L H H × × × ×
Idle Power down entry H L L H H H ×
H L H × × × ×
Power down Power down exit L H H × × × ×
L H L H H H ×
Remark: H: VIH. L: VIL. ×: VIH or VIL
0 1 2 3
Data Sheet E0497E20 (Ver. 2.0)
14
EDS6432AFBH, EDS6432CFBH
Function Truth Table
The following table shows the operations that are performed when each command is issued in each mode of the
SDRAM.
The following table assumes that CKE is high.
Current state /CS /RAS /CAS /WE Address Command Operation
Precharge H × × × × DESL Enter IDLE after tRP
L H H H × NOP Enter IDLE after tRP
L H H L × BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL*3
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL*3
L L H H BA, RA ACT ILLEGAL*3
L L H L BA, A10 PRE, PALL NOP*5
L L L H × REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL
Idle H × × × × DESL NOP
L H H H × NOP NOP
L H H L × BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL*4
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL*4
L L H H BA, RA ACT Bank and row active
L L H L BA, A10 PRE, PALL NOP
L L L H × REF, SELF Refresh
L L L L MODE MRS Mode register set*8
Row active H × × × × DESL NOP
L H H H × NOP NOP
L H H L × BST ILLEGAL
L H L H BA, CA, A10 READ/READA Begin read*6
L H L L BA, CA, A10 WRIT/WRITA Begin write*6
L L H H BA, RA ACT
L L H L BA, A10 PRE, PALL Precharge*7
L L L H × REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL
Read H × × × × DESL Continue burst to end
L H H H × NOP Continue burst to end
L H H L × BST Burst stop
L H L H BA, CA, A10 READ/READA
L H L L BA, CA, A10 WRIT/WRITA Term burst read/start write
L L H H BA, RA ACT
L L H L BA, A10 PRE, PALL Term burst read and Precharge
L L L H × REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL
Other bank active
ILLEGAL on same bank*
Continue burst read to /CAS
latency and New read
Other bank active
ILLEGAL on same bank*
2
2
Data Sheet E0497E20 (Ver. 2.0)
15
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