DATA SHEET
64M bits SDRAM
EDS6432AFBH, EDS6432CFBH
(2M words × 32 bits)
Description
The EDS6432AFBH, EDS6432CFBH are 64M bits
SDRAMs organized as 524,288 words × 32 bits × 4
banks. All inputs and outputs are synchronized with
the positive edge of the clock.
Supply voltages are 3.3V (EDS6432AFBH) and 2.5V
(EDS6432CFBH).
They are packaged in 90-ball FBGA.
Features
• 3.3V and 2.5V power supply
• Clock frequency: 166MHz/133MHz (max.)
• Single pulsed /RAS
• ×32 organization
• 4 banks can operate simultaneously and
independently
• Burst read/write operation and burst read/single
write operation capability
• Programmable burst length (BL): 1, 2, 4, 8, full page
• 2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8, full page)
Interleave (BL = 1, 2, 4, 8)
• Programmable /CAS latency (CL): 2, 3
• Byte control by DQM
• Refresh cycles: 4096 refresh cycles/64ms
• 2 variations of refresh
Auto refresh
Self refresh
Pin Configurations
/xxx indicate active low signal.
90-ball FBGA
23456789
1
A
DQ26
B
DQ28
C
VSSQ
D
VSSQ
E
VDDQ
F
VSS
G
A4
H
A7
J
CLK
K
DQM1 NC NC /CAS /WE DQM0
L
VDDQ DQ8 VSS VDD DQ7 VSSQ
M
VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ
N
VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ
P
DQ11 VDDQ VSSQ VDDQ VSSQ DQ4
R
DQ13 DQ15 VSS VDD DQ0 DQ2
DQ24
VDDQ
DQ27
DQ29
DQ31
DQM3
A5
A8
CKE
VSS
VSSQ
DQ25
DQ30
NC
A3
A6
NC
A9
(Top view)
VDD
VDDQ
DQ22
DQ17
NC
A2
A10
NC
BA0
DQ23
VSSQ
DQ20
DQ18
DQ16
DQM2
A0
BA1
/CS
DQ21
DQ19
VDDQ
VDDQ
VSSQ
VDD
A1
NC
/RAS
• FBGA package with lead free solder (Sn-Ag-Cu)
RoHS compliant
A0 to A10
BA0, BA1
DQ0 to DQ31
/CS
/RAS
/CAS
/WE
DQM0 to DQM3
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Address inputs
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
DQ mask enable
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0497E20 (Ver. 2.0)
Date Published July 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004-2005
Ordering Information
Part number
EDS6432AFBH-6B-E 3.3V 2M × 32 4
EDS6432AFBH-75-E
EDS6432CFBH-75-E 2.5V 2M × 32 4
Supply
voltage
Organization
(words × bits)
Internal Banks
Part Number
E D S 64 32 A F BH - 6B - E
EDS6432AFBH, EDS6432CFBH
Clock frequency
MHz (max.)
166
100
133
100
133
100
/CAS latency Package
3
2
3
2
3
2
90-ball FBGA
Elpida Memory
Type
D: Monolithic Device
Product Family
S: SDRAM
Density / Bank
64: 64M/4-bank
Organization
32: x32
Power Supply, Interface
A: 3.3V, LVTTL
C: 2.5V, LVTTL
Die Rev.
Environment Code
E: Lead Free
Speed
6B: 166MHz/CL3
100MHz/CL2
75: 133MHz/CL3
100MHz/CL2
Package
BH: FBGA (Board Type)
Data Sheet E0497E20 (Ver. 2.0)
2
CONTENTS
EDS6432AFBH, EDS6432CFBH
Description.....................................................................................................................................................1
Features.........................................................................................................................................................1
Pin Configurations .........................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Electrical Specifications.................................................................................................................................4
Block Diagram .............................................................................................................................................10
Pin Function.................................................................................................................................................11
Command Operation ...................................................................................................................................12
Simplified State Diagram .............................................................................................................................20
Mode Register Configuration.......................................................................................................................21
Power-up Sequence ....................................................................................................................................23
Operation of the SDRAM.............................................................................................................................24
Timing Waveforms.......................................................................................................................................40
Package Drawing ........................................................................................................................................46
Recommended Soldering Conditions..........................................................................................................47
Data Sheet E0497E20 (Ver. 2.0)
3
EDS6432AFBH, EDS6432CFBH
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, execute power up sequence and initialization sequence before proper device operation is achieved
(refer to the Power up sequence).
Absolute Maximum Ratings
Parameter Symbol Rating Unit Note
Voltage on any pin relative to VSS
[EDS6432AF]
[EDS6432CF] VT –0.5 to VDD + 0.5 (≤ 3.6 (max.)) V
Supply voltage relative to VSS
[EDS6432AF]
[EDS6432CF] VDD –0.5 to +3.6 V
Short circuit output current IOS 50 mA
Power dissipation PD 1.0 W
Operating ambient temperature TA 0 to +70 °C
Storage temperature Tstg –55 to +125 °C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0°C to +70°C)
[EDS6432AF]
Parameter Symbol min. max. Unit Notes
Supply voltage VDD, VDDQ 3.0 3.6 V 1
VSS, VSSQ 0 0 V 2
Input high voltage VIH 2.0 VDD + 0.3 V 3
Input low voltage VIL –0.3 0.8 V 4
Notes: 1. The supply voltage with all VDD and VDDQ pins must be on the same level.
2. The supply voltage with all VSS and VSSQ pins must be on the same level.
3. VIH (max.) = VDD + 1.5V (pulse width ≤ 5ns).
4. VIL (min.) = VSS – 1.5V (pulse width ≤ 5ns).
[EDS6432CF]
Parameter Symbol min. max. Unit Notes
Supply voltage VDD, VDDQ 2.3 2.7 V 1
VSS, VSSQ 0 0 V 2
Input high voltage VIH 1.7 VDD + 0.3 V 3
Input low voltage VIL –0.3 0.7 V 4
Notes: 1. The supply voltage with all VDD and VDDQ pins must be on the same level.
2. The supply voltage with all VSS and VSSQ pins must be on the same level.
3. VIH (max.) = VDD + 1.5V (pulse width ≤ 5ns).
4. VIL (min.) = VSS – 1.5V (pulse width ≤ 5ns).
VT –0.5 to VDD + 0.5 (≤ 4.6 (max.)) V
VDD –0.5 to +4.6 V
Data Sheet E0497E20 (Ver. 2.0)
4
EDS6432AFBH, EDS6432CFBH
DC Characteristics 1 (TA = 0°C to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V) [EDS6432AF]
(TA = 0°C to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [EDS6432CF]
EDS6432AF EDS6432CF
Parameter Symbol Grade max. max. Unit Test condition Notes
Operating current IDD1
Standby current in power
down
Standby current in power
down (input signal stable)
Standby current in non power
down
Standby current in non power
down (input signal stable)
Active standby current in
power down
Active standby current in
power down (input signal
stable)
Active standby current in non
power down
Active standby current in non
power down (input signal
stable)
Burst operating current IDD4
Refresh current IDD5
Self refresh current IDD6 1.5 1.5 mA
IDD2P 3 3 mA
IDD2PS 2 2 mA CKE = VIL, tCK = ∞ 7
IDD2N 20 20 mA
IDD2NS 9 9 mA
IDD3P 4 4 mA
IDD3PS 3 3 mA CKE = VIL, tCK = ∞ 2, 7
IDD3N 40 40 mA
IDD3NS 30 30 mA
-6B
-75
-6B
-75
-6B
-75
120
100
150
130
260
220
120
100
150
130
260
220
mA
mA
mA tRC = tRC (min.) 3
Notes: 1. IDD depends on output load condition when the device is selected. IDD (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
Burst length = 1
tRC = tRC (min.)
CKE = VIL,
tCK = tCK (min.)
CKE, /CS = VIH,
tCK = tCK (min.)
CKE = VIH, tCK = ∞,
/CS = VIH
CKE = VIL,
tCK = tCK (min.)
CKE, /CS = VIH,
tCK = tCK (min.)
CKE = VIH, tCK = ∞,
/CS = VIH
tCK = tCK (min.),
BL = 4
VIH ≥ VDD – 0.2V
VIL ≤ 0.2V
1, 2, 3
6
4
8
1, 2, 6
1, 2, 4
2, 8
1, 2, 5
Data Sheet E0497E20 (Ver. 2.0)
5
EDS6432AFBH, EDS6432CFBH
DC Characteristics 2 (TA = 0°C to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V) [EDS6432AF]
(TA = 0°C to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [EDS6432CF]
[EDS6432AF]
Parameter Symbol min. max. Unit Test condition Note
Input leakage current ILI –1 1 µA 0 ≤ VIN ≤ VDD
Output leakage current ILO –1.5 1.5 µA 0 ≤ VOUT ≤ VDD, DQ = disable
Output high voltage VOH 2.4 — V IOH = –2 mA
Output low voltage VOL — 0.4 V IOL = 2 mA
[EDS6432CF]
Parameter Symbol min. max. Unit Test condition Note
Input leakage current ILI –1 1 µA 0 ≤ VIN ≤ VDD
Output leakage current ILO –1.5 1.5 µA 0 ≤ VOUT ≤ VDD, DQ = disable
Output high voltage VOH 2.0 — V IOH = –1 mA
Output low voltage VOL — 0.4 V IOL = 1 mA
Pin Capacitance (TA = 25°C, VDD, VDDQ = 3.3V ± 0.3V) [EDS6432AF]
(TA = 25°C, VDD, VDDQ = 2.5V ± 0.2V) [EDS6432CF]
Parameter Symbol Pins min. typ. max. Unit Notes
Input capacitance CI1 CLK 1.5 — 3.5 pF 1, 2, 4
Address, CKE, /CS,
CI2
Data input/output
capacitance
CI/O DQ 3.0 — 6.5 pF 1, 2, 3, 4
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. Measurement condition: f = 1MHz, 1.4V(EDS6432AFBH) and 1.2V (EDS6432CFBH) bias, 200mV swing.
3. DQM = VIH to disable DOUT.
4. This parameter is sampled and not 100% tested.
/RAS, /CAS, /WE,
DQM
1.5 — 3.8 pF 1, 2, 4
Data Sheet E0497E20 (Ver. 2.0)
6
EDS6432AFBH, EDS6432CFBH
AC Characteristics (TA = 0°C to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V) [EDS6432AF]
(TA = 0°C to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [EDS6432CF]
-6B -75
Parameter Symbol min. max. min. max. Unit Notes
System clock cycle time
(CL = 2)
(CL = 3) tCK 6 — 7.5 — ns 1
CLK high pulse width tCH 2.5 — 2.5 — ns 1
CLK low pulse width tCL 2.5 — 2.5 — ns 1
Access time from CLK tAC — 5.4 — 5.4 ns 1, 2
Data-out hold time tOH 2 — 2 — ns 1, 2
CLK to Data-out low impedance tLZ 0 — 0 — ns 1, 2, 3
CLK to Data-out high impedance tHZ — 5.4 — 5.4 ns 1, 4
Input setup time tSI 1.5 — 1.5 — ns 1
Input hold time tHI 0.8 — 0.8 — ns 1
Ref/Active to Ref/Active command period tRC 60 — 67.5 — ns 1
Active to Precharge command period tRAS 42 120000 45 120000 ns 1
Active command to column command
(same bank)
Precharge to active command period tRP 18 — 20 — ns 1
Write recovery or data-in to precharge lead
time
Last data into active latency tDAL
Active (a) to Active (b) command period tRRD 12 — 15 — ns 1
Transition time (rise and fall) tT 0.5 5 0.5 5 ns
Refresh period
(4096 refresh cycles)
Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V(EDS6432AF)
and 1.2V (EDS6432CF).
2. Access time is measured at 1.4V(EDS6432AF) and 1.2V (EDS6432CF). Load condition is CL = 30pF.
3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.
tCK 10 — 10 — ns 1
tRCD 18 — 20 — ns 1
tDPL 12 — 15 — ns 1
2CLK +
18ns
tREF — 64 — 64 ms
—
2CLK +
20ns
—
Data Sheet E0497E20 (Ver. 2.0)
7
Test Conditions
[EDS6432AF]
• AC high level voltage/low level input voltage: 2.4V/0.4V
• Input and output timing reference levels: 1.4V
• Output timing measurement reference level: 1.4V
• Input waveform and output load: See following figures
2.4 V
input
[EDS6432CF]
• AC high level voltage/low level input voltage: 2.1V/0.3V
• Input and output timing reference levels: 1.2V
• Output timing measurement reference level: 1.2V
• Input waveform and output load: See following figures
input
2.0 V
0.8 V
0.4 V
t
T
Input waveform and Output load [EDS6432AF]
2.1 V
1.7 V
0.7 V
0.3 V
EDS6432AFBH, EDS6432CFBH
I/O
CL
tT
I/O
CL
t
T
Input waveform and Output load [EDS6432CF]
tT
Data Sheet E0497E20 (Ver. 2.0)
8
EDS6432AFBH, EDS6432CFBH
Relationship Between Frequency and Minimum Latency
Parameter -6B -75
Frequency (MHz) 166 100 133 100
tCK (ns) Symbol 6 10 7.5 10 Unit Notes
Active command to column command
(same bank)
Active command to active command
(same bank)
Active command to precharge command
(same bank)
Precharge command to active command
(same bank)
Write recovery or data-in to precharge
command (same bank)
Active command to active command
(different bank)
Self refresh exit time lSREX 1 1 1 1 tCK 2
Last data in to active command
(Auto precharge, same bank)
Self refresh exit to command input lSEC 10 7 9 7 tCK
Precharge command to high impedance
(CL = 2)
(CL = 3) lHZP 3 3 3 3 tCK
Last data out to active command
(Auto precharge, same bank)
Last data out to precharge (early precharge)
(CL = 2)
(CL = 3) lEP –2 –2 –2 –2 tCK
Column command to column command lCCD 1 1 1 1 tCK
Write command to data in latency lWCD 0 0 0 0 tCK
DQM to data in lDID 0 0 0 0 tCK
DQM to data out lDOD 2 2 2 2 tCK
CKE to CLK disable lCLE 1 1 1 1 tCK
Register set to active command lMRD 2 2 2 2 tCK
/CS to command disable lCDD 0 0 0 0 tCK
Power down exit to command input lPEC 1 1 1 1 tCK
lRCD 3 2 3 2 tCK 1
lRC 10 7 9 7 tCK 1
lRAS 7 5 6 5 tCK 1
lRP 3 2 3 2 tCK 1
lDPL 2 2 2 2 tCK 1
lRRD 2 2 2 2 tCK 1
lDAL 5 4 5 4 tCK = [lDPL + lRP]
lHZP 2 2 tCK
lAPR 1 1 1 1 tCK
lEP –1 –1 tCK
Notes: 1. lRCD to lRRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
= [lRC]
3
Data Sheet E0497E20 (Ver. 2.0)
9
Block Diagram
CLK
CKE
Address
/CS
/RAS
/CAS
/WE
Clock
Generator
Mode
Register
Control Logic
Command Decoder
Row
Address
Buffer
&
Refresh
Counter
Column
Address
Buffer
&
Burst
Counter
EDS6432AFBH, EDS6432CFBH
Bank 3
Bank 2
Bank 1
Bank 0
Row Decoder
Sense Amplifier
Column Decoder &
Latch Circuit
Data Control Circuit
Latch Circuit
DQM
DQ
Input & Output
Buffer
Data Sheet E0497E20 (Ver. 2.0)
10
EDS6432AFBH, EDS6432CFBH
Pin Function
CLK (input pin)
CLK is the master clock input. Other inputs signals are referenced to the CLK rising edge.
CKE (input pins)
CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge is valid; otherwise it is
invalid. If the CLK rising edge is invalid, the internal clock is not issued and the Synchronous DRAM suspends
operation.
When the Synchronous DRAM is not in burst mode and CKE is negated, the device enters power down mode.
During power down mode, CKE must remain low.
/CS (input pins)
/CS low starts the command input cycle. When /CS is high, commands are ignored but operations continue.
/RAS, /CAS, and /WE (input pins)
/RAS, /CAS and /WE have the same symbols on conventional DRAM but different functions. For details, refer to the
command table.
A0 to A10 (input pins)
Row Address is determined by A0 to A10 at the CLK (clock) rising edge in the active command cycle.
Column Address is determined by A0 to A7 at the CLK rising edge in the read or write command cycle.
A10 defines the precharge mode. When A10 is high in the precharge command cycle, all banks are precharged;
when A10 is low, only the bank selected by BA0 and BA1 is precharged.
When A10 is high in read or write command cycle, the precharge starts automatically after the burst access.
BA0 and BA1 (input pin)
BA0 and BA1 are bank select signal (BS). (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0 BA1
Bank 0 L L
Bank 1 H L
Bank 2 L H
Bank 3 H H
Remark: H: VIH. L: VIL.
DQM (input pins)
DQM controls I/O buffers. DQM0 controls DQ0 to DQ7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to
DQ23, DQM3 controls DQ24 to DQ31. In read mode, DQM controls the output buffers like a conventional /OE pin.
DQM high and DQM low turn the output buffers off and on, respectively. The DQM latency for the read is two clocks.
In write mode, DQM controls the word mask. Input data is written to the memory cell if DQM is low but not if DQM is
high. The DQM latency for the write is zero.
DQ0 to DQ31 (input/output pins)
DQ pins have the same function as I/O pins on a conventional DRAM.
VDD, VSS, VDDQ, VSSQ (Power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
buffers.
Data Sheet E0497E20 (Ver. 2.0)
11
EDS6432AFBH, EDS6432CFBH
Command Operation
Command Truth Table
The SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins.
CKE
A0 to
Function Symbol n – 1 n /CS /RAS /CAS /WE BA1 BA0 A10
Device deselect DESL H × H × × × × × × ×
No operation NOP H × L H H H × × × ×
Burst stop BST H × L H H L × × × ×
Read READ H × L H L H V V L V
Read with auto precharge READA H × L H L H V V H V
Write WRIT H × L H L L V V L V
Write with auto precharge WRITA H × L H L L V V H V
Bank activate ACT H × L L H H V V V V
Precharge select bank PRE H × L L H L V V L ×
Precharge all banks PALL H × L L H L × × H ×
Mode register set MRS H × L L L L L L L V
Remark: H: VIH. L: VIL. ×: VIH or VIL. V: Valid address input.
Device deselect command [DESL]
When this command is set (/CS is High), the SDRAM ignore command input at the clock. However, the internal
status is held.
No operation [NOP]
This command is not an execution command. However, the internal operations continue.
Burst stop command [BST]
This command can stop the current burst operation.
Column address strobe and read command [READ]
This command starts a read operation. In addition, the start address of burst read is determined by the column
address (see Address Pins Table in Pin Function) and the bank select address (BA0, BA1). After the read operation,
the output buffer becomes High-Z.
Read with auto-precharge [READA]
This command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4 or 8.
Column address strobe and write command [WRIT]
This command starts a write operation. When the burst write mode is selected, the column address (see Address
Pins Table in Pin Function) and the bank select address (BA0, BA1) become the burst write start address. When the
single write mode is selected, data is only written to the location specified by the column address (see Address Pins
Table in Pin Function) and the bank select address (BA0, BA1).
Write with auto-precharge [WRITA]
This command automatically performs a precharge operation after a burst write with a length of 1, 2, 4 or 8, or after a
single write operation.
A10
Data Sheet E0497E20 (Ver. 2.0)
12
EDS6432AFBH, EDS6432CFBH
Row address strobe and bank activate [ACT]
This command activates the bank that is selected by BA0, BA1 and determines the row address (A0 to A10). (See
Bank Select Signal Table)
Precharge selected bank [PRE]
This command starts precharge operation for the bank selected by BA0, BA1. (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0 BA1
Bank 0 L L
Bank 1 H L
Bank 2 L H
Bank 3 H H
Remark: H: VIH. L: VIL.
Precharge all banks [PALL]
This command starts a precharge operation for all banks.
Refresh [REF/SELF]
This command starts the refresh operation. There are two types of refresh operation, the one is auto-refresh, and
the other is self-refresh. For details, refer to the CKE truth table section.
Mode register set [MRS]
The SDRAM has a mode register that defines how it operates. The mode register is specified by the address pins
(A0 to BA0 and BA1) at the mode register set cycle. For details, refer to the Mode Register Configuration. After
power on, the contents of the mode register are undefined, execute the mode register set command to set up the
mode register.
Data Sheet E0497E20 (Ver. 2.0)
13
EDS6432AFBH, EDS6432CFBH
DQM Truth Table
CKE DQM
Function Symbol n – 1 n
Data write / output enable ENB H × L L L L
Data mask / output disable MASK H × H H H H
DQ0 to DQ7 write enable/output enable ENB0 H × L × × ×
DQ8 to DQ15 write enable/output enable ENB1 H × × L × ×
DQ16 to DQ23 write enable/output enable ENB2 H × × × L ×
DQ24 to DQ31 write enable/output enable ENB3 H × × × × L
DQ0 to DQ7 write inhibit/output disable MASK0 H × H × × ×
DQ8 to DQ15 write inhibit/output disable MASK 1 H × × H × ×
DQ16 to DQ23 write inhibit/output disable MASK 2 H × × × H ×
DQ24 to DQ31 write inhibit/output disable MASK 3 H × × × × H
Remark: H: VIH. L: VIL. ×: VIH or VIL
Write: lDID is needed.
Read: lDOD is needed.
CKE Truth Table
CKE
Current state Function Symbol n – 1 n /CS /RAS /CAS /WE Address
Activating Clock suspend mode entry H L × × × × ×
Any Clock suspend mode L L × × × × ×
Clock suspend Clock suspend mode exit L H × × × × ×
Idle CBR (auto) refresh command REF H H L L L H ×
Idle Self refresh entry SELF H L L L L H ×
Self refresh Self refresh exit L H L H H H ×
L H H × × × ×
Idle Power down entry H L L H H H ×
H L H × × × ×
Power down Power down exit L H H × × × ×
L H L H H H ×
Remark: H: VIH. L: VIL. ×: VIH or VIL
0 1 2 3
Data Sheet E0497E20 (Ver. 2.0)
14
EDS6432AFBH, EDS6432CFBH
Function Truth Table
The following table shows the operations that are performed when each command is issued in each mode of the
SDRAM.
The following table assumes that CKE is high.
Current state /CS /RAS /CAS /WE Address Command Operation
Precharge H × × × × DESL Enter IDLE after tRP
L H H H × NOP Enter IDLE after tRP
L H H L × BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL*3
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL*3
L L H H BA, RA ACT ILLEGAL*3
L L H L BA, A10 PRE, PALL NOP*5
L L L H × REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL
Idle H × × × × DESL NOP
L H H H × NOP NOP
L H H L × BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL*4
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL*4
L L H H BA, RA ACT Bank and row active
L L H L BA, A10 PRE, PALL NOP
L L L H × REF, SELF Refresh
L L L L MODE MRS Mode register set*8
Row active H × × × × DESL NOP
L H H H × NOP NOP
L H H L × BST ILLEGAL
L H L H BA, CA, A10 READ/READA Begin read*6
L H L L BA, CA, A10 WRIT/WRITA Begin write*6
L L H H BA, RA ACT
L L H L BA, A10 PRE, PALL Precharge*7
L L L H × REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL
Read H × × × × DESL Continue burst to end
L H H H × NOP Continue burst to end
L H H L × BST Burst stop
L H L H BA, CA, A10 READ/READA
L H L L BA, CA, A10 WRIT/WRITA Term burst read/start write
L L H H BA, RA ACT
L L H L BA, A10 PRE, PALL Term burst read and Precharge
L L L H × REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL
Other bank active
ILLEGAL on same bank*
Continue burst read to /CAS
latency and New read
Other bank active
ILLEGAL on same bank*
2
2
Data Sheet E0497E20 (Ver. 2.0)
15
EDS6432AFBH, EDS6432CFBH
Current state /CS /RAS /CAS /WE Address Command Operation
Read with autoprecharge
H × × × × DESL
L H H H × NOP
L H H L × BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL*3
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL*3
L L H H BA, RA ACT
L L H L BA, A10 PRE, PALL ILLEGAL*3
L L L H × REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL
Write H × × × × DESL Continue burst to end
L H H H × NOP Continue burst to end
L H H L × BST Burst stop
L H L H BA, CA, A10 READ/READA Term burst and New read
L H L L BA, CA, A10 WRIT/WRITA Term burst and New write
L L H H BA, RA ACT
L L H L BA, A10 PRE, PALL Term burst write and Precharge*
L L L H × REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL
Write with autoprecharge
Refresh (auto-refresh)
H × × × × DESL
L H H H × NOP
L H H L × BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL*
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL*
L L H H BA, RA ACT
L L H L BA, A10 PRE, PALL ILLEGAL*
L L L H × REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL
H × × × × DESL Enter IDLE after tRC
L H H H × NOP Enter IDLE after tRC
L H H L × BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL*
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL*
L L H H BA, RA ACT ILLEGAL*
L L H L BA, A10 PRE, PALL ILLEGAL*
L L L H × REF, SELF ILLEGAL
L L L L MODE MRS ILLEGAL
Continue burst to end and
precharge
Continue burst to end and
precharge
Other bank active
ILLEGAL on same bank*
Other bank active
ILLEGAL on same bank*
Continue burst to end and
precharge
Continue burst to end and
precharge
3
3
Other bank active
ILLEGAL on same bank*
3
4
4
4
4
2
3
3
1
Data Sheet E0497E20 (Ver. 2.0)
16
EDS6432AFBH, EDS6432CFBH
Current state /CS /RAS /CAS /WE Address Command Operation
Mode register set H × × × × DESL NOP
L H H H × NOP NOP
L H H L × BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL*4
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL*4
L L H H BA, RA ACT Bank and row active*9
L L H L BA, A10 PRE, PALL NOP
L L L H × REF, SELF Refresh*
L L L L MODE MRS Mode register set*8
Remark: H: VIH. L: VIL. ×: VIH or VIL
Notes: 1. An interval of tDPL is required between the final valid data input and the precharge command.
2. If tRRD is not satisfied, this operation is illegal.
3. Illegal for same bank, except for another bank.
4. Illegal for all banks.
5. NOP for same bank, except for another bank.
6. Illegal if tRCD is not satisfied.
7. Illegal if tRAS is not satisfied.
8. MRS command must be issued after DOUT finished, in case of DOUT remaining.
9. Illegal if lMRD is not satisfied.
9
Data Sheet E0497E20 (Ver. 2.0)
17
EDS6432AFBH, EDS6432CFBH
Command Truth Table for CKE
CKE
Current State n – 1 n /CS /RAS /CAS /WE Address Operation Notes
Self refresh H × × × × × × INVALID, CLK (n – 1) would exit self refresh
L H H × × × × Self refresh recovery
L H L H H × × Self refresh recovery
L H L H L × × ILLEGAL
L H L L × × × ILLEGAL
L L × × × × × Continue self refresh
Self refresh recovery H H H × × × × Idle after tRC
H H L H H × × Idle after tRC
H H L H L × × ILLEGAL
H H L L × × × ILLEGAL
H L H × × × × ILLEGAL
H L L H H × × ILLEGAL
H L L H L × × ILLEGAL
H L L L × × × ILLEGAL
Power down H × × × × × INVALID, CLK (n – 1) would exit power down
L H H × × × × EXIT power down
L H L H H H × EXIT power down
L L × × × × × Continue power down mode
All banks idle H H H × × × Refer to operations in Function Truth Table
H H L H × × Refer to operations in Function Truth Table
H H L L H × Refer to operations in Function Truth Table
H H L L L H × CBR (auto) Refresh
H H L L L L OPCODE Refer to operations in Function Truth Table
H L H × × × Begin power down next cycle
H L L H × × Refer to operations in Function Truth Table
H L L L H × Refer to operations in Function Truth Table
H L L L L H × Self refresh 1
H L L L L L OPCODE Refer to operations in Function Truth Table
L H × × × × × Exit power down next cycle
L L × × × × × Power down 1
Row active H × × × × × × Refer to operations in Function Truth Table
L × × × × × × Clock suspend 1
Any state other than H H × × × × Refer to operations in Function Truth Table
listed above H L × × × × × Begin clock suspend next cycle 2
L H × × × × × Exit clock suspend next cycle
L L × × × × × Maintain clock suspend
Remark: H: VIH. L: VIL. ×: VIH or VIL
Notes: 1. Self refresh can be entered only from the all banks idle state. Power down can be entered only from all
banks idle. Clock suspend can be entered only from following states, row active, read, read with autoprecharge, write and write with auto precharge.
2. Must be legal command as defined in Function Truth Table.
Data Sheet E0497E20 (Ver. 2.0)
18
EDS6432AFBH, EDS6432CFBH
Clock suspend mode entry
The SDRAM enters clock suspend mode from active mode by setting CKE to Low. If command is input in the clock
suspend mode entry cycle, the command is valid. The clock suspend mode changes depending on the current
status (1 clock before) as shown below.
ACTIVE clock suspend
This suspend mode ignores inputs after the next clock by internally maintaining the bank active status.
READ suspend and READ with Auto-precharge susp end
The data being output is held (and continues to be output).
WRITE suspend and WRIT with Auto-precharge suspend
In this mode, external signals are not accepted. However, the internal state is held.
Clock suspend
During clock suspend mode, keep the CKE to Low.
Clock suspend mode exit
The SDRAM exits from clock suspend mode by setting CKE to High during the clock suspend state.
IDLE
In this state, all banks are not selected, and completed precharge operation.
Auto-refresh command [REF]
When this command is input from the IDLE state, the SDRAM starts auto-refresh operation. (The auto-refresh is the
same as the CBR refresh of conventional DRAMs.) During the auto-refresh operation, refresh address and bank
select address are generated inside the SDRAM. For every auto-refresh cycle, the internal address counter is
updated. Accordingly, 4096 times are required to refresh the entire memory. Before executing the auto-refresh
command, all the banks must be in the IDLE state. In addition, since the precharge for all banks is automatically
performed after auto-refresh, no precharge command is required after auto-refresh.
Self-refresh entry [SELF]
When this command is input during the IDLE state, the SDRAM starts self-refresh operation. After the execution of
this command, self-refresh continues while CKE is Low. Since self-refresh is performed internally and automatically,
external refresh operations are unnecessary.
Power down mode entry
When this command is executed during the IDLE state, the SDRAM enters power down mode. In power down
mode, power consumption is suppressed by cutting off the initial input circuit.
Self-refresh exit
When this command is executed during self-refresh mode, the SDRAM can exit from self-refresh mode. After exiting
from self-refresh mode, the SDRAM enters the IDLE state.
Power down exit
When this command is executed at the power down mode, the SDRAM can exit from power down mode. After
exiting from power down mode, the SDRAM enters the IDLE state.
Data Sheet E0497E20 (Ver. 2.0)
19
Simplified State Diagram
EDS6432AFBH, EDS6432CFBH
SELF
REFRESH
SR ENTRY
SR EXIT
WRITE
SUSPEND
WRITEA
SUSPEND
MODE
REGISTER
SET
Write
CKE_
CKE
WRITE
WITH AP
CKE_
CKE
BST
MRS
ACTIVE
CLOCK
SUSPEND
CKE
WRITE
WRITE
WITH
AP
WRITE
READ
WITH AP
WRITEA
PRECHARGE PRECHARGE
IDLE
ACTIVE
CKE_
ROW
ACTIVE
READ
WRITE
PRECHARGE
CKE_
READ
WITH
AP
WRITE
WITH AP
REFRESH
CKE
READ
IDLE
POWER
DOWN
BST
READ
READA
AUTO
REFRESH
Read
CKE_
CKE
READ
WITH AP
CKE_
CKE
*1
READ
SUSPEND
READA
SUSPEND
POWER
APPLIED
POWER
ON
PRECHARGE
PRECHARGE
Automatic transition after completion of command.
Transition resulting from command input.
Note: 1. After the auto-refresh operation, precharge operation is performed automatically and
enter the IDLE state.
Data Sheet E0497E20 (Ver. 2.0)
20
EDS6432AFBH, EDS6432CFBH
Mode Register Configuration
Mode Register Set
The mode register is set by the input to the address pins (A0 to A10, BA0 and BA1) during mode register set cycles.
The mode register consists of five sections, each of which is assigned to address pins.
BA1, BA0, A8, A9, A10: (OPCODE): The SDRAM has two types of write modes. One is the burst write mode, and
the other is the single write mode. These bits specify write mode.
Burst read and burst write: Burst write is performed for the specified burst length starting from the column address
specified in the write cycle.
Burst read and single write: Data is only written to the column address specified during the write cycle, regardless of
the burst length.
A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set.
A6, A5, A4: (LMODE): These pins specify the /CAS latency.
A3: (BT): A burst type is specified.
A2, A1, A0: (BL): These pins specify the burst length.
BA1
0
0
0
0
0
1
1
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A10
BA0BA1
OPCODE 0 LMODE BT BL
A3
BA0
0
0
0
0
1
0
1
000 R
001 R
010 2
011 3
1XX R
A9
A10
0
0
0R
X
1 Burst read and single write
X
1R
X
XRX
X
XRX
X
XRX
X
Write mode
A8
Burst read and burst write
0
1
0
1
Burst typeA6 A5 A4 CAS latency
0 Sequential
1 Interleave
F.P.: Full Page
R is Reserved (inhibit)
X: 0 or 1
A2 A1 A0
000 1
001 2
010 4
011 8
100 R
101 R R
110 R
111
Mode Register Set
Burst length
BT=0 BT=1
1
2
4
8
R
R
F.P.
R
Data Sheet E0497E20 (Ver. 2.0)
21
EDS6432AFBH, EDS6432CFBH
Burst length = 2
Starting Ad.
A0
0
1
Burst length = 8
Starting Ad.
A2 A1 A0
000
001
010
011
100
101
110
111
Addressing(decimal)
InterleaveSequential
0, 1,
1, 0,
Addressing(decimal)
0, 1, 2, 3, 4, 5, 6, 7,
1, 2, 3, 4, 5, 6, 7,
2, 3, 4, 5, 6, 7,
3, 4, 5, 6, 7,
4, 5, 6, 7,
5, 6, 7,
6, 7,
7,
0, 1,
1, 0,
0, 1, 2, 3,
0, 1, 2, 3, 4,
0, 1, 2, 3, 4, 5,
0, 1, 2, 3, 4, 5, 6,
Burst length = 4
Starting Ad.
A1 A0
00
01
10
11
InterleaveSequential
0, 1, 2, 3, 4, 5, 6, 7,
0,
1, 0, 3, 2, 5, 4, 7,
0, 1,
0, 1, 2,
Burst Sequence
2, 3, 0, 1, 6, 7,
3, 2, 1, 0, 7,
4, 5, 6, 7,
5, 4, 7,
6, 7,
7,
Addressing(decimal)
InterleaveSequential
0, 1, 2, 3,
1, 2, 3, 0,
2, 3, 0, 1,
3,
0, 1, 2,
0, 1, 2, 3,
6, 1, 0, 3, 2,
4, 5, 2, 3, 0, 1,
6, 5, 4, 3, 2, 1, 0,
0, 1, 2, 3,
1, 0, 3, 2,
2, 3, 0, 1,
3, 2, 1, 0,
4, 5,
6, 5, 4,
6,
Full page burst is available only for sequential addressing. The addressing sequence is started from the column
address that is asserted by read/write command. And the address is increased one by one.
It is back to the address 0 when the address reaches at the end of address 255. “Full page burst” stops the burst
read/write with burst stop command.
Data Sheet E0497E20 (Ver. 2.0)
22
EDS6432AFBH, EDS6432CFBH
Power-up Sequence
Power-up sequence
The SDRAM should be goes on the following sequence with power up.
The CLK, CKE, /CS, DQM and DQ pins keep low till power stabilizes.
The CLK pin is stabilized within 100 µs after power stabilizes before the following initialization sequence.
The CKE and DQM is driven to high between power stabilizes and the initialization sequence.
This SDRAM has VDD clamp diodes for CLK, CKE, address, /RAS, /CAS, /WE, /CS, DQM and DQ pins. If these
pins go high before power up, the large current flows from these pins to VDD through the diodes.
Initialization sequence
When 200 µs or more has past after the above power-up sequence, all banks must be precharged using the
precharge command (PALL). After tRP delay, set 8 or more auto refresh commands (REF). Set the mode register
set command (MRS) to initialize the mode register. We recommend that by keeping DQM and CKE to High, the
output buffer becomes High-Z during Initialization sequence, to avoid DQ bus contention on memory system formed
with a number of device.
Power up sequence
Initialization sequence
VDD, VDDQ
CKE, DQM
CLK
/CS, DQ
100 µs
0 V
Low
Low
Low
Power stabilize
Power-up sequence and Initialization sequence
200 µs
Data Sheet E0497E20 (Ver. 2.0)
23
EDS6432AFBH, EDS6432CFBH
Operation of the SDRAM
Read/Write Operations
Bank active
Before executing a read or write operation, the corresponding bank and the row address must be activated by the
bank active (ACT) command. An interval of tRCD is required between the bank active command input and the
following read/write command input.
Read operation
A read operation starts when a read command is input. Output buffer becomes Low-Z in the (/CAS Latency - 1)
cycle after read command set. The SDRAM can perform a burst read operation.
The burst length can be set to 1, 2, 4 and 8. The start address for a burst read is specified by the column address
and the bank select address at the read command set cycle. In a read operation, data output starts after the number
of clocks specified by the /CAS Latency. The /CAS Latency can be set to 2 or 3.
When the burst length is 1, 2, 4 and 8 the DOUT buffer automatically becomes High-Z at the next clock after the
successive burst-length data has been output.
The /CAS latency and burst length must be specified at the mode register.
CLK
tRCD
Command
ACT
READ
Address
DQ
CLK
Command
Address
DQ
BL = 1
BL = 2
BL = 4
BL = 8
CL = 2
CL = 3
ACT
Row
Row
tRCD
READ
Column
Column
out 0
out 0 out 1
out 0 out 1 out 2
out 0 out 1 out 2
out 0 out 1 out 2
out 0 out 1 out 2
/CAS Latency
out 3
out 4
out 5
out 3
Burst Length
out 6 out 7
out 3
out 3
CL = /CAS latency
Burst Length = 4
BL : Burst Length
/CAS Latency = 2
Data Sheet E0497E20 (Ver. 2.0)
24
EDS6432AFBH, EDS6432CFBH
Write operation
Burst write or single write mode is selected by the OPCODE of the mode register.
1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the
same clock as a write command set. (The latency of data input is 0 clock.) The burst length can be set to 1, 2, 4
and 8, like burst read operations. The write start address is specified by the column address and the bank select
address at the write command set cycle.
CLK
tRCD
Command
ACT
WRIT
Address
DQ
Row
BL = 1
BL = 2
BL = 4
BL = 8
Column
in 0
in 0
in 0
in 0
in 1
in 1
in 1
in 2
in 2
in 3
in 3
in 4
in 5
in 6 in 7
CL = 2, 3
Burst write
2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write
operation, data is only written to the column address and the bank select address specified by the write
command set cycle without regard to the burst length setting. (The latency of data input is 0 clock).
CLK
tRCD
Command
Address
DQ
ACT
Row
WRIT
Column
in 0
Single write
Data Sheet E0497E20 (Ver. 2.0)
25
EDS6432AFBH, EDS6432CFBH
Auto Precharge
Read with auto-precharge
In this operation, since precharge is automatically performed after completing a read operation, a precharge
command need not be executed after each read operation. The command executed for the same bank after the
execution of this command must be the bank active (ACT) command. In addition, an interval defined by lAPR is
required before execution of the next command.
[Clock cycle time]
/CAS latency Precharge start cycle
3 2 cycle before the final data is output
2 1 cycle before the final data is output
CLK
CL=2 Command
CL=3 Command
ACT
DQ
ACT
DQ
lRAS
lRAS
READA
READA
ACT
out3out2out1out0
lAPR
ACT
out3out2out1out0
Note: Internal auto-precharge starts at the timing indicated by " ".
And an interval of tRAS (lRAS) is required between previous active (ACT) command and internal precharge " ".
lAPR
Burst Read (BL = 4)
Write with auto-precharge
In this operation, since precharge is automatically performed after completing a burst write or single write operation,
a precharge command need not be executed after each write operation. The command executed for the same bank
after the execution of this command must be the bank active (ACT) command. In addition, an interval of lDAL is
required between the final valid data input and input of next command.
CLK
Command
ACT
WRITA
ACT
lRAS
DQ
in0 in1 in2 in3
lDAL
Note: Internal auto-precharge starts at the timing indicated by " ".
and an interval of tRAS (lRAS) is required between previous active (ACT) command
and internal precharge " ".
Burst Write (BL = 4)
Data Sheet E0497E20 (Ver. 2.0)
26
EDS6432AFBH, EDS6432CFBH
CLK
Command
Note: Internal auto-precharge starts at the timing indicated by " ".
ACT
lRAS
DQ
and an interval of tRAS (lRAS) is required between previous active (ACT) command
and internal precharge " ".
WRITA
in
Single Write
ACT
lDAL
Data Sheet E0497E20 (Ver. 2.0)
27
EDS6432AFBH, EDS6432CFBH
Burst Stop Command
During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus
goes to High-Z after the /CAS latency from the burst stop command.
CLK
Command
DQ
(CL = 2)
DQ
(CL = 3)
READ
BST
out outout
High-Z
out outout
High-Z
Burst Stop at Read
During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes
to High-Z at the same clock with the burst stop command.
CLK
Command
DQ
WRITE
in
in
in
in
BST
High-Z
Burst Stop at Write
Data Sheet E0497E20 (Ver. 2.0)
28
EDS6432AFBH, EDS6432CFBH
Command Intervals
Read command to Read command interval
1. Same bank, same ROW address: When another read command is executed at the same ROW address of the
same bank as the preceding read command execution, the second read can be performed after an interval of no
less than 1 clock. Even when the first command is a burst read that is not yet finished, the data read by the
second command will be valid.
CLK
Command
ACT
READ
READ
Address
Row
Column A
Column B
BS
DQ
Bank0
Active
Column =A
Read
Column =B
Read
out A0
Column =A
Dout
out B0
Column =B
Dout
out B1
out B2
CL = 3
BL = 4
Bank 0
out B3
READ to READ Command Interval (same ROW address in same bank)
2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive read
commands cannot be executed; it is necessary to separate the two read commands with a precharge command
and a bank active command.
3. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1
clock, provided that the other bank is in the bank active state. Even when the first command is a burst read that
is not yet finished, the data read by the second command will be valid.
CLK
Command
Address
ACT
Row 0
ACT
Row 1
READ
Column A
READ
Column B
BS
out B3
DQ
Bank0
Active
Bank3
Active
Bank0
Read
Bank3
Read
out A0
Bank0
Dout
out B0
Bank3
Dout
out B1
out B2
CL = 3
BL = 4
READ to READ Command Interval (different bank)
Data Sheet E0497E20 (Ver. 2.0)
29
EDS6432AFBH, EDS6432CFBH
Write command to Write command interval
1. Same bank, same ROW address: When another write command is executed at the same ROW address of the
same bank as the preceding write command, the second write can be performed after an interval of no less than
1 clock. In the case of burst writes, the second write command has priority.
CLK
Command
Address
ACT
Row
WRIT
Column A
WRIT
Column B
BS
DQ
Bank0
Active
in A0
Column =A
Write
in B0
Column =B
Write
in B1
in B2
Burst Write Mode
BL = 4
Bank 0
in B3
WRITE to WRITE Command Interval (same ROW address in same bank)
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be
executed; it is necessary to separate the two write commands with a precharge command and a bank active
command.
3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1
clock, provided that the other bank is in the bank active state. In the case of burst write, the second write
command has priority.
CLK
Command
Address
BS
ACT
Row 0
ACT
Row 1
WRIT
Column A
WRIT
Column B
DQ
Bank0
Active
in B1
in B2
Bank3
Active
in A0
Bank0
Write
in B0
Bank3
Write
in B3
WRITE to WRITE Command Interval (different bank)
Burst Write Mode
BL = 4
Data Sheet E0497E20 (Ver. 2.0)
30
EDS6432AFBH, EDS6432CFBH
Read command to Write command interval
1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same
bank as the preceding read command, the write command can be performed after an interval of no less than 1
clock. However, DQM must be set High so that the output buffer becomes High-Z before data input.
CLK
Command
READ
WRIT
CL=2
DQM
CL=3
DQ (input)
DQ (output)
in B0
High-Z
in B1
in B2
in B3
BL = 4
Burst write
READ to WRITE Command Interval (1)
CLK
Command
READ
WRIT
DQM
2 clock
CL=2
out out out
in
DQ
CL=3
out outinininininin
in
READ to WRITE Command Interval (2)
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be
executed; it is necessary to separate the two commands with a precharge command and a bank active
command.
3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1
cycle, provided that the other bank is in the bank active state. However, DQM must be set High so that the
output buffer becomes High-Z before data input.
Data Sheet E0497E20 (Ver. 2.0)
31
EDS6432AFBH, EDS6432CFBH
Write command to Read command interval:
1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same
bank as the preceding write command, the read command can be performed after an interval of no less than 1
clock. However, in the case of a burst write, data will continue to be written until one clock before the read
command is executed.
CLK
Command
DQM
DQ (input)
DQ (output)
CLK
Command
DQM
DQ (input)
WRIT READ
in A0
Column = A
Write
Column = B
Read
WRITE to READ Command Interval (1)
WRIT
in A0
Column = A
Write
in A1
WRITE to READ Command Interval (2)
READ
Column = B
Read
out B0
/CAS Latency
Column = B
Dout
out B0DQ (output)
/CAS Latency
Column = B
Dout
out B1 out B2 out B3
out B1 out B2 out B3
Burst Write Mode
CL = 2
BL = 4
Bank 0
Burst Write Mode
CL = 2
BL = 4
Bank 0
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be
executed; it is necessary to separate the two commands with a precharge command and a bank active
command.
3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1
clock, provided that the other bank is in the bank active state. However, in the case of a burst write, data will
continue to be written until one clock before the read command is executed (as in the case of the same bank and
the same address).
Data Sheet E0497E20 (Ver. 2.0)
32
EDS6432AFBH, EDS6432CFBH
Read with auto precharge to Read command interval
1. Different bank: When some banks are in the active state, the second read command (another bank) is executed.
Even when the first read with auto-precharge is a burst read that is not yet finished, the data read by the second
command is valid. The internal auto-precharge of one bank starts at the next clock of the second command.
CLK
Command
BS
READA READ
DQ
bank0
Read A
Note: Internal auto-precharge starts at the timing indicated by " ".
bank3
Read
out A0
out A1
out B0
out B1
CL= 3
BL = 4
Read with Auto Precharge to Read Command Interval (Different bank)
2. Same bank: The consecutive read command (the same bank) is illegal.
Write with auto precharge to Write command interval
1. Different bank: When some banks are in the active state, the second write command (another bank) is executed.
In the case of burst writes, the second write command has priority. The internal auto-precharge of one bank
starts 2 clocks later from the second command.
CLK
Command
BS
DQ
Note: Internal auto-precharge starts at the timing indicated by " ".
WRITA WRIT
in A0
bank0
Write A
in A1
in B0
bank3
Write
in B1
in B2
in B3
BL= 4
Write with Auto Precharge to Write Command Interval (Different bank)
2. Same bank: The consecutive write command (the same bank) is illegal.
Data Sheet E0497E20 (Ver. 2.0)
33
EDS6432AFBH, EDS6432CFBH
Read with auto precharge to Write command interval
1. Different bank: When some banks are in the active state, the second write command (another bank) is executed.
However, DQM must be set High so that the output buffer becomes High-Z before data input. The internal autoprecharge of one bank starts at the next clock of the second command.
CLK
Command
BS
READA WRIT
DQM
2. Same bank: The consecutive write command from read with auto precharge (the same bank) is illegal. It is
necessary to separate the two commands with a bank active command.
Write with auto precharge to Read command interval
1. Different bank: When some banks are in the active state, the second read command (another bank) is executed.
However, in case of a burst write, data will continue to be written until one clock before the read command is
executed. The internal auto-precharge of one bank starts at 2 clocks later from the second command.
Command
CL = 2
CL = 3
DQ (input)
DQ (output)
bank0
ReadA
Note: Internal auto-precharge starts at the timing indicated by " ".
Read with Auto Precharge to Write Command Interval (Different bank)
CLK
WRITA READ
BS
in B0
bank3
Write
in B1
High-Z
in B2
in B3
BL = 4
DQM
DQ (input)
DQ (output)
2. Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal. It is
necessary to separate the two commands with a bank active command.
Data Sheet E0497E20 (Ver. 2.0)
in A0
out B0
bank0
WriteA
Note: Internal auto-precharge starts at the timing indicated by " ".
Write with Auto Precharge to Read Command Interval (Different bank)
bank3
Read
34
out B1
out B2
out B3
CL = 3
BL = 4
EDS6432AFBH, EDS6432CFBH
Read command to Precharge command interval (same ban k)
When the precharge command is executed for the same bank as the read command that preceded it, the minimum
interval between the two commands is one clock. However, since the output buffer then becomes High-Z after the
clocks defined by lHZP, there is a case of interruption to burst read data output will be interrupted, if the precharge
command is input during burst read. To read all data by burst read, the clocks defined by lEP must be assured as
an interval from the final data output to precharge command execution.
CLK
Command
DQ
READ
out A0 out A1 out A2 out A3
CL=2
PRE/PALL
lEP = -1 cycle
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 2, BL = 4)
CLK
Command
DQ
READ
CL=3 lEP = -2 cycle
PRE/PALL
out A0 out A1 out A2 out A3
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 3, BL = 4)
CLK
Command
DQ
READ
PRE/PALL
out A0
High-Z
lHZP = 2
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 2, BL = 1, 2, 4, 8)
CLK
Command
DQ
READ
PRE/PALL
lHZP =3
out A0
High-Z
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 3, BL = 1, 2, 4, 8)
Data Sheet E0497E20 (Ver. 2.0)
35
EDS6432AFBH, EDS6432CFBH
Write command to Precharge command interval (same bank)
When the precharge command is executed for the same bank as the write command that preceded it, the minimum
interval between the two commands is 1 clock. However, if the burst write operation is unfinished, the input data
must be masked by means of DQM for assurance of the clock defined by tDPL.
CLK
Command
DQM
DQ
WRIT
in A0 in A1
PRE/PALL
in A2
tDPL
WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To stop write operation))
CLK
Command
DQM
DQ
WRIT
in A0 in A1 in A2
in A3
tDPL
PRE/PALL
WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To write all data))
Data Sheet E0497E20 (Ver. 2.0)
36
EDS6432AFBH, EDS6432CFBH
Bank active command interval
1. Same bank: The interval between the two bank active commands must be no less than tRC.
2. In the case of different bank active commands: The interval between the two bank active commands must be no
less than tRRD.
CLK
Command
Address
BS
ACT
ROW
Bank 0
Active
tRC
ACT
ROW
Bank 0
Active
Bank Active to Bank Active for Same Bank
CLK
Command
Address
BS
ACT
ROW:0
tRRD
Bank 0
Active
ACT
ROW:1
Bank 3
Active
Bank Active to Bank Active for Different Bank
Mode register set to Bank active command interval
The interval between setting the mode register and executing a bank active command must be no less than lMRD.
CLK
Command
Address
MRS
OPCODE
Mode
Register Set
lMRD
ACT
BS & ROW
Bank
Active
Mode register set to Bank active command interval
Data Sheet E0497E20 (Ver. 2.0)
37
EDS6432AFBH, EDS6432CFBH
DQM Control
The DQM mask the DQ data. The timing of DQM is different during reading and writing.
Reading
When data is read, the output buffer can be controlled by DQM. By setting DQM to Low, the output buffer becomes
Low-Z, enabling data output. By setting DQM to High, the output buffer becomes High-Z, and the corresponding
data is not output. However, internal reading operations continue. The latency of DQM during reading is 2 clocks.
Writing
Input data can be masked by DQM. By setting DQM to Low, data can be written. In addition, when DQM is set to
High, the corresponding data is not written, and the previous data is held. The latency of DQM during writing is 0
clock.
CLK
DQM
DQ
CLK
DQM
DQ
out 0 out 1
lDOD = 2 Latency
Reading
in 0 in 1
Writing
High-Z
lDID = 0 Latency
out 3
in 3
Data Sheet E0497E20 (Ver. 2.0)
38
EDS6432AFBH, EDS6432CFBH
Refresh
Auto-refresh
All the banks must be precharged before executing an auto-refresh command. Since the auto-refresh command
updates the internal counter every time it is executed and determines the banks and the ROW addresses to be
refreshed, external address specification is not required. The refresh cycles are required to refresh all the ROW
addresses within tREF (max.). The output buffer becomes High-Z after auto-refresh start. In addition, since a
precharge has been completed by an internal operation after the auto-refresh, an additional precharge operation by
the precharge command is not required.
Self-refresh
After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During selfrefresh operation, all ROW addresses are refreshed by the internal refresh timer. A self-refresh is terminated by a
self-refresh exit command. Before and after self-refresh mode, execute auto-refresh to all refresh addresses in or
within tREF (max.) period on the condition 1 and 2 below.
1. Enter self-refresh mode within time as below* after either burst refresh or distributed refresh at equal interval to
all refresh addresses are completed.
2. Start burst refresh or distributed refresh at equal interval to all refresh addresses within time as below*after
exiting from self-refresh mode.
Note: tREF (max.) / refresh cycles.
Others
Powe r-down mo de
The SDRAM enters power-down mode when CKE goes Low in the IDLE state. In power down mode, power
consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held
Low. In addition, by setting CKE to High, the SDRAM exits from the power down mode, and command input is
enabled from the next clock. In this mode, internal refresh is not performed.
Clock suspend mode
By driving CKE to Low during a bank active or read/write operation, the SDRAM enters clock suspend mode. During
clock suspend mode, external input signals are ignored and the internal state is maintained. When CKE is driven
High, the SDRAM terminates clock suspend mode, and command input is enabled from the next clock. For details,
refer to the "CKE Truth Table".
Data Sheet E0497E20 (Ver. 2.0)
39
Timing Waveforms
Read Cycle
CLK
CKE
/CS
/RAS
/CAS
/WE
A10
Address
DQM
VIH
BS
tCH t
tHItSI
tHItSI
tHItSI
tHItSI
tHItSI
tHItSI
tHItSI
tCK
CL
tRCD
EDS6432AFBH, EDS6432CFBH
tRC
tRAS
tHItSI
tHItSI
tHItSI
tHItSI
tHItSI
tHItSI
tHItSI
tHI
tSI
tHItSI
tHItSI
tHItSI
tHItSI
tHItSI
tHItSI
t
RP
tHItSI
tHItSI
tHItSI
tHItSI
tHItSI
tHItSI
tHItSI
DQ (input)
DQ (output)
Bank 0
Active
Bank 0
Read
t
AC
t
AC
t
LZ
t
OH
t
OH
t
AC
t
t
OH
Bank 0
Precharge
t
AC
HZ
t
OH
/CAS latency = 2
Burst length = 4
Bank 0 access
= VIH or VIL
= VOH or VOL
Data Sheet E0497E20 (Ver. 2.0)
40
Write Cycle
/RAS
/CAS
Address
DQM
DQ (input)
DQ (output)
CLK
CKE
/CS
/WE
BS
A10
VIH
tCK
tCH t
CL
tRCD
tHItSI tHItSI
tHItSI
tHItSI
tHItSI
tHItSI
tHItSI
tHItSI
tHItSI
tHItSI
tHItSI
tHItSI
tHItSI
tHI
tSI
tSI
tHI tHItSItSI tSItSI
tRC
tRAS
tHI
tHI tHI
EDS6432AFBH, EDS6432CFBH
tRP
tHItSI tHItSI
tHItSI tHItSI
tHItSI tHItSI
tHItSI
tHItSI
tHItSI
tDPL
tHItSI
tHItSI
tHItSI
tHItSI
Bank 0
Active
Mode Register Set Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLK
/CS
/WE
BS
VIH
Precharge
If needed
valid
CKE
/RAS
/CAS
Address
DQM
DQ (output)
DQ (input)
code
Mode
register
Set
Bank 0
Write
lMRD
R: b
Bank 3
Active
Bank 0
Precharge
C: b
High-Z
lRCDlRP
Bank 3
Read
Output mask
C: b’
b b+3 b’ b’+1 b’+2 b’+3
CL = 2
BL = 4
Bank 0 access
= VIH or VIL
lRCD = 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
Data Sheet E0497E20 (Ver. 2.0)
41
Read Cycle/Write Cycle
CLK
CKE
/CS
/RAS
/CAS
/WE
BS
Address
DQM
DQ (output)
DQ (input)
CKE
/CS
/RAS
/CAS
/WE
BS
Address
DQM
DQ (output)
DQ (input)
Read/Single Write Cycle
CLK
CKE
/RAS
/CAS
/WE
Address
DQM
DQ (input)
DQ (output)
CKE
/RAS
/CAS
/WE
Address
DQM
DQ (input)
DQ (output)
0 1 2 3 4 5 6 7 8 9 1011121314151617181920
VIH
R:a C:a R:b C:b C:b' C:b"
Bank 0
Active
VIH
R:a C:a R:b C:b C:b' C:b"
Bank 0
Active
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
V
IH
/CS
BS
R:a C:a R:b C:a'
Bank 0
Active
V
IH
/CS
BS
R:a C:a C:a
Bank 0
Active
EDS6432AFBH, EDS6432CFBH
a a+1 a+2 a+3 b b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3
Bank 0
Read
Bank 3
Active
Bank 3
Read
a a+1 a+2 a+3 b b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2b"+3
Bank 0
Write
Bank 3
Active
Bank 3
Write
a
Bank 0
Read
Bank 3
Active
R:b
a
Bank 0
Read
Bank 3
Active
High-Z
Bank 0
Precharge
High-Z
Bank 0
Precharge
a+1 a+2 a+3
a+1 a+3
Bank 3
Read
Bank 3
Write
a
Bank 0
Write
a
Bank 0
Write
Bank 3
Read
Bank 3
Write
C:a
Bank 0
Read
C:b
bc
Bank 0
Bank 0
Write
Write
Bank 3
Precharge
Bank 3
Precharge
a a+1 a+2 a+3
C:c
Read cycle
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
=
VIH or VIL
Write cycle
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
Bank 0
Precharge
Bank 0
Precharge
Bank 3
Precharge
Read/Single write
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
=
VIH or VIL
Data Sheet E0497E20 (Ver. 2.0)
42
Read/Burst Write Cycle
CLK
CKE
/CS
/RAS
/CAS
/WE
BS
Address
DQM
DQ (input)
DQ (output)
CKE
/CS
/RAS
/CAS
/WE
BS
Address
DQM
DQ (input)
DQ (output)
Auto Refresh Cycle
CLK
CKE
/CS
/RAS
/CAS
/WE
BS
Address
DQM
DQ (input)
DQ (output)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
R:a C:a R:b C:a'
Bank 0
Active
VIH
R:a C:a C:a
Bank 0
Active
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
VIH
A10=1
Precharge
If needed
t
RP
Bank 0
Read
Bank 0
Read
Auto Refresh
a
Bank 3
Active
R:b
a a+3
Bank 3
Active
t
RC
a+1 a+2 a+3
Clock
suspend
a+1
High-Z
Auto Refresh
EDS6432AFBH, EDS6432CFBH
a a+1 a+2 a+3
Bank 0
Write
a a+1 a+2 a+3
Bank 0
Write
t
RC
Active
Bank 0
R:a
Bank 0
Precharge
Bank 0
Precharge
Read/Burst write
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
=
C:a
Refresh cycle and
Read
Read cycle
Bank 0
/RAS-/CAS delay = 2
/CAS latency = 2
Burst length = 4
= VIH or VIL
Bank 3
Precharge
VIH or VIL
20
19
a a+1
Data Sheet E0497E20 (Ver. 2.0)
43
Self Refresh Cycle
EDS6432AFBH, EDS6432CFBH
CLK
CKE
/CS
/RAS
/CAS
/WE
BS
Address
A10=1
DQM
DQ (input)
DQ (output)
Precharge command
If needed
Clock Suspend Mode
CLK
CKE
/CS
/RAS
/CAS
/WE
BS
Address
DQM
DQ (output)
DQ (input)
CKE
/CS
/RAS
/CAS
/WE
BS
Address
DQM
DQ (output)
DQ (input)
01234 5 6 7 8 9 1011121314151617181920
R:a C:a R:b
Bank0
Active
R:a C:a
Bank0
Active
t
RP
Active clock
suspend start
Active clock
suspend start
CKE Low
Self refresh entry
command
tSI tSI
tHI
a a+1 a+2 a+3 b b+1 b+2
Bank0
Active clock
suspend end
Read
Bank3
Active
R:b
a a+1
a+2
Bank0
Write
Bank3
Active
Active clock
supend end
lSREX
Self refresh exit
ignore command
or No operation
Read suspend
High-Z
Write suspend
start
start
High-Z
t
RC
High-Z
Read suspend
a+3
Write suspend
Next
Self refresh entry
clock
command
enable
C:b
Bank3
end
Read
C:b
b b+1 b+2 b+3
Bank0
Bank3
Precharge
end
Write
Bank0
Precharge
t
RC
Next
clock
enable
b+3
Earliest Bank3
Precharge
Earliest Bank3
Precharge
Self refresh cycle
Auto
refresh
/RAS-/CAS delay = 3
CL = 3
BL = 4
=
Read cycle
/RAS-/CAS delay = 2
/CAS latency = 2
Burst length = 4
= VIH or VIL
Write cycle
/RAS-/CAS delay = 2
/CAS latency = 2
Burst length = 4
= VIH or VIL
VIH or VIL
Data Sheet E0497E20 (Ver. 2.0)
44
Power Down Mode
CLK
CKE
/CS
/RAS
/CAS
/WE
BS
EDS6432AFBH, EDS6432CFBH
CKE Low
Address
DQM
DQ (input)
DQ (output)
Initialization Sequence
CLK
CKE
/CS
/RAS
/CAS
/WE
Address
DQM
DQ
VIH
V
IH
All banks
Precharge
A10=1
RPt
Precharge command
If needed
0123456
valid
tRP
Auto Refresh
Power down entry
t
RC
High-Z
Power down
mode exit
78910
Auto Refresh
R: a
Active Bank 0
48 49 50 51
High-Z
t
RC
Power down cycle
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
52
code
lMRD
Mode register
Set
53
54
Valid
Bank active
If needed
55
Data Sheet E0497E20 (Ver. 2.0)
45
Package Drawing
90-ball FBGA
Solder ball: Lead free (Sn-Ag-Cu)
0.2
SA
8.0 ± 0.1
EDS6432AFBH, EDS6432CFBH
Unit: mm
SB
0.2
13.0 ± 0.1
0.8
INDEX AREA
S
0.1
S
0.2
1.14 max.
S
0.35 ± 0.05
B
90-φ0.45 ± 0.05
φ0.08
MSAB
A
INDEX MARK
1.6
Data Sheet E0497E20 (Ver. 2.0)
0.8
0.8
0.9
ECA-TS2-0096-01
46
EDS6432AFBH, EDS6432CFBH
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the EDS6432AFBH and EDS6432CFBH.
Type of Surface Mount Device
EDS6432AFBH, EDS6432CFBH: 90-ball FBGA < Lead free (Sn-Ag-Cu) >
Data Sheet E0497E20 (Ver. 2.0)
47
EDS6432AFBH, EDS6432CFBH
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to V
DD
or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
Data Sheet E0497E20 (Ver. 2.0)
48
EDS6432AFBH, EDS6432CFBH
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E0107
Data Sheet E0497E20 (Ver. 2.0)
49
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