ELPIDA EDD5104ADTA, EDD5108ADTA, EDD5116ADTA DATA SHEET
查询EDD5104ADTA供应商查询EDD5104ADTA供应商
EDD5104ADTA (128M words ×××× 4 bits)
EDD5108ADTA (64M words ×××× 8 bits)
EDD5116ADTA (32M words ×××× 16 bits)
DATA SHEET
512M bits DDR SDRAM
Description
The EDD5104AD, the EDD5108AD and the
EDD5116AD are 512M bits Double Data Rate (DDR)
SDRAM. Read and write operations are performed at
the cross points of the CK and the /CK. This highspeed data transfer is realized by the 2 bits prefetchpipelined architecture. Data strobe (DQS) both for
read and write are available for high speed and reliable
data bus design. By setting extended mode register,
the on-chip Delay Locked Loop (DLL) can be set
enable or disable. It is packaged in standard 66-pin
plastic TSOP (II).
Features
• Power supply: VDD, VDDQ = 2.5V ± 0.2V
• Data Rate: 333Mbps/266Mbps (max.)
• Double Data Rate architecture; two data transfers per
clock cycle
• Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
• Data inputs, outputs, and DM are synchronized with
DQS
• 4 internal banks for concurrent operation
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Auto precharge option for each burst access
• SSTL_2 compatible I/O
• Programmable burst length (BL): 2, 4, 8
• Programmable /CAS latency (CL): 2, 2.5
• Programmable output driver strength: normal/weak
• Refresh cycles: 8192 refresh cycles/64ms
7.8µs maximum average periodic refresh interval
• 2 variations of refresh
Auto refresh
Self refresh
Document No. E0384E30 (Ver. 3.0)
Date Published January 2004 (K) Japan
URL: http://www.elpida.com
Pin Configurations
/xxx indicates active low signal.
66-pin Plastic TSOP(II)
VDD
VDD
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10(AP)
A0
A1
A2
A3
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10(AP)
A0
A1
A2
A3
VDD
A0 to A12
BA0, BA1
DQ0 to DQ15
DQS, LDQS, UDQS
/CS
/RAS
/CAS
/WE
DM, LDM, UDM
CK
/CK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10(AP)
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A0
29
A1
30
A2
31
A3
32
33
X 16
X 8
X 4
(Top view)
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
66
VSS
65
DQ15
64
VSSQ
63
DQ14
62
DQ13
61
VDDQ
60
DQ12
59
DQ11
58
VSSQ
57
DQ10
56
DQ9
55
VDDQ
54
DQ8
53
NC
52
VSSQ
51
UDQS
50
NC
49
VREF
48
VSS
47
UDM
46
/CK
45
CK
44
CKE
43
NC
42
A12
41
A11
40
A9
39
A8
38
A7
37
A6
36
A5
35
A4
34
VSS
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
Elpida Memory, Inc. 2003-2004
Ordering Information
Part number
EDD5104ADTA-6B
EDD5104ADTA-7A
EDD5104ADTA-7B
EDD5108ADTA-6B
EDD5108ADTA-7A
EDD5108ADTA-7B
EDD5116ADTA-6B
EDD5116ADTA-7A
EDD5116ADTA-7B
EDD5104ADTA-6BL
EDD5104ADTA-7AL
EDD5104ADTA-7BL
EDD5108ADTA-6BL
EDD5108ADTA-7AL
EDD5108ADTA-7BL
EDD5116ADTA-6BL
EDD5116ADTA-7AL
EDD5116ADTA-7BL
Part Number
Mask
version
D 128M × 4 4
64M × 8
32M × 16
D 128M × 4 4
64M × 8
32M × 16
EDD5104ADTA, EDD5108ADTA, EDD5116ADTA
Organization
(words × bits)
Internal
banks
Data rate
Mbps (max.)
333
266
266
333
266
266
333
266
266
333
266
266
333
266
266
333
266
266
JEDEC speed bin
(CL-tRCD-tRP)
DDR333B (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
DDR333B (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
DDR333B (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
DDR333B (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
DDR333B (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
DDR333B (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
Package
66-pin Plastic
TSOP (II)
Elpida Memory
Type
D: Monolithic Device
Product Code
D: DDR SDRAM
Density / Bank
51: 512M / 4-bank
Bit Organization
04: x4
08: x8
16: x16
Voltage, Interface
A: 2.5V, SSTL_2
Die Rev.
Package
TA: TSOP (II)
Speed
6B: DDR333B (2.5-3-3)
7A: DDR266A (2-3-3)
7B: DDR266B (2.5-3-3)
E D D 51 04 A D TA - 6B L
Power Consumption
Blank: Normal
L: Low Power
Data Sheet E0384E30 (Ver. 3.0)
2
CONTENTS
EDD5104ADTA, EDD5108ADTA, EDD5116ADTA
Description.....................................................................................................................................................1
Features.........................................................................................................................................................1
Pin Configurations .........................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Electrical Specifications.................................................................................................................................4
Block Diagram .............................................................................................................................................10
Pin Function.................................................................................................................................................11
Command Operation ...................................................................................................................................13
Simplified State Diagram .............................................................................................................................20
Operation of the DDR SDRAM ....................................................................................................................21
Timing Waveforms.......................................................................................................................................40
Package Drawing ........................................................................................................................................46
Recommended Soldering Conditions ..........................................................................................................47
Data Sheet E0384E30 (Ver. 3.0)
3
EDD5104ADTA, EDD5108ADTA, EDD5116ADTA
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 200 µs and then, execute power on sequence and CBR (Auto) refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter Symbol Rating Unit Note
Voltage on any pin relative to VSS VT –1.0 to +3.6 V
Supply voltage relative to VSS VDD –1.0 to +3.6 V
Short circuit output current IOS 50 mA
Power dissipation PD 1.0 W
Operating ambient temperature TA 0 to +70 °C
Storage temperature Tstg –55 to +125 °C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to +70°°°°C)
Parameter Symbol min typ max Unit Notes
Supply voltage
Input reference voltage VREF 0.49 × VDDQ 0.50 × VDDQ 0.51 × VDDQ V
Termination voltage VTT VREF – 0.04 VREF VREF + 0.04 V
Input high voltage VIH (DC) VREF + 0.15 — VDDQ + 0.3 V 2
Input low voltage VIL (DC) –0.3 — VREF – 0.15 V 3
Input voltage level,
CK and /CK inputs
Input differential cross point
voltage, CK and /CK inputs
Input differential voltage,
CK and /CK inputs
VDD,
VDDQ
VSS,
VSSQ
VIN (DC) –0.3 — VDDQ + 0.3 V 4
VIX (DC) 0.5 × VDDQ − 0.2V 0.5 × VDDQ 0.5 × VDDQ + 0.2V V
VID (DC) 0.36 — VDDQ + 0.6 V 5, 6
2.3 2.5 2.7 V 1
0 0 0 V
Notes: 1. VDDQ must be lower than or equal to VDD.
2. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns.
3. VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns.
4. VIN (DC) specifies the allowable DC execution of each differential input.
5. VID (DC) specifies the input differential voltage required for switching.
6. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V
if measurement.
Data Sheet E0384E30 (Ver. 3.0)
4
EDD5104ADTA, EDD5108ADTA, EDD5116ADTA
DC Characteristics 1 (TA = 0 to +70°°°°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
max.
Parameter Symbol Grade × 4 × 8 × 16 Unit Test condition Notes
Operating current (ACTPRE)
Operating current
(ACT-READ-PRE)
Idle power down standby
current
Floating idle standby
current
Quiet idle standby current IDD2Q 20 20 20 mA
Active power down
standby current
Active standby current IDD3N
Operating current
(Burst read operation)
Operating current
(Burst write operation)
Auto Refresh current IDD5
Self refresh current IDD6 4 4 4 mA
Self refresh current
((L-version))
Operating current
(4 banks interleaving)
IDD0
IDD1
IDD2P 3 3 3 mA CKE ≤ VIL 4
IDD2F
IDD3P 20 20 20 mA CKE ≤ VIL 3
IDD4R
IDD4W
IDD6 -xxL 3 3 3 mA
IDD7A
Notes: 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one clock cycle.
6. DQ, DM and DQS transition twice per one clock cycle.
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once every two clock cycles.
10. Command/Address stable at ≥ VIH or ≤ VIL.
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
150
135
190
170
30
25
65
55
230
200
230
200
320
300
490
410
150
135
200
175
30
25
65
55
250
210
250
210
320
300
510
430
150
135
210
180
30
25
65
55
270
230
270
230
320
300
530
450
CKE ≥ VIH,
mA
tRC = tRC (min.)
CKE ≥ VIH, BL = 4,
mA
CL = 2.5,
tRC = tRC (min.)
CKE ≥ VIH, /CS ≥ VIH,
mA
DQ, DQS, DM = VREF
CKE ≥ VIH, /CS ≥ VIH,
DQ, DQS, DM = VREF
CKE ≥ VIH, /CS ≥ VIH
mA
tRAS = tRAS (max.)
CKE ≥ VIH, BL = 2,
mA
CL = 2.5
CKE ≥ VIH, BL = 2,
mA
CL = 2.5
tRFC = tRFC (min.),
mA
Input ≤ VIL or ≥ VIH
Input ≥ VDD – 0.2 V
Input ≤ 0.2 V
mA BL = 4 1, 5, 6, 7
1, 2, 9
1, 2, 5
4, 5
4, 10
3, 5, 6
1, 2, 5, 6
1, 2, 5, 6
DC Characteristics 2 (TA = 0 to +70°°°°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
Parameter Symbol min. max. Unit Test condition Notes
Input leakage current ILI –2 2 µA VDD ≥ VIN ≥ VSS
Output leakage current ILO –5 5 µA VDDQ ≥ VOUT ≥ VSS
Output high current IOH –15.2 — mA VOUT = 1.95V
Output low current IOL 15.2 — mA VOUT = 0.35V
Data Sheet E0384E30 (Ver. 3.0)
5
EDD5104ADTA, EDD5108ADTA, EDD5116ADTA
Pin Capacitance (TA = +25°C, VDD, VDDQ = 2.5V ± 0.2V)
Parameter Symbol Pins min. typ max. Unit Notes
Input capacitance CI1 CK, /CK 2.0 — 3.0 pF 1
CI2 All other input pins 2.0 — 3.0 pF 1
Delta input capacitance Cdi1 CK, /CK — — 0.25 pF 1
Cdi2 All other input-only pins — — 0.5 pF 1
Data input/output capacitance CI/O DQ, DM, DQS 4.0 — 5 pF 1, 2,
Delta input/output capacitance Cdio DQ, DM, DQS — — 0.5 pF 1
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VDDQ/2, ∆VOUT = 0.2V,
TA = +25°C.
2. DOUT circuits are disabled.
AC Characteristics (TA = 0 to +70°°°°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
-6B -7A -7B
Parameter Symbol
Clock cycle time
(CL = 2)
(CL = 2.5) tCK 6 12 7.5 12 7.5 12 ns
CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK
CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK
CK half period tHP
DQ output access time from CK, /CK tAC –0.7 0.7 –0.75 0.75 –0.75 0.75 ns 2, 11
DQS output access time from CK,
/CK
DQS to DQ skew tDQSQ — 0.45 — 0.5 — 0.5 ns 3
DQ/DQS output hold time from DQS tQH tHP – tQHS — tHP – tQHS — tHP – tQHS — ns
Data hold skew factor tQHS — 0.55 — 0.75 — 0.75 ns
Data-out high-impedance time from
CK, /CK
Data-out low-impedance time from
CK, /CK
Read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK
Read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK
DQ and DM input setup time tDS 0.45 — 0.5 — 0.5 — ns 8
DQ and DM input hold time tDH 0.45 — 0.5 — 0.5 — ns 8
DQ and DM input pulse width tDIPW 1.75 — 1.75 — 1.75 — ns 7
Write preamble setup time tWPRES 0 — 0 — 0 — ns
Write preamble tWPRE 0.25 — 0.25 — 0.25 — tCK
Write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK 9
Write command to first DQS latching
transition
DQS falling edge to CK setup time tDSS 0.2 — 0.2 — 0.2 — tCK
DQS falling edge hold time from CK tDSH 0.2 — 0.2 — 0.2 — tCK
DQS input high pulse width tDQSH 0.35 — 0.35 — 0.35 — tCK
DQS input low pulse width tDQSL 0.35 0.35 — 0.35 — tCK
tCK 7.5 12 7.5 12 10 12 ns 10
tDQSCK –0.6 0.6 –0.75 0.75 –0.75 0.75 ns 2, 11
tHZ –0.7 0.7 –0.75 0.75 –0.75 0.75 ns 5, 11
tLZ –0.7 0.7 –0.75 0.75 –0.75 0.75 ns 6, 11
tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK
min. max. min. max min. max.
min
(tCH, tCL)
—
min
(tCH, tCL)
—
min
(tCH, tCL)
— tCK
Unit Notes
Address and control input setup time tIS 0.75 — 0.9 — 0.9 — ns 8
Address and control input hold time tIH 0.75 — 0.9 — 0.9 — ns 8
Data Sheet E0384E30 (Ver. 3.0)
6
EDD5104ADTA, EDD5108ADTA, EDD5116ADTA
-6B -7A -7B
Parameter Symbol
Address and control input pulse width tIPW 2.2 — 2.2 — 2.2 — ns 7
Mode register set command cycle
time
Active to Precharge command period tRAS 42 120000 45 120000 45 120000 ns
Active to Active/Auto refresh
command period
Auto refresh to Active/Auto refresh
command period
Active to Read/Write delay tRCD 18 — 20 — 20 — ns
Precharge to active command period tRP 18 — 20 — 20 — ns
Active to Autoprecharge delay tRAP tRCD min. — tRCD min. — tRCD min. — ns
Active to active command period tRRD 12 — 15 — 15 — ns
Write recovery time tWR 15 — 15 — 15 — ns
Auto precharge write recovery and
precharge time
Internal write to Read command
delay
Average periodic refresh interval tREF — 7.8 — 7.8 — 7.8 µs
tMRD 2 — 2 — 2 — tCK
tRC 60 — 65 — 65 — ns
tRFC 72 — 75 — 75 — ns
tDAL
tWTR 1 — 1 — 1 — tCK
Notes: 1. On all AC measurements, we assume the test conditions shown in the next page. For timing parameter
definitions, see ‘Timing Waveforms’ section.
2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal
transition is defined to occur when the signal level crossing VTT.
3. The timing reference level is VTT.
4. Output valid window is defined to be the period between two successive transition of data out or DQS
(read) signals. The signal transition is defined to occur when the signal level crossing VTT.
5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The
timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage
level, but specify when the device output stops driving.
6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This
parameter is not referred to a specific DOUT voltage level, but specify when the device output begins
driving.
7. Input valid windows is defined to be the period between two successive transition of data input or DQS
(write) signals. The signal transition is defined to occur when the signal level crossing VREF.
8. The timing reference level is VREF.
9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific
reference voltage to judge this transition is not given.
10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not
assured.
11. tCK = tCK (min.) when these parameters are measured. Otherwise, absolute minimum values of these
values are 10% of tCK.
12. VDD is assumed to be 2.5V ± 0.2V. VDD power supply variation per cycle expected to be less than
0.4V/400 cycle.
13. tDAL = (tWR/tCK)+(tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer.
Example: For –7A Speed at CL = 2.5, tCK = 7.5ns, tWR = 15ns and tRP= 20ns,
tDAL = (15ns/7.5ns) + (20ns/7.5ns) = (2) + (3)
tDAL = 5 clocks
min. max. min. max min. max.
(tWR/tCK)+
(tRP/tCK)
(tWR/tCK)+
(tRP/tCK)
—
(tWR/tCK)+
(tRP/tCK)
— tCK 13
Unit Notes
Data Sheet E0384E30 (Ver. 3.0)
7
EDD5104ADTA, EDD5108ADTA, EDD5116ADTA
Test Conditions
Parameter Symbol Value Unit
Input reference voltage VREF VDDQ/2 V
Termination voltage VTT VREF V
Input high voltage VIH (AC) VREF + 0.31 V
Input low voltage VIL (AC) VREF − 0.31 V
Input differential voltage, CK and /CK
inputs
Input differential cross point voltage,
CK and /CK inputs
Input signal slew rate SLEW 1 V/ns
CK
/CK
VID (AC) 0.62 V
VIX (AC) VREF V
VID
tCL
tCK
tCH
VDD
VREF
VSS
VIX
VDD
VIH
VIL
∆t
SLEW = (VIH (AC) – VIL (AC))/∆t
VTT
Measurement point
RT = 50Ω
DQ
CL = 30pF
Input Waveforms and Output Load
VREF
VSS
Data Sheet E0384E30 (Ver. 3.0)
8
EDD5104ADTA, EDD5108ADTA, EDD5116ADTA
Timing Parameter Measured in Clock Cycle
Number of clock cycle
tCK 6ns 7.5ns
Parameter Symbol min. max. min. max. Unit
Write to pre-charge command delay (same bank) tWPD 4 + BL/2 — 3 + BL/2 — tCK
Read to pre-charge command delay (same bank) tRPD BL/2 — BL/2 — tCK
Write to read command delay (to input all data) tWRD 2 + BL/2 — 2 + BL/2 — tCK
Burst stop command to write command delay
(CL = 2)
(CL = 2.5) tBSTW 3 — 3 — tCK
Burst stop command to DQ High-Z
(CL = 2)
(CL = 2.5) tBSTZ 2.5 2.5 2.5 2.5 tCK
Read command to write command delay
(to output all data)
(CL = 2)
(CL = 2.5) tRWD 3 + BL/2 — 3 + B L/2 — tCK
Pre-charge command to High-Z
(CL = 2)
(CL = 2.5) tHZP 2.5 2.5 2.5 2.5 tCK
Write command to data in latency tWCD 1 1 1 1 tCK
Write recovery time tWR 3 — 2 — tCK
DM to data in latency tDMD 0 0 0 0 tCK
Mode register set command cycle time tMRD 2 — 2 — tCK
Self refresh exit to non-read command tSNR 12 — 10 — tCK
Self refresh exit to read command tSRD 200 — 200 — tCK
Power down entry tPDEN 1 1 1 1 tCK
Power down exit to command input tPDEX 1 — 1 — tCK
tBSTW — — 2 — tCK
tBSTZ — — 2 2 tCK
tRWD — — 2 + BL/2 — tCK
tHZP — — 2 2 tCK
Data Sheet E0384E30 (Ver. 3.0)
9
Block Diagram
CK
/CK
CKE
Clock
generator
EDD5104ADTA, EDD5108ADTA, EDD5116ADTA
Bank 3
Bank 2
Bank 1
A0 to A12, BA0, BA1
/RAS
/CAS
/CS
/WE
Mode
register
Control logic
Command decoder
Row
address
buffer
and
refresh
counter
Column
address
buffer
and
burst
counter
CK, /CK
DLL
Memory cell array
Row decoder
Sense amp.
Column decoder
Data control circuit
Latch circuit
Input & Output buffer
Bank 0
DQS
DM
DQ
Data Sheet E0384E30 (Ver. 3.0)
10
EDD5104ADTA, EDD5108ADTA, EDD5116ADTA
Pin Function
CK, /CK (input pins)
The CK and the /CK are the master clock inputs. All inputs except DM, DQS and DQs are referred to the cross point
of the CK rising edge and the /CK falling edge. When a read operation, DQS and DQs are referred to the cross point
of the CK and the /CK. When a write operation, DQS and DQs are referred to the cross point of the DQS and the
VREF level. DQS for write operation is referred to the cross point of the CK and the /CK. CK is the master clock
input to this pin. The other input signals are referred at CK rising edge.
/CS (input pin)
When /CS is Low, commands and data can be input. When /CS is High, all inputs are ignored. However, internal
operations (bank active, burst operations, etc.) are held.
/RAS, /CAS, and /WE (input pins)
These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.
See "Command operation".
A0 to A12 (input pins)
Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the
/CK falling edge in a bank active command cycle. Column address (See “Address Pins Table”) is loaded via the A0
to the A9, A11 and A12 at the cross point of the CK rising edge and the /CK falling edge in a read or a write
command cycle. This column address becomes the starting address of a burst operation.
[Address Pins Table]
Address (A0 to A12)
Part number Row address Column address
EDD5104AD AX0 to AX12 AY0 to AY9, AY11, AY12
EDD5108AD AX0 to AX12 AY0 to AY9, AY11
EDD5116AD AX0 to AX12 AY0 to AY9
A10 (AP) (input pin)
A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If
A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low when a precharge
command is issued, only the bank that is selected by BA1/BA0 is precharged. If A10 = High when read or write
command, auto-precharge function is enabled. While A10 = Low, auto-precharge function is disabled.
BA0 and BA1 (input pins)
BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See
Bank Select Signal Table)
[Bank Select Signal Table]
BA0 BA1
Bank 0 L L
Bank 1 H L
Bank 2 L H
Bank 3 H H
Remark: H: VIH. L: VIL
Data Sheet E0384E30 (Ver. 3.0)
11
EDD5104ADTA, EDD5108ADTA, EDD5116ADTA
CKE (input pin)
This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge is valid. If CKE is
Low. CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when
the CKE is driven Low and exited when it resumes to High. CKE must be maintained high throughout read or write
access.
The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge
and the /CK falling edge with proper setup time tIS, by the next CK rising edge CKE level must be kept with proper
hold time tIH.
DM, LDM and UDM (input pins)
DMs are the reference signal of the data input mask function. DMs are sampled at the cross point of DQS and
VREF. DMs provide the byte mask function. When DM = High, the data input at the same timing are masked while
the internal burst counter will be count up. In ×16 products, LDM controls the lower byte (DQ0 to DQ7) and UDM
controls the upper byte (DQ8 to DQ15) of write data.
DQ0 to DQ15 (input/output pins)
Data is input to and output from these pins (DQ0 to DQ3; EDD5104AD, DQ0 to DQ7; EDD5108AD, DQ0 to DQ15;
EDD5116AD).
DQS, LDQS and UDQS (input and output pins)
DQS provides the read data strobes (as output) and the write data strobes (as input). In ×16 products, LDQS is the
lower byte (DQ0 to DQ7) data strobe signal, UDQS is the upper byte (DQ8 to DQ15) data strobe signal.
VDD, VSS, VDDQ, VSSQ (Power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
buffers.
Data Sheet E0384E30 (Ver. 3.0)
12
EDD5104ADTA, EDD5108ADTA, EDD5116ADTA
Command Operation
Command Truth Table
DDR SDRAM recognize the following commands specified by the /CS, /RAS, /CAS, /WE and address pins. All other
combinations than those in the table below are illegal.
CKE
Command Symbol n – 1 n /CS /RAS /CAS /WE BA1 BA0 AP Address
Ignore command DESL H H H × × × × × × ×
No operation NOP H H L H H H × × × ×
Burst stop in read command BST H H L H H L × × × ×
Column address and read command READ H H L H L H V V L V
Read with auto-precharge READA H H L H L H V V H V
Column address and write command WRIT H H L H L L V V L V
Write with auto-precharge WRITA H H L H L L V V H V
Row address strobe and bank active ACT H H L L H H V V V V
Precharge select bank PRE H H L L H L V V L ×
Precharge all bank PALL H H L L H L × × H ×
Refresh REF H H L L L H × × × ×
SELF H L L L L H × × × ×
Mode register set MRS H H L L L L L L L V
EMRS H H L L L L L H L V
Remark: H: VIH. L: VIL. ×: VIH or VIL V: Valid address input
Note: The CKE level must be kept for 1 CK cycle at least.
Ignore command [DESL]
When /CS is High at the cross point of the CK rising edge and the VREF level, every input are neglected and internal
status is held.
No operation [NOP]
As long as this command is input at the cross point of the CK rising edge and the VREF level, address and data
input are neglected and internal status is held.
Burst stop in read operation [BST]
This command stops a burst read operation, which is not applicable for a burst write operation.
Column address strobe and read command [READ]
This command starts a read operation. The start address of the burst read is determined by the column address
(See “Address Pins Table” in Pin Function) and the bank select address. After the completion of the read operation,
the output buffer becomes High-Z.
Read with auto-precharge [READA]
This command starts a read operation. After completion of the read operation, precharge is automatically executed.
Column address strobe and write command [WRIT]
This command starts a write operation. The start address of the burst write is determined by the column address
(See “Address Pins Table” in Pin Function) and the bank select address.
Write with auto-precharge [WRITA]
This command starts a write operation. After completion of the write operation, precharge is automatically executed.
Data Sheet E0384E30 (Ver. 3.0)
13
EDD5104ADTA, EDD5108ADTA, EDD5116ADTA
Row address strobe and bank activate [ACT]
This command activates the bank that is selected by BA0, BA1 and determines the row address (AX0 to AX12).
(See Bank Select Signal Table)
Precharge selected bank [PRE]
This command starts precharge operation for the bank selected by BA0, BA1. (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0 BA1
Bank 0 L L
Bank 1 H L
Bank 2 L H
Bank 3 H H
Remark: H: VIH. L: VIL
Precharge all banks [PALL]
This command starts a precharge operation for all banks.
Refresh [REF/SELF]
This command starts a refresh operation. There are two types of refresh operation, one is auto-refresh, and another
is self-refresh. For details, refer to the CKE truth table section.
Mode register set/Extended mode register set [MRS/EMRS]
The DDR SDRAM has the two mode registers, the mode register and the extended mode register, to defines how it
works. The both mode registers are set through the address pins (the A0 to the A12, BA0 to BA1) in the mode
register set cycle. For details, refer to "Mode register and extended mode register set".
CKE Truth Table
CKE
Current state Command n – 1 n /CS /RAS /CAS /WE Address Notes
Idle Auto-refresh command (REF) H H L L L H × 2
Idle Self-refresh entry (SELF) H L L L L H × 1, 2
Idle Power down entry (PDEN) H L L H H H ×
H L H × × × ×
Self refresh Self refresh exit (SELFX) L H L H H H ×
L H H × × × ×
Power down Power down exit (PDEX) L H L H H H ×
L H H × × × ×
Remark: H: VIH. L: VIL. ×: VIH or VIL.
Notes: 1. All the banks must be in IDLE before executing this command.
2. The CKE level must be kept for 1 CK cycle at least.
Data Sheet E0384E30 (Ver. 3.0)
14
EDD5104ADTA, EDD5108ADTA, EDD5116ADTA
Function Truth Table
The following tables show the operations that are performed when each command is issued in each state of the
DDR SDRAM.
Current state /CS /RAS /CAS /WE Address Command Operation Next state
1
Precharging*
L H H H × NOP NOP ldle
L H H L × BST ILLEGAL*
L H L H BA, CA, A10 READ/READA ILLEGAL*11 —
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL*11 —
L L H H BA, RA ACT ILLEGAL*11 —
L L H L BA, A10 PRE, PALL NOP ldle
L L L × × ILLEGAL —
2
Idle*
H × × × × DESL NOP ldle
L H H H × NOP NOP ldle
L H H L × BST ILLEGAL*
L H L H BA, CA, A10 READ/READA ILLEGAL*11 —
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL*11 —
L L H H BA, RA ACT Activating Active
L L H L BA, A10 PRE, PALL NOP ldle
L L L H × REF, SELF
L L L L MODE MRS Mode register set*12 ldle
Refresh
(auto-refresh)*
L H H H × NOP NOP ldle
L H H L × BST ILLEGAL —
L H L × × ILLEGAL —
L L × × × ILLEGAL —
Activating*
L H H H × NOP NOP Active
L H H L × BST ILLEGAL*
L H L H BA, CA, A10 READ/READA ILLEGAL*11 —
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL*11 —
L L H H BA, RA ACT ILLEGAL*11 —
L L H L BA, A10 PRE, PALL ILLEGAL*11 —
L L L × × ILLEGAL —
Active*
L H H H × NOP NOP Active
L H H L × BST ILLEGAL Active
L H L H BA, CA, A10 READ/READA Starting read operation Read/READA
L H L L BA, CA, A10 WRIT/WRITA Starting write operation
L L H H BA, RA ACT ILLEGAL*11 —
L L H L BA, A10 PRE, PALL Pre-charge Idle
L L L × × ILLEGAL —
H × × × × DESL NOP ldle
11
—
11
—
Refresh/
Self refresh*
H × × × × DESL NOP ldle
3
4
H × × × × DESL NOP Active
5
H × × × × DESL NOP Active
12
11
—
ldle/
Self refresh
Write
recovering/
precharging
Data Sheet E0384E30 (Ver. 3.0)
15
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