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1GB Registered DDR2 SDRAM DIMM

EBE10RD4AEFA (128M words × 72 bits, 1 Rank)

DATA SHEET

Description

The EBE10RD4AEFA is a 128M words × 72 bits, 1
rank DDR2 SDRAM Module, mounting 18 pieces of
DDR2 SDRAM sealed in FBGA (µBGA
Read and write operations are performed at the cross
points of the CK and the /CK. This high-speed data
transfer is realized by the 4bits prefetch-pipelined
architecture. Data strobe (DQS and /DQS) both for
read and write are available for high spe ed and rel iable
data bus design. By setting extended mode register,
the on-chip Delay Locked Loop (DLL) can be set
enable or disable. This module prov ides high density
mounting without utilizing surface mount technology.
Decoupling capacitors are mounted beside each FBGA
(µBGA) on the module board.

Note: Do not push the components or drop the

modules in order to avoid mechanical defects,
which may result in electrical defects.



) package.

Features

• 240-pin socket type dual in line memory module
(DIMM)

 PCB height: 30.0mm
 Lead pitch: 1.0mm
 Lead-free

• Power supply: VDD, VDDQ = 1.8V ± 0.1V

• Data rate: 533Mbps/400Mbps (max.)

• SSTL_18 compatible I/O

• Double-data-rate architecture: two data transfers per

clock cycle

• Bi-directional, data strobe (DQS and /DQS) is
transmitted /received with data, to be used in
capturing data at the receiver

• DQS is edge aligned with data for READs; center
aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge; data
referenced to both edges of DQS

• Four internal banks for concurrent operation
(components)

• Burst length: 4, 8

• /CAS latency (CL): 3, 4, 5

• Auto precharge option for each burst access

• Auto refresh and self refresh modes

• Average refresh period

 7.8µs at 0°C ≤ TC ≤ +85°C
 3.9µs at +85°C < TC ≤ +95°C

• Posted CAS by programmable additive latency for

better command and data bus efficiency

• Off-Chip-Driver Impedance Adjustment and On-Die­Termination for better signal quality

• /DQS can be disabled for single-ended Data Strobe
operation

• 1 piece of PLL clock driver, 2 pieces of register driver
and 1 piece of serial EEPROM (2k bits EEPROM) for
Presence Detect (PD)

Document No. E0644E30 (Ver. 3.0)
Date Published April 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com

Elpida Memory, Inc. 2005

EBE10RD4AEFA

Ordering Information

Component

Part number
EBE10RD4AEFA-5C-E 533 DDR2-533 (4-4-4) EDE5104AESK-5C-E

EBE10RD4AEFA-4A-E 400 DDR2-400 (3-3-3)

Data rate
Mbps (max.)

JEDEC speed bin*
(CL-tRCD-tRP)

Note: 1. Module /CAS latency = component CL + 1

Pin Configurations

Front side

1 pin

121 pin 184 pin 185 pin 240 pin

Back side

Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name
1 VREF 61 A4 121 VSS 181 VDD
2 VSS 62 VDD 122 DQ4 182 A3
3 DQ0 63 A2 123 DQ5 183 A1
4 DQ1 64 VDD 124 VSS 184 VDD
5 VSS 65 VSS 125 DQS9 185 CK0
6 /DQS0 66 VSS 126 /DQS9 186 /CK0
7 DQS0 67 VDD 127 VSS 187 VDD
8 VSS 68 NC 128 DQ6 188 A0
9 DQ2 69 VDD 129 DQ7 189 VDD
10 DQ3 70 A10 130 VSS 190 BA1
11 VSS 71 BA0 131 DQ12 191 VDD
12 DQ8 72 VDD 132 DQ13 192 /RAS
13 DQ9 73 /WE 133 VSS 193 /CS0
14 VSS 74 /CAS 134 DQS10 194 VDD
15 /DQS1 75 VDD 135 /DQS10 195 ODT0
16 DQS1 76 NC 136 VSS 196 A13
17 VSS 77 NC 137 NC 197 VDD
18 /RESET 78 VDD 138 NC 198 VSS
19 NC 79 VSS 139 VSS 199 DQ36
20 VSS 80 DQ32 140 DQ14 200 DQ37
21 DQ10 81 DQ33 141 DQ15 201 VSS
22 DQ11 82 VSS 142 VSS 202 DQS13
23 VSS 83 /DQS4 143 DQ20 203 /DQS13
24 DQ16 84 DQS4 144 DQ21 204 VSS
25 DQ17 85 VSS 145 VSS 205 DQ38
26 VSS 86 DQ34 146 DQS11 206 DQ39
27 /DQS2 87 DQ35 147 /DQS11 207 VSS
28 DQS2 88 VSS 148 VSS 208 DQ44

1

Package
240-pin DIMM

(lead-free)

64 pin65 pin 120 pin

Contact
pad

Gold

Mounted devices

EDE5104AESK-5C-E
EDE5104AESK-4A-E

Data Sheet E0644E30 (Ver. 3.0)

2

EBE10RD4AEFA

Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name
29 VSS 89 DQ40 149 DQ22 209 DQ45
30 DQ18 90 DQ41 150 DQ23 210 VSS
31 DQ19 91 VSS 151 VSS 211 DQS14
32 VSS 92 /DQS5 152 DQ28 212 /DQS14
33 DQ24 93 DQS5 153 DQ29 213 VSS
34 DQ25 94 VSS 154 VSS 214 DQ46
35 VSS 95 DQ42 155 DQS12 215 DQ47
36 /DQS3 96 DQ43 156 /DQS12 216 VSS
37 DQS3 97 VSS 157 VSS 217 DQ52
38 VSS 98 DQ48 158 DQ30 218 DQ53
39 DQ26 99 DQ49 159 DQ31 219 VSS
40 DQ27 100 VSS 160 VSS 220 NC
41 VSS 101 SA2 161 CB4 221 NC
42 CB0 102 NC 162 CB5 222 VSS
43 CB1 103 VSS 163 VSS 223 DQS15
44 VSS 104 /DQS6 164 DQS17 224 /DQS15
45 /DQS8 105 DQS6 165 /DQS17 225 VSS
46 DQS8 106 VSS 166 VSS 226 DQ54
47 VSS 107 DQ50 167 CB6 227 DQ55
48 CB2 108 DQ51 168 CB7 228 VSS
49 CB3 109 VSS 169 VSS 229 DQ60
50 VSS 110 DQ56 170 VDD 230 DQ61
51 VDD 111 DQ57 171 NC 231 VSS
52 CKE0 112 VSS 172 VDD 232 DQS16
53 VDD 113 /DQS7 173 NC 233 /DQS16
54 NC 114 DQS7 174 NC 234 VSS
55 NC 115 VSS 175 VDD 235 DQ62
56 VDD 116 DQ58 176 A12 236 DQ63
57 A11 117 DQ59 177 A9 237 VSS
58 A7 118 VSS 178 VDD 238 VDDSPD
59 VDD 119 SDA 179 A8 239 SA0
60 A5 120 SCL 180 A6 240 SA1

Data Sheet E0644E30 (Ver. 3.0)

3

EBE10RD4AEFA

Pin Description

Pin name Function

Address input

A0 to A13

A10 (AP) Auto precharge
BA0, BA1 Bank select address
DQ0 to DQ63 Data input/output
CB0 to CB7 Check bit (Data input/output)
/RAS Row address strobe command
/CAS Column address strobe command
/WE Write enable
/CS0 Chip select
CKE0 Clock enable
CK0 Clock input
/CK0 Differential clock input
DQS0 to DQS17, /DQS0 to /DQS17 Input and output data strobe
SCL Clock input for serial PD
SDA Data input/output for serial PD
SA0 to SA2 Serial address input
VDD Power for internal circuit
VDDSPD Power for serial EEPROM
VREF Input reference voltage
VSS Ground
ODT0 ODT control
/RESET Reset pin (forces register and PLL inputs low) *1
NC No connection

Note: 1. Reset pin is connected to both OE of PLL and reset to reg ister.

Row address A0 to A13
Column address A0 to A9, A11

Data Sheet E0644E30 (Ver. 3.0)

4

EBE10RD4AEFA

Serial PD Matrix*

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
0

1
2 Memory type 0 0 0 0 1 0 0 0 08H DDR2 SDRAM

3 Number of row address 0 0 0 0 1 1 1 0 0EH 14
4 Number of column address 0 0 0 0 1 0 1 1 0BH 11
5 Number of DIMM ranks 0 1 1 0 0 0 0 0 60H 1
6 Module data width 0 1 0 0 1 0 0 0 48H 72
7 Module data width continuation 0 0 0 0 0 0 0 0 00H 0
8 Voltage interface level of this assembly 0 0 0 0 0 1 0 1 05H SSTL 1.8V

9

-4A 0 1 0 1 0 0 0 0 50H 5.0ns*1
10

-4A 0 1 1 0 0 0 0 0 60H 0.6ns*1
11 DIMM configuration type 0 0 0 0 0 0 1 0 02H ECC
12 Refresh rate/type 1 0 0 0 0 0 1 0 82H 7.8µs
13 Primary SDRAM width 0 0 0 0 0 1 0 0 04H × 4
14 Error checking SDRAM width 0 0 0 0 0 1 0 0 04H × 4
15 Reserved 0 0 0 0 0 0 0 0 00H 0

16

17

18
19 Reserved 0 0 0 0 0 0 0 0 00H 0

20 DIMM type information 0 0 0 0 0 0 0 1 01H Registered
21 SDRAM module attributes 0 0 0 0 0 0 0 0 00H Normal
22 SDRAM device attributes: General 0 0 0 0 0 0 0 1 01H Weak Driver

23

-4A 0 1 0 1 0 0 0 0 50H 5.0ns*1

24

-4A 0 1 1 0 0 0 0 0 60H 0.6ns*1
25

26

Number of bytes utilized by module
manufacturer

Total number of bytes in serial PD
device

DDR SDRAM cycle time, CL = 5

-5C

SDRAM access from clock (tAC)

-5C

SDRAM device attributes:
Burst length supported

SDRAM device attributes: Number of
banks on SDRAM device

SDRAM device attributes:
/CAS latency

Minimum clock cycle time at CL = 4

-5C

Maximum data access time (tAC) from
clock at CL = 4

-5C

Minimum clock cycle time at CL = 3

-5C, -4A
Maximum data access time (tAC) from

clock at CL = 3

-5C, -4A

1

1 0 0 0 0 0 0 0 80H 128 bytes

0 0 0 0 1 0 0 0 08H 256 bytes

0 0 1 1 1 1 0 1 3DH 3.75ns*1

0 1 0 1 0 0 0 0 50H 0.5ns*

0 0 0 0 1 1 0 0 0CH 4,8

0 0 0 0 0 1 0 0 04H 4

0 0 1 1 1 0 0 0 38H 3, 4, 5

0 0 1 1 1 1 0 1 3DH 3.75ns*1

0 1 0 1 0 0 0 0 50H 0.5ns*1

0 1 0 1 0 0 0 0 50H 5.0ns*

0 1 1 0 0 0 0 0 60H 0.6ns*1

1

1

Data Sheet E0644E30 (Ver. 3.0)

5

EBE10RD4AEFA

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
27

28

29

30

-4A 0 0 1 0 1 0 0 0 28H 40ns
31 Module rank density 0 0 0 0 0 0 0 1 01H 1GB

32

-4A 0 0 1 1 0 1 0 1 35H 0.35ns*1

33

-4A 0 1 0 0 1 0 0 0 48H 0.48ns*1

34

-4A 0 0 0 1 0 1 0 1 15H 0.15ns*1
35

-4A 0 0 1 0 1 0 0 0 28H 0.28ns*1
36 Write recovery time (tWR) 0 0 1 1 1 1 0 0 3CH 15ns*1

37

-4A 0 0 1 0 1 0 0 0 28H 10ns*1
38
39 Memory analysis probe characteristics 0 0 0 0 0 0 0 0 00H TBD

40 Extension of Byte 41 and 42 0 0 0 0 0 0 0 0 00H Undefined
41

-4A 0 0 1 1 0 1 1 1 37H 55ns*1
42
43 SDRAM tCK cycle max. (tCK max.) 1 0 0 0 0 0 0 0 80H 8ns*1
44

-4A 0 0 1 0 0 0 1 1 23H 0.35ns*1
45

-4A 0 0 1 0 1 1 0 1 2DH 0.45ns*1
46 PLL relock time 0 0 0 0 1 1 1 1 0FH 15µs
47 to 61 0 0 0 0 0 0 0 0 00H

Minimum row precharge time (tRP)

-5C, -4A
Minimum row active to row active delay

(tRRD)
Minimum /RAS to /CAS delay (tRCD)

-5C, -4A
Minimum active to precharge time

(tRAS)

-5C

Address and command setup time
before clock (tIS)

-5C

Address and command hold time after
clock (tIH)

-5C

Data input setup time before clock
(tDS)

-5C

Data input hold time after clock (tDH)

-5C

Internal write to read command delay
(tWTR)

-5C

Internal read to precharge command
delay (tRTP)

Active command period (tRC)

-5C

Auto refresh to active/
Auto refresh command cycle (tRFC)

Dout to DQS skew

-5C

Data hold skew (tQHS)

-5C

0 0 1 1 1 1 0 0 3CH 15ns

0 0 0 1 1 1 1 0 1EH 7.5ns

0 0 1 1 1 1 0 0 3CH 15ns

0 0 1 0 1 1 0 1 2DH 45ns

0 0 1 0 0 1 0 1 25H 0.25ns*1

0 0 1 1 1 0 0 0 38H 0.38ns*

1

0 0 0 1 0 0 0 0 10H 0.10ns*1

0 0 1 0 0 0 1 1 23H 0.23ns*1

0 0 0 1 1 1 1 0 1EH 7.5ns*1

0 0 0 1 1 1 1 0 1EH 7.5ns*

1

0 0 1 1 1 1 0 0 3CH 60ns*1

0 1 1 0 1 0 0 1 69H 105ns*

1

0 0 0 1 1 1 1 0 1EH 0.30ns*1

0 0 1 0 1 0 0 0 28H 0.40ns*1

Data Sheet E0644E30 (Ver. 3.0)

6

EBE10RD4AEFA

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
62 SPD Revision 0 0 0 1 0 0 0 0 10H Rev. 1.0

63

-4A 1 1 0 0 0 1 1 0 C6H
64 to 65 Manufacturer’s JEDEC ID code 0 1 1 1 1 1 1 1 7FH
66 Manufacturer’s JEDEC ID code 1 1 1 1 1 1 1 0 FEH Elpida Memory

67 to 71 Manufacturer’s JEDEC ID code 0 0 0 0 0 0 0 0 00H
72 Manufacturing location × × × × × × × × ××
73 Module part number 0 1 0 0 0 1 0 1 45H E

74 Module part number 0 1 0 0 0 0 1 0 42H B
75 Module part number 0 1 0 0 0 1 0 1 45H E
76 Module part number 0 0 1 1 0 0 0 1 31H 1
77 Module part number 0 0 1 1 0 0 0 0 30H 0
78 Module part number 0 1 0 1 0 0 1 0 52H R
79 Module part number 0 1 0 0 0 1 0 0 44H D
80 Module part number 0 0 1 1 0 1 0 0 34H 4
81 Module part number 0 1 0 0 0 0 0 1 41H A
82 Module part number 0 1 0 0 0 1 0 1 45H E
83 Module part number 0 1 0 0 0 1 1 0 46H F
84 Module part number 0 1 0 0 0 0 0 1 41H A
85 Module part number 0 0 1 0 1 1 0 1 2DH —

86

-4A 0 0 1 1 0 1 0 0 34H 4
87

-5C 0 1 0 0 0 0 1 1 43H C
88 Module part number 0 0 1 0 1 1 0 1 2DH —
89 Module part number 0 1 0 0 0 1 0 1 45H E
90 Module part number 0 0 1 0 0 0 0 0 20H (Space)
91 Revision code 0 0 1 1 0 0 0 0 30H Initial
92 Revision code 0 0 1 0 0 0 0 0 20H (Space)

93 Manufacturing date × × × × × × × × ××

94 Manufacturing date × × × × × × × × ××
95 to 98 Module serial number

99 to 127 Manufacture specific data

Checksum for bytes 0 to 62

-5C

Module part number

-5C

Module part number

-4A

Note: 1. These specifications are defined based on component specification, not module.

0 1 0 0 1 1 0 0 4CH

Continuation
code

(ASCII-8bit
code)

0 0 1 1 0 1 0 1 35H 5

0 1 0 0 0 0 0 1 41H A

Year code
(BCD)

Week code
(BCD)

Data Sheet E0644E30 (Ver. 3.0)

7