Datasheet EBD52UC8AKFA-5 Datasheet (ELPIDA)

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512MB Unbuffered DDR SDRAM DIMM

PRELIMINARY DATA SHEET

EBD52UC8AKFA -5

(64M words ×××× 64 bits, 2 Ranks)

Description

The EBD52UC8AKFA is 64M words × 64 bits, 2 ranks

Double Data Rate (DDR) SDRAM unbuffered module, mounting 16 pieces of 256M bits DDR SDRAM sealed in TSOP package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each TSOP on the module board.

Features

• 184-pin socket type dual in line memory module

(DIMM)

 PCB height: 31.75mm  Lead pitch: 1.27mm

• 2.5V power supply

• Data rate: 400Mbps (max.)

• 2.5 V (SSTL_2 compatible) I/O

• Double Data Rate architecture; two data transfers per

clock cycle

• Bi-directional, data strobe (DQS) is transmitted

/received with data, to be used in capturing data at the receiver

• Data inputs and outputs are synchronized with DQS

• 4 internal banks for concurrent operation

(Component)

• DQS is edge aligned with data for READs; center

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge; data

referenced to both edges of DQS

• Data mask (DM) for write data

• Auto precharge option for each burst access

• Programmable burst length: 2, 4, 8

• Programmable /CAS latency (CL): 3

• Programmable output driver strength: normal/weak

• Refresh cycles: (8192 refresh cycles /64ms)  7.8µs maximum average periodic refresh interval

• 2 variations of refresh  Auto refresh  Self refresh

Document No. E0355E30 (Ver. 3.0) Date Published June 2003 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2003

EBD52UC8AKFA-5

Ordering Information

Part number

EBD52UC8AKFA-5B EBD52UC8AKFA-5C

Pin Configurations

Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name

1 VREF 47 NC 93 VSS 139 VSS

2 DQ0 48 A0 94 DQ4 140 NC

3 VSS 49 NC 95 DQ5 141 A10

4 DQ1 50 VSS 96 VDD 142 NC

5 DQS0 51 NC 97 DM0/DQS9 143 VDD

6 DQ2 52 BA1 98 DQ6 144 NC

7 VDD 53 DQ32 99 DQ7 145 VSS

8 DQ3 54 VDD 100 VSS 146 DQ36

9 NC 55 DQ33 101 NC 147 DQ37

10 NC 56 DQS4 102 NC 148 VDD

11 VSS 57 DQ34 103 NC 149 DM4/DQS13

12 DQ8 58 VSS 104 VDD 150 DQ38

13 DQ9 59 BA0 105 DQ12 151 DQ39

14 DQS1 60 DQ35 106 DQ13 152 VSS

15 VDD 61 DQ40 107 DM1/DQS10 153 DQ44

16 CK1 62 VDD 108 VDD 154 /RAS

17 /CK1 63 /WE 109 DQ14 155 DQ45

18 VSS 64 DQ41 110 DQ15 156 VDD

19 DQ10 65 /CAS 111 CKE1 157 /CS0

20 DQ11 66 VSS 112 VDD 158 /CS1

21 CKE0 67 DQS5 113 NC 159 DM5/DQS14

22 VDD 68 DQ42 114 DQ20 160 VSS

23 DQ16 69 DQ43 115 A12 161 DQ46

24 DQ17 70 VDD 116 VSS 162 DQ47

25 DQS2 71 NC 117 DQ21 163 NC

26 VSS 72 DQ48 118 A11 164 VDD

27 A9 73 DQ49 119 DM2/DQS11 165 DQ52

28 DQ18 74 VSS 120 VDD 166 DQ53

29 A7 75 /CK2 121 DQ22 167 NC

Data rate Mbps (max.)

400

Component JEDEC speed bin (CL-tRCD-tRP)

DDR400B (3-3-3) DDR400C (3-4-4)

Front side

1 pin

93 pin 144 pin 145 pin184 pin

Back side

Package

184-pin DIMM Gold

52 pin53 pin 92 pin

Contact pad Mounted devices

EDD2508AKTA-5B EDD2508AKTA-5B, -5C

Preliminary Data Sheet E0355E30 (Ver. 3.0)

EBD52UC8AKFA-5

Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name

30 VDD 76 CK2 122 A8 168 VDD

31 DQ19 77 VDD 123 DQ23 169 DM6/DQS15

32 A5 78 DQS6 124 VSS 170 DQ54

33 DQ24 79 DQ50 125 A6 171 DQ55

34 VSS 80 DQ51 126 DQ28 172 VDD

35 DQ25 81 VSS 127 DQ29 173 NC

36 DQS3 82 VDDID 128 VDD 174 DQ60

37 A4 83 DQ56 129 DM3/DQS12 175 DQ61

38 VDD 84 DQ57 130 A3 176 VSS

39 DQ26 85 VDD 131 DQ30 177 DM7/DQS16

40 DQ27 86 DQS7 132 VSS 178 DQ62

41 A2 87 DQ58 133 DQ31 179 DQ63

42 VSS 88 DQ59 134 NC 180 VDD

43 A1 89 VSS 135 NC 181 SA0

44 NC 90 NC 136 VDD 182 SA1

45 NC 91 SDA 137 CK0 183 SA2

46 VDD 92 SCL 138 /CK0 184 VDDSPD

Preliminary Data Sheet E0355E30 (Ver. 3.0)

EBD52UC8AKFA-5

Pin Description

Pin name Function

Address input

A0 to A12

BA0, BA1 Bank select address

DQ0 to DQ63 Data input/output

/RAS Row address strobe command

/CAS Column address strobe command

/WE Write enable

/CS0, /CS1 Chip select

CKE0, CKE1 Clock enable

CK0 to CK2 Clock input

/CK0 to /CK2 Differential clock input

DQS0 to DQS7 Input and output data strobe

DM0 to DM7/DQS9 to DQS16 Input mask

SCL Clock input for serial PD

SDA Data input/output for serial PD

SA0 to SA2 Serial address input

VDD Power for internal circuit

VDDSPD Power for serial EEPROM

VREF Input reference voltage

VSS Ground

VDDID VDD identification flag

NC No connection

Row address A0 to A12 Column address A0 to A9

Preliminary Data Sheet E0355E30 (Ver. 3.0)

EBD52UC8AKFA-5

Serial PD Matrix

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

2 Memory type 0 0 0 0 0 1 1 1 07H DDR SDRAM

3 Number of row address 0 0 0 0 1 1 0 1 0DH 13

4 Number of column address 0 0 0 0 1 0 1 0 0AH 10

5 Number of DIMM ranks 0 0 0 0 0 0 1 0 02H 2

6 Module data width 0 1 0 0 0 0 0 0 40H 64

7 Module data width continuation 0 0 0 0 0 0 0 0 00H 0

8 Voltage interface level of this assembly 0 0 0 0 0 1 0 0 04H SSTL2

9 DDR SDRAM cycle time, CL = 3 0 1 0 1 0 0 0 0 50H 5.0ns*1

10 SDRAM access from clock (tAC) 0 1 1 1 0 0 0 0 70H 0.7ns*1

11 DIMM configuration type 0 0 0 0 0 0 0 0 00H None.

12 Refresh rate/type 1 0 0 0 0 0 1 0 82H 7.8µs 13 Primary SDRAM width 0 0 0 0 1 0 0 0 08H × 8

14 Error checking SDRAM width 0 0 0 0 0 0 0 0 00H None.

21 SDRAM module attributes 0 0 1 0 0 0 0 0 20H

22 SDRAM device attributes: General 1 1 0 0 0 0 0 0 C0H VDD ± 0.2V

23 Minimum clock cycle time at CL = 2.5 0 1 1 0 0 0 0 0 60H 6.0ns*1

25 Minimum clock cycle time at CL = 2 0 1 1 1 0 1 0 1 75H 0.75ns*1

-5C 0 1 0 0 1 0 0 0 48H 18ns

31 Module rank density 0 1 0 0 0 0 0 0 40H 256M bytes

Number of bytes utilized by module manufacturer

Total number of bytes in serial PD device

SDRAM device attributes: Minimum clock delay back-to-back column access

SDRAM device attributes: Burst length supported

SDRAM device attributes: Number of banks on SDRAM device

SDRAM device attributes: /CAS latency

SDRAM device attributes: /CS latency

SDRAM device attributes: /WE latency

Maximum data access time (tAC) from clock at CL = 2.5

Maximum data access time (tAC) from clock at CL = 2

Minimum row precharge time (tRP)

-5B

Minimum row active to row active delay (tRRD)

Minimum /RAS to /CAS delay (tRCD)

-5B

Minimum active to precharge time (tRAS)

1 0 0 0 0 0 0 0 80H 128 bytes

0 0 0 0 1 0 0 0 08H 256 bytes

0 0 0 0 0 0 0 1 01H 1 CLK

0 0 0 0 1 1 1 0 0EH 2, 4, 8

0 0 0 0 0 1 0 0 04H 4

0 0 0 1 1 1 0 0 1CH 2, 2.5, 3

0 0 0 0 0 0 0 1 01H 0

0 0 0 0 0 0 1 0 02H 1

Differential Clock

0 1 1 1 0 0 0 0 70H 0.7ns*1

0 1 1 1 0 1 0 1 75H 0.75ns*1

0 0 1 1 1 1 0 0 3CH 15ns

0 0 1 0 1 0 0 0 28H 10ns

0 0 1 1 1 1 0 0 3CH 15ns

0 0 1 0 1 0 0 0 28H 40ns

Preliminary Data Sheet E0355E30 (Ver. 3.0)

EBD52UC8AKFA-5

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

35 Data input hold time after clock (tDH) 0 1 0 0 0 0 0 0 40H 0.4ns*1

36 to 40 Superset information 0 0 0 0 0 0 0 0 00H Future use

-5C 0 0 1 1 1 1 0 0 3CH 60ns*1

43 SDRAM tCK cycle max. (tCK max.) 0 0 1 0 0 0 0 0 20H 8ns*1

44 Dout to DQS skew 0 0 1 0 1 0 0 0 28H 0.4ns*1

45 Data hold skew (tQHS) 0 1 0 1 0 0 0 0 50H 0.5ns*1

46 to 61 Superset information 0 0 0 0 0 0 0 0 00H Future use

62 SPD Revision 0 0 0 0 0 0 0 0 00H

-5C 0 1 1 1 1 1 0 0 7CH

64 to 65 Manufacturer’s JEDEC ID code 0 1 1 1 1 1 1 1 7FH

66 Manufacturer’s JEDEC ID code 1 1 1 1 1 1 1 0 FEH Elpida Memory

67 to 71 Manufacturer’s JEDEC ID code 0 0 0 0 0 0 0 0 00H

72 Manufacturing location × × × × × × × × ××

73 Module part number 0 1 0 0 0 1 0 1 45H E

74 Module part number 0 1 0 0 0 0 1 0 42H B

75 Module part number 0 1 0 0 0 1 0 0 44H D

76 Module part number 0 0 1 1 0 1 0 1 35H 5

77 Module part number 0 0 1 1 0 0 1 0 32H 2

78 Module part number 0 1 0 1 0 1 0 1 55H U

79 Module part number 0 1 0 0 0 0 1 1 43H C

80 Module part number 0 0 1 1 1 0 0 0 38H 8

81 Module part number 0 1 0 0 0 0 0 1 41H A

82 Module part number 0 1 0 0 1 0 1 1 4BH K

83 Module part number 0 1 0 0 0 1 1 0 46H F

84 Module part number 0 1 0 0 0 0 0 1 41H A

85 Module part number 0 0 1 0 1 1 0 1 2DH —

86 Module part number 0 0 1 1 0 1 0 1 35H 5

-5C 0 1 0 0 0 0 1 1 43H C

88 to 90 Module part number 0 0 1 0 0 0 0 0 20H (Space)

91 Revision code 0 0 1 1 0 0 0 0 30H Initial

92 Revision code 0 0 1 0 0 0 0 0 20H (Space)

Address and command setup time before clock (tIS)

Address and command hold time after clock (tIH)

Data input setup time before clock (tDS)

Active command period (tRC)

-5B

Auto refresh to active/ Auto refresh command cycle (tRFC)

Checksum for bytes 0 to 62

-5B

Module part number

-5B

0 1 1 0 0 0 0 0 60H 0.6ns

0 1 1 0 0 0 0 0 60H 0.6ns*1

0 1 0 0 0 0 0 0 40H 0.4ns*1

0 0 1 1 0 1 1 1 37H 55ns*1

0 1 0 0 0 1 1 0 46H 70ns*1

0 1 0 1 1 1 1 1 5FH

0 1 0 0 0 0 1 0 42H B

Continuation code

(ASCII-8bit code)

Preliminary Data Sheet E0355E30 (Ver. 3.0)

EBD52UC8AKFA-5

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 93 Manufacturing date × × × × × × × × ××

94 Manufacturing date × × × × × × × × ××

95 to 98 Module serial number

99 to 127 Manufacture specific data

Note: 1.These specifications are defined based on component specification, not module.

Year code (HEX)

Week code (HEX)

Preliminary Data Sheet E0355E30 (Ver. 3.0)

Block Diagram

EBD52UC8AKFA-5

/CS0

DQS0

DQ0 to DQ7

DQS1

DQ8 to DQ15

DQS2

DQ16 to DQ23

DQS3

DQ24 to DQ31

DQS4

DQ32 to DQ39

DQS5

DQ40 to DQ47

DQS6

DQ48 to DQ55

DQS7

DQ56 to DQ63

* U1 to U8, U10 to U17: 256M bits DDR SDRAM

U20: 2k bits EEPROM RS: 22Ω

VDD

VREF

VSS

VDDID

open

Clock wiring Clock input CK0, /CK0 CK1, /CK1 CK2, /CK2 Note: Wire per Clock loading table/Wiring diagrams.

DDR SDRAMS 4DRAM loads 6DRAM loads 6DRAM loads

/CS

DQS DM

DQS DM/CS

U11

DQS DM/CS

U13

DQS DM/CS

U14

DQS DM/CS

U16

DQS DM/CS

U1 to U8, U10 to U17 U1 to U8, U10 to U17 U1 to U8, U10 to U17

/CS1

DQS DM/CS

U10

DQS DM/CS

U12

DQS DM/CS

U15

DQS DM/CS

U17

A0 to A12

BA0, BA1

SCL

/RAS /CAS

/WE

CKE0 CKE1

3.3Ω

Serial PD

SCL

DM0/DQS9

DM1/DQS10

DM2/DQS11

DM3/DQS12

DM4/DQS13

DM5/DQS14

DM6/DQS15

DM7/DQS16

A0 to A12 (U1 to U8, U10 to U17) BA0, BA1 (U1 to U8, U10 to U17)

/RAS (U1 to U8, U10 to U17) /CAS (U1 to U8, U10 to U17)

/WE (U1 to U8, U10 to U17)

CKE (U1 to U8, U10 to U17) CKE (U1 to U8, U10 to U17)

SDA

U20

A1 A2

Notes:

1. The SDA pull-up resistor is required due to the open-drain/open-collector output.

2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state.

SA0 SA1 SA2

SDA

Preliminary Data Sheet E0355E30 (Ver. 3.0)

Logical Clock Net Structure

EBD52UC8AKFA-5

6DRAM loads

CLK

DIMM connector

/CLK

4DRAM loads

DIMM connector

R = 120Ω

DRAM1

DRAM2 DRAM3

DRAM4 DRAM5

DRAM6

DRAM1

DRAM2 Capacitance

Capacitance DRAM5

DRAM6

5DRAM loads

DIMM connector

3DRAM loads

DIMM connector

R = 120Ω

DRAM1

DRAM2 DRAM3

Capacitance DRAM5

DRAM6

DRAM1

Capacitance DRAM3

Capacitance DRAM5

Capacitance

2DRAM loads

DIMM connector

R = 120Ω

DRAM1

Capacitance Capacitance

Capacitance DRAM5

Capacitance

1DRAM loads

DIMM connector

R = 120Ω

Capacitance

Capacitance DRAM3

Capacitance

Preliminary Data Sheet E0355E30 (Ver. 3.0)

EBD52UC8AKFA-5

Electrical Specifications

• All voltages are referenced to VSS (GND).

Absolute Maximum Ratings

Parameter Symbol Value Unit Note

Voltage on any pin relative to VSS VT –0.5 to +3.6 V

Supply voltage relative to VSS VDD –0.5 to +3.6 V

Short circuit output current IOS 50 mA

Power dissipation PD 16 W

Operating ambient temperature TA 0 to +70 °C 1

Storage temperature Tstg –55 to +125 °C

Notes: 1. DDR SDRAM component specification.

Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.

DC Operating Conditions (TA = 0 to +70°C) (DDR SDRAM Component Specification)

Parameter Symbol Min Typ Max Unit Notes

Supply voltage VDD,VDDQ 2.5 2.6 2.7 V 1

VSS 0 0 0 V

Input reference voltage VREF 0.49 × VDDQ 0.50 × VDDQ 0.51 × VDDQ V

Termination voltage VTT VREF – 0.04 VREF VREF + 0.04 V

Input high voltage VIH (DC) VREF + 0.15 — VDDQ + 0.3 V 2

Input low voltage VIL (DC) –0.3 — VREF – 0.15 V 3

Input voltage level, CK and /CK inputs

Input differential cross point voltage, CK and /CK inputs

Input differential voltage, CK and /CK inputs

Notes. 1. VDDQ must be lower than or equal to VDD.

2. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns.

3. VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns.

4. VIN (DC) specifies the allowable DC execution of each differential input.

5. VID (DC) specifies the input differential voltage required for switching.

6. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V if measurement.

VIN (DC) –0.3 — VDDQ + 0.3 V 4

VIX (DC) 0.5 × VDDQ − 0.2V 0.5 × VDDQ 0.5 × VDDQ + 0.2V V

VID (DC) 0.36 — VDDQ + 0.6 V 5, 6

Preliminary Data Sheet E0355E30 (Ver. 3.0)

EBD52UC8AKFA-5

DC Characteristics 1 (TA = 0 to +70°C, VDD = 2.6V ± 0.1V, VSS = 0V)

Parameter Symbol Grade max. Unit Test condition Notes

Operating current (ACTV-PRE) IDD0

Operating current (ACTV-READ-PRE)

Idle power down standby current IDD2P 48 mA CKE ≤ VIL 4

Floating idle Standby current

Quiet idle Standby current

Active power down standby current

Active standby current IDD3N 960 mA

Operating current (Burst read operation)

Operating current (Burst write operation)

Auto refresh current IDD5 2720 mA

Self refresh current IDD6 48 mA

Operating current (4 banks interleaving)

IDD1

IDD2F 480 mA

IDD2Q 400 mA

IDD3P 320 mA CKE ≤ VIL 3

IDD4R 2080 mA

IDD4W 2160 mA

IDD7A 3040 mA BL = 4 5, 6, 7

-5B

-5C

-5B

-5C

Notes. 1. These IDD data are measured under condition that DQ pins are not connected.

2. One bank operation.

3. One bank active.

4. All banks idle.

5. Command/Address transition once per one cycle.

6. DQ, DM and DQS mask transition twice per one cycle.

7. 4 banks active. Only one bank is running at tRC = tRC (min.)

8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.

9. Command/Address transition once per one every two clock cycles.

10. Command/Address stable at ≥ VIH or ≤ VIL.

1360 1280

1600 1520

CKE ≥ VIH, tRC = tRC (min.)

CKE ≥ VIH, BL = 4, CL = 3, tRC = tRC (min.)

CKE ≥ VIH, /CS ≥ VIH DQ, DQS, DM = VREF

CKE ≥ VIH, /CS ≥ VIH tRAS = tRAS (max.)

CKE ≥ VIH, BL = 2, CL = 3

tRFC = tRFC (min.), Input ≤ VIL or ≥ VIH

Input ≥ VDD – 0.2 V Input ≤ 0.2 V

1, 2, 9

1, 2, 5

4, 5

4, 10

3, 5, 6

1, 2, 5, 6

DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.6V ± 0.1V, VSS = 0V)

Parameter Symbol min. max. Unit Test condition Notes

Input leakage current ILI –32 32 µA VDD ≥ VIN ≥ VSS

Output leakage current ILO –10 10 µA VDD ≥ VOUT ≥ VSS

Output high current IOH –15.2 — mA VOUT = 1.95V 1

Output low current IOL 15.2 — mA VOUT = 0.35V 1

Note: 1. DDR SDRAM component specification.

Preliminary Data Sheet E0355E30 (Ver. 3.0)

EBD52UC8AKFA-5

Pin Capacitance (TA = 25°C, VDD = 2.6V ± 0.1V)

Parameter Symbol Pins max. Unit Notes

Input capacitance CI1

Input capacitance CI2 CK, /CK 60 pF

Data and DQS input/output capacitance

CO DQ, DQS, DM 15 pF

AC Characteristics (TA = 0 to +70°°°°C, VDD, VDDQ = 2.6V ± 0.1V, VSS = 0V) (DDR SDRAM Component Specification)

-5B -5C

Parameter Symbol min. max. min. max. Unit Notes

Clock cycle time tCK 5 8 5 8 ns 10

CK high-level width tCH 0.45 0.55 0.45 0.55 tCK

CK low-level width tCL 0.45 0.55 0.45 0.55 tCK

CK half period tHP

DQ output access time from CK, /CK tAC –0.7 0.7 –0.7 0.7 ns 2, 11

DQS output access time from CK, /CK tDQSCK –0.55 0.55 –0.55 0.55 ns 2, 11

DQS to DQ skew tDQSQ — 0.4 — 0.4 ns 3

DQ/DQS output hold time from DQS tQH tHP – tQHS — tHP – tQHS — ns

Data hold skew factor tQHS — 0.5 — 0.5 ns

Data-out high-impedance time from CK, /CK

Data-out low-impedance time from CK, /CK

Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK

Read postamble tRPST 0.4 0.6 0.4 0.6 tCK

DQ and DM input setup time tDS 0.4 — 0.4 — ns 8

DQ and DM input hold time tDH 0.4 — 0.4 — ns 8

DQ and DM input pulse width tDIPW 1.75 — 1.75 — ns 7

Write preamble setup time tWPRES 0 — 0 — ns

Write preamble tWPRE 0.25 — 0.25 — tCK

Write postamble tWPST 0.4 0.6 0.4 0.6 tCK 9

Write command to first DQS latching transition

DQS falling edge to CK setup time tDSS 0.2 — 0.2 — tCK

DQS falling edge hold time from CK tDSH 0.2 — 0.2 — tCK

DQS input high pulse width tDQSH 0.35 — 0.35 — tCK

DQS input low pulse width tDQSL 0.35 — 0.35 — tCK

Address and control input setup time tIS 0.6 — 0.6 — ns 8

Address and control input hold time tIH 0.6 — 0.6 — ns 8

Address and control input pulse width tIPW 2.2 — 2.2 — ns 7

Mode register set command cycle time tMRD 2 — 2 — tCK

Active to Precharge command period tRAS 40 120000 40 120000 ns

Active to Active/Auto refresh command period

tHZ — 0.7 — 0.7 ns 5, 11

tLZ –0.7 0.7 –0.7 0.7 ns 6, 11

tDQSS 0.72 1.28 0.72 1.28 tCK

tRC 55 — 60 — ns

Address, /RAS, /CAS, /WE, /CS, CKE

min (tCH, tCL)

—

90 pF

min (tCH, tCL)

— tCK

Preliminary Data Sheet E0355E30 (Ver. 3.0)

EBD52UC8AKFA-5

-5B -5C

Parameter Symbol min. max. min. max. Unit Notes

Auto refresh to Active/Auto refresh command period

Active to Read/Write delay tRCD 15 — 18 — ns

Precharge to active command period tRP 15 — 18 — ns

Active to Autoprecharge delay tRAP tRCD min. — tRCD min. — ns

Active to active command period tRRD 10 — 10 — ns

Write recovery time tWR 15 — 15 — ns

Auto precharge write recovery and precharge time

Internal write to Read command delay tWTR 2 — 2 — tCK

Average periodic refresh interval tREF — 7.8 — 7.8 µs

Notes: 1. All the AC parameters listed in this data sheet is component specifications. For AC testing conditions,

refer to the corresponding component data sheet.

2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal transition is defined to occur when the signal level crossing VTT.

3. The timing reference level is VTT.

4. Output valid window is defined to be the period between two successive transition of data out or DQS (read) signals. The signal transition is defined to occur when the signal level crossing VTT.

5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage level, but specify when the device output stops driving.

6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This parameter is not referred to a specific DOUT voltage level, but specify when the device output begins driving.

7. Input valid windows is defined to be the period between two successive transition of data input or DQS (write) signals. The signal transition is defined to occur when the signal level crossing VREF.

8. The timing reference level is VREF.

9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific reference voltage to judge this transition is not given.

10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not assured.

11. tCK = tCK (min) when these parameters are measured. Otherwise, absolute minimum values of these values are 10% of tCK.

12. VDD is assumed to be 2.6V ± 0.1V. VDD power supply variation per cycle expected to be less than

0.4V/400 cycle.

13. tDAL = (tWR/tCK)+(tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer.

Example: For –5C Speed at CL = 3, tCK = 5ns, tWR = 15ns and tRP= 18ns,

tDAL = (15ns/5ns) + (18ns/5ns) = (3) + (4)

tDAL = 7 clocks

tRFC 70 — 70 — ns

tDAL

(tWR/tCK)+ (tRP/tCK)

—

(tWR/tCK)+ (tRP/tCK)

— tCK 13

Preliminary Data Sheet E0355E30 (Ver. 3.0)

Timing Parameter Measured in Clock Cycle for Unbuffered DIMM

EBD52UC8AKFA-5

Number of clock cycle

tCK 5ns

Parameter Symbol min. max. Unit

Write to pre-charge command delay (same bank) tWPD 4 + BL/2 tCK

Read to pre-charge command delay (same bank) tRPD BL/2

Write to read command delay (to input all data) tWRD 2 + BL/2

Burst stop command to write command delay tBSTW 3

Burst stop command to DQ High-Z tBSTZ 3 3

Read command to write command delay (to output all data)

Pre-charge command to High-Z tHZP 3 3

Write command to data in latency tWCD 1 1

Write recovery tWR 3

DM to data in latency tDMD 0 0

Mode register set command cycle time tMRD 2

Self refresh exit to non-read command tSNR 15

Self refresh exit to read command tSRD 200

Power down entry tPDEN 1 1

Power down exit to command input tPDEX 1

tRWD 3 + BL/2

tCK

Preliminary Data Sheet E0355E30 (Ver. 3.0)

EBD52UC8AKFA-5

Pin Functions

CK, /CK (input pin)

The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross point of the CK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS and the VREF level. DQSs for write operation are referred to the cross point of the CK and the /CK.

/CS (input pin)

When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held.

/RAS, /CAS, and /WE (input pins)

These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation".

A0 to A12 (input pins)

Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to AY9) is loaded via the A0 to the A9 at the cross point of the CK rising edge and the VREF level in a read or a write command cycle. This column address becomes the starting address of a burst operation.

A10 (AP) (input pin)

A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = high when read or write command, auto-precharge function is enabled. While A10 = low, auto-precharge function is disabled.

BA0, BA1 (input pin)

BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See Bank Select Signal Table)

[Bank Select Signal Table]

BA0 BA1

Bank 0 L L

Bank 1 H L

Bank 2 L H

Bank 3 H H

Remark: H: VIH. L: VIL.

CKE (input pin)

CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven low and exited when it resumes to high.

The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold time tIH.

DQ (input and output pins)

Data are input to and output from these pins.

DQS (input and output pin)

DQS provide the read data strobes (as output) and the write data strobes (as input).

Preliminary Data Sheet E0355E30 (Ver. 3.0)

EBD52UC8AKFA-5

DM (input pins): DM is the reference signal of the data input mask function. DMs are sampled at the cross point of

DQS and VREF

VDD (power supply pins)

2.5V is applied. (VDD is for the internal circuit.)

VDDSPD (power supply pin)

2.5V is applied (For serial EEPROM).

VSS (power supply pin)

Ground is connected.

Detailed Operation Part and Timing Waveforms

Refer to the EDD2508AKTA-5 datasheet (E0349E).

Preliminary Data Sheet E0355E30 (Ver. 3.0)

Physical Outline

2.30

1 92

2 – φ 2.50 ± 0.10

133.35 ± 0.15

128.95

(64.48)

(DATUM -A-)

Component area

(Front)

64.77 49.53

EBD52UC8AKFA-5

Unit: mm

4.00 max

4.00 min

1.27 ± 0.10

4.00 ± 0.10

Component area

(Back)

R 2.00

Detail A

1.27 typ

2.50 ± 0.20

1.00 ± 0.05

Note: Tolerance on all dimensions ± 0.13 unless otherwise specified.

Detail B

0.20 ± 0.15

3.80

(DATUM -A-)

6.62

2.175 R 0.90

1.80 ± 0.10

6.35

3.00 min

184

10.00

17.80

31.75 ± 0.15

ECA-TS2-0040-01

Preliminary Data Sheet E0355E30 (Ver. 3.0)

EBD52UC8AKFA-5

CAUTION FOR HANDLING MEMORY MODULES

When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects.

When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR MOS DEVICES

Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES

No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V

or GND with a resistor, if it is considered to have a possibility of being an output

pin. The unused pins must be handled in accordance with the related specifications.

MDE0202

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.

CME0107

Preliminary Data Sheet E0355E30 (Ver. 3.0)

EBD52UC8AKFA-5

The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.

No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc.

Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others.

Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information.

[Product applications]

Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury.

[Product usage]

Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product.

[Usage environment]

This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment.

If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations.

If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.

M01E0107

Preliminary Data Sheet E0355E30 (Ver. 3.0)

Datasheet EBD52UC8AKFA-5 Datasheet (ELPIDA)

Specifications and Main Features

Frequently Asked Questions

User Manual