ELPIDA EBD52UC8AKFA-5 DATA SHEET

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512MB Unbuffered DDR SDRAM DIMM

PRELIMINARY DATA SHEET

EBD52UC8AKFA -5

(64M words ×××× 64 bits, 2 Ranks)

Description

The EBD52UC8AKFA is 64M words × 64 bits, 2 ranks

Double Data Rate (DDR) SDRAM unbuffered module,
mounting 16 pieces of 256M bits DDR SDRAM sealed
in TSOP package. Read and write operations are
performed at the cross points of the CK and the /CK.
This high-speed data transfer is realized by the 2 bits
prefetch-pipelined architecture. Data strobe (DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. This module provides high
density mounting without utilizing surface mount
technology. Decoupling capacitors are mounted
beside each TSOP on the module board.

Features

• 184-pin socket type dual in line memory module

(DIMM)

 PCB height: 31.75mm
 Lead pitch: 1.27mm

• 2.5V power supply

• Data rate: 400Mbps (max.)

• 2.5 V (SSTL_2 compatible) I/O

• Double Data Rate architecture; two data transfers per

clock cycle

• Bi-directional, data strobe (DQS) is transmitted

/received with data, to be used in capturing data at
the receiver

• Data inputs and outputs are synchronized with DQS

• 4 internal banks for concurrent operation

(Component)

• DQS is edge aligned with data for READs; center

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge; data

referenced to both edges of DQS

• Data mask (DM) for write data

• Auto precharge option for each burst access

• Programmable burst length: 2, 4, 8

• Programmable /CAS latency (CL): 3

• Programmable output driver strength: normal/weak

• Refresh cycles: (8192 refresh cycles /64ms)
 7.8µs maximum average periodic refresh interval

• 2 variations of refresh
 Auto refresh
 Self refresh

Document No. E0355E30 (Ver. 3.0)
Date Published June 2003 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2003

EBD52UC8AKFA-5

Ordering Information

Part number

EBD52UC8AKFA-5B
EBD52UC8AKFA-5C

Pin Configurations

Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name

1 VREF 47 NC 93 VSS 139 VSS

2 DQ0 48 A0 94 DQ4 140 NC

3 VSS 49 NC 95 DQ5 141 A10

4 DQ1 50 VSS 96 VDD 142 NC

5 DQS0 51 NC 97 DM0/DQS9 143 VDD

6 DQ2 52 BA1 98 DQ6 144 NC

7 VDD 53 DQ32 99 DQ7 145 VSS

8 DQ3 54 VDD 100 VSS 146 DQ36

9 NC 55 DQ33 101 NC 147 DQ37

10 NC 56 DQS4 102 NC 148 VDD

11 VSS 57 DQ34 103 NC 149 DM4/DQS13

12 DQ8 58 VSS 104 VDD 150 DQ38

13 DQ9 59 BA0 105 DQ12 151 DQ39

14 DQS1 60 DQ35 106 DQ13 152 VSS

15 VDD 61 DQ40 107 DM1/DQS10 153 DQ44

16 CK1 62 VDD 108 VDD 154 /RAS

17 /CK1 63 /WE 109 DQ14 155 DQ45

18 VSS 64 DQ41 110 DQ15 156 VDD

19 DQ10 65 /CAS 111 CKE1 157 /CS0

20 DQ11 66 VSS 112 VDD 158 /CS1

21 CKE0 67 DQS5 113 NC 159 DM5/DQS14

22 VDD 68 DQ42 114 DQ20 160 VSS

23 DQ16 69 DQ43 115 A12 161 DQ46

24 DQ17 70 VDD 116 VSS 162 DQ47

25 DQS2 71 NC 117 DQ21 163 NC

26 VSS 72 DQ48 118 A11 164 VDD

27 A9 73 DQ49 119 DM2/DQS11 165 DQ52

28 DQ18 74 VSS 120 VDD 166 DQ53

29 A7 75 /CK2 121 DQ22 167 NC

Data rate
Mbps (max.)

400

Component JEDEC speed bin
(CL-tRCD-tRP)

DDR400B (3-3-3)
DDR400C (3-4-4)

Front side

1 pin

93 pin 144 pin 145 pin184 pin

Back side

Package

184-pin DIMM Gold

52 pin53 pin 92 pin

Contact
pad Mounted devices

EDD2508AKTA-5B
EDD2508AKTA-5B, -5C

Preliminary Data Sheet E0355E30 (Ver. 3.0)

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EBD52UC8AKFA-5

Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name

30 VDD 76 CK2 122 A8 168 VDD

31 DQ19 77 VDD 123 DQ23 169 DM6/DQS15

32 A5 78 DQS6 124 VSS 170 DQ54

33 DQ24 79 DQ50 125 A6 171 DQ55

34 VSS 80 DQ51 126 DQ28 172 VDD

35 DQ25 81 VSS 127 DQ29 173 NC

36 DQS3 82 VDDID 128 VDD 174 DQ60

37 A4 83 DQ56 129 DM3/DQS12 175 DQ61

38 VDD 84 DQ57 130 A3 176 VSS

39 DQ26 85 VDD 131 DQ30 177 DM7/DQS16

40 DQ27 86 DQS7 132 VSS 178 DQ62

41 A2 87 DQ58 133 DQ31 179 DQ63

42 VSS 88 DQ59 134 NC 180 VDD

43 A1 89 VSS 135 NC 181 SA0

44 NC 90 NC 136 VDD 182 SA1

45 NC 91 SDA 137 CK0 183 SA2

46 VDD 92 SCL 138 /CK0 184 VDDSPD

Preliminary Data Sheet E0355E30 (Ver. 3.0)

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EBD52UC8AKFA-5

Pin Description

Pin name Function

Address input

A0 to A12

BA0, BA1 Bank select address

DQ0 to DQ63 Data input/output

/RAS Row address strobe command

/CAS Column address strobe command

/WE Write enable

/CS0, /CS1 Chip select

CKE0, CKE1 Clock enable

CK0 to CK2 Clock input

/CK0 to /CK2 Differential clock input

DQS0 to DQS7 Input and output data strobe

DM0 to DM7/DQS9 to DQS16 Input mask

SCL Clock input for serial PD

SDA Data input/output for serial PD

SA0 to SA2 Serial address input

VDD Power for internal circuit

VDDSPD Power for serial EEPROM

VREF Input reference voltage

VSS Ground

VDDID VDD identification flag

NC No connection

Row address A0 to A12
Column address A0 to A9

Preliminary Data Sheet E0355E30 (Ver. 3.0)

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EBD52UC8AKFA-5

Serial PD Matrix

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

0

1

2 Memory type 0 0 0 0 0 1 1 1 07H DDR SDRAM

3 Number of row address 0 0 0 0 1 1 0 1 0DH 13

4 Number of column address 0 0 0 0 1 0 1 0 0AH 10

5 Number of DIMM ranks 0 0 0 0 0 0 1 0 02H 2

6 Module data width 0 1 0 0 0 0 0 0 40H 64

7 Module data width continuation 0 0 0 0 0 0 0 0 00H 0

8 Voltage interface level of this assembly 0 0 0 0 0 1 0 0 04H SSTL2

9 DDR SDRAM cycle time, CL = 3 0 1 0 1 0 0 0 0 50H 5.0ns*1

10 SDRAM access from clock (tAC) 0 1 1 1 0 0 0 0 70H 0.7ns*1

11 DIMM configuration type 0 0 0 0 0 0 0 0 00H None.

12 Refresh rate/type 1 0 0 0 0 0 1 0 82H 7.8µs
13 Primary SDRAM width 0 0 0 0 1 0 0 0 08H × 8

14 Error checking SDRAM width 0 0 0 0 0 0 0 0 00H None.

15

16

17

18

19

20

21 SDRAM module attributes 0 0 1 0 0 0 0 0 20H

22 SDRAM device attributes: General 1 1 0 0 0 0 0 0 C0H VDD ± 0.2V

23 Minimum clock cycle time at CL = 2.5 0 1 1 0 0 0 0 0 60H 6.0ns*1

24

25 Minimum clock cycle time at CL = 2 0 1 1 1 0 1 0 1 75H 0.75ns*1

26

27

-5C 0 1 0 0 1 0 0 0 48H 18ns

28

29

-5C 0 1 0 0 1 0 0 0 48H 18ns

30

31 Module rank density 0 1 0 0 0 0 0 0 40H 256M bytes

Number of bytes utilized by module
manufacturer

Total number of bytes in serial PD
device

SDRAM device attributes:
Minimum clock delay back-to-back
column access

SDRAM device attributes:
Burst length supported

SDRAM device attributes: Number of
banks on SDRAM device

SDRAM device attributes:
/CAS latency

SDRAM device attributes:
/CS latency

SDRAM device attributes:
/WE latency

Maximum data access time (tAC) from
clock at CL = 2.5

Maximum data access time (tAC) from
clock at CL = 2

Minimum row precharge time (tRP)

-5B

Minimum row active to row active
delay (tRRD)

Minimum /RAS to /CAS delay (tRCD)

-5B

Minimum active to precharge time
(tRAS)

1 0 0 0 0 0 0 0 80H 128 bytes

0 0 0 0 1 0 0 0 08H 256 bytes

0 0 0 0 0 0 0 1 01H 1 CLK

0 0 0 0 1 1 1 0 0EH 2, 4, 8

0 0 0 0 0 1 0 0 04H 4

0 0 0 1 1 1 0 0 1CH 2, 2.5, 3

0 0 0 0 0 0 0 1 01H 0

0 0 0 0 0 0 1 0 02H 1

Differential
Clock

0 1 1 1 0 0 0 0 70H 0.7ns*1

0 1 1 1 0 1 0 1 75H 0.75ns*1

0 0 1 1 1 1 0 0 3CH 15ns

0 0 1 0 1 0 0 0 28H 10ns

0 0 1 1 1 1 0 0 3CH 15ns

0 0 1 0 1 0 0 0 28H 40ns

Preliminary Data Sheet E0355E30 (Ver. 3.0)

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EBD52UC8AKFA-5

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

32

33

34

35 Data input hold time after clock (tDH) 0 1 0 0 0 0 0 0 40H 0.4ns*1

36 to 40 Superset information 0 0 0 0 0 0 0 0 00H Future use

41

-5C 0 0 1 1 1 1 0 0 3CH 60ns*1

42

43 SDRAM tCK cycle max. (tCK max.) 0 0 1 0 0 0 0 0 20H 8ns*1

44 Dout to DQS skew 0 0 1 0 1 0 0 0 28H 0.4ns*1

45 Data hold skew (tQHS) 0 1 0 1 0 0 0 0 50H 0.5ns*1

46 to 61 Superset information 0 0 0 0 0 0 0 0 00H Future use

62 SPD Revision 0 0 0 0 0 0 0 0 00H

63

-5C 0 1 1 1 1 1 0 0 7CH

64 to 65 Manufacturer’s JEDEC ID code 0 1 1 1 1 1 1 1 7FH

66 Manufacturer’s JEDEC ID code 1 1 1 1 1 1 1 0 FEH Elpida Memory

67 to 71 Manufacturer’s JEDEC ID code 0 0 0 0 0 0 0 0 00H

72 Manufacturing location × × × × × × × × ××

73 Module part number 0 1 0 0 0 1 0 1 45H E

74 Module part number 0 1 0 0 0 0 1 0 42H B

75 Module part number 0 1 0 0 0 1 0 0 44H D

76 Module part number 0 0 1 1 0 1 0 1 35H 5

77 Module part number 0 0 1 1 0 0 1 0 32H 2

78 Module part number 0 1 0 1 0 1 0 1 55H U

79 Module part number 0 1 0 0 0 0 1 1 43H C

80 Module part number 0 0 1 1 1 0 0 0 38H 8

81 Module part number 0 1 0 0 0 0 0 1 41H A

82 Module part number 0 1 0 0 1 0 1 1 4BH K

83 Module part number 0 1 0 0 0 1 1 0 46H F

84 Module part number 0 1 0 0 0 0 0 1 41H A

85 Module part number 0 0 1 0 1 1 0 1 2DH —

86 Module part number 0 0 1 1 0 1 0 1 35H 5

87

-5C 0 1 0 0 0 0 1 1 43H C

88 to 90 Module part number 0 0 1 0 0 0 0 0 20H (Space)

91 Revision code 0 0 1 1 0 0 0 0 30H Initial

92 Revision code 0 0 1 0 0 0 0 0 20H (Space)

Address and command setup time
before clock (tIS)

Address and command hold time after
clock (tIH)

Data input setup time before clock
(tDS)

Active command period (tRC)

-5B

Auto refresh to active/
Auto refresh command cycle (tRFC)

Checksum for bytes 0 to 62

-5B

Module part number

-5B

0 1 1 0 0 0 0 0 60H 0.6ns

0 1 1 0 0 0 0 0 60H 0.6ns*1

0 1 0 0 0 0 0 0 40H 0.4ns*1

0 0 1 1 0 1 1 1 37H 55ns*1

0 1 0 0 0 1 1 0 46H 70ns*1

0 1 0 1 1 1 1 1 5FH

0 1 0 0 0 0 1 0 42H B

*1

Continuation
code

(ASCII-8bit
code)

Preliminary Data Sheet E0355E30 (Ver. 3.0)

6