ELPID EBS26UC6APS-80L, EBS26UC6APS-80, EBS26UC6APS-7AL, EBS26UC6APS-7A, EBS26UC6APS-75L Datasheet

DATA SHEET

256MB SDRAM S.O.DIMM

EBS26UC6APS (32M words ×××× 64 bits, 2 bank)

Description

The EBS26UC6APS is 32M words × 64 bits, 2 banks

Synchronous Dynamic RAM Small Outline Dual In-line
Memory Module (S.O.DIMM), mounted 8 pieces of
256M bits SDRAM (EDS2516APTA) sealed in TSOP
package. This module provides high density and large
quantities of memory in a small space without utilizing
the surface mounting technology. Decoupling
capacitors are mounted on power supply line for noise
reduction.

Features

• Fully compatible with 8 bytes S.O.DIMM: JEDEC

standard outline

• 144-pin socket type small outline dual in line memory

module (S.O.DIMM)

 PCB height: 31.75mm (1.25inch )
 Lead pitch: 0.80mm

• 3.3V power supply

• Clock frequency: 100MHz/133MHz (max.)

• LVTTL interface

• Data bus width: × 64 non-ECC

• Single pulsed /RAS

• 4 Banks can operates simultaneously and

independently

• Burst read/write operation and burst read/single write

operation capability

• Programmable burst length (BL): 1, 2, 4, 8, Full page

• 2 variations of burst sequence
 Sequential
 Interleave

• Programmable /CAS latency (CL): 2, 3

• Byte control by DQMB

• Refresh cycles: 8192 refresh cycles/64ms

• 2 variations of refresh
 Auto refresh
 Self refresh

Document No. E0225E20 (Ver. 2.0)
Date Published December 2001 (K) Japan
URL: http://www.elpida.com

C

Elpida Memory, Inc. 2001

Ordering Information

Part number

EBS26UC6APS-7A
EBS26UC6APS-75 *
EBS26UC6APS-80

EBS26UC6APS-7AL
EBS26UC6APS-75L*
EBS26UC6APS-80L

Note: 100MHz operation at /CAS latency = 2.

Clock frequency
MHz (max.)

133
133
100

133
133
100

/CAS latency Package

2, 3
3
2, 3

2, 3
3
2, 3

Pin Configurations

1pin 59pin 61pin 143pin

2pin 60pin 62pin 144pin

EBS26UC6APS

Contact pad

144-pin S.O.DIMM Gold EDS2516APTA

Front Side

Mounted devices

Back Side

Front side Back side

Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name

1 VSS 73 NC 2 VSS 74 CLK1

3 DQ0 75 VSS 4 DQ32 76 VSS

5 DQ1 77 NC 6 DQ33 78 NC

7 DQ2 79 NC 8 DQ34 80 NC

9 DQ3 81 VDD 10 DQ35 82 VDD

11 VDD 83 DQ16 12 VDD 84 DQ48

13 DQ4 85 DQ17 14 DQ36 86 DQ49

15 DQ5 87 DQ18 16 DQ37 88 DQ50

17 DQ6 89 DQ19 18 DQ38 90 DQ51

19 DQ7 91 VSS 20 DQ39 92 VSS

21 VSS 93 DQ20 22 VSS 94 DQ52

23 DQMB0 95 DQ21 24 DQMB4 96 DQ53

25 DQMB1 97 DQ22 26 DQMB5 98 DQ54

27 VDD 99 DQ23 28 VDD 100 DQ55

29 A0 101 VDD 30 A3 102 VDD

31 A1 103 A6 32 A4 104 A7

33 A2 105 A8 34 A5 106 BA0

35 VSS 107 VSS 36 VSS 108 VSS

37 DQ8 109 A9 38 DQ40 110 BA1

39 DQ9 111 A10 (AP) 40 DQ41 112 A11

41 DQ10 113 VDD 42 DQ42 114 VDD

43 DQ11 115 DQMB2 44 DQ43 116 DQMB6

Data Sheet E0225E20 (Ver. 2.0)

2

EBS26UC6APS

Front side Back side

Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name

45 VDD 117 DQMB3 46 VDD 118 DQMB7

47 DQ12 119 VSS 48 DQ44 120 VSS

49 DQ13 121 DQ24 50 DQ45 122 DQ56

51 DQ14 123 DQ25 52 DQ46 124 DQ57

53 DQ15 125 DQ26 54 DQ47 126 DQ58

55 VSS 127 DQ27 56 VSS 128 DQ59

57 NC 129 VDD 58 NC 130 VDD

59 NC 131 DQ28 60 NC 132 DQ60

61 CLK0 133 DQ29 62 CKE0 134 DQ61

63 VDD 135 DQ30 64 VDD 136 DQ62

65 /RAS 137 DQ31 66 /CAS 138 DQ63

67 /WE 139 VSS 68 CKE1 140 VSS

69 /CS0 141 SDA 70 A12 142 SCL

71 /CS1 143 VDD 72 NC 144 VDD

Pin Description

Pin name Function

Address input

A0 to A12

BA0, BA1 Bank select address

DQ0 to DQ63 Data input/output

/CS0, /CS1 Chip select input

/RAS Row enable (/RAS) input

/CAS Column enable (/CAS) input

/WE Write enable input

DQMB0 to DQMB7 Byte data mask

CLK0, CLK1 Clock input

CKE0, CKE1 Clock enable input

SDA Data input/output for serial PD

SCL Clock input for serial PD

VDD Primary positive power supply

VSS Ground

NC No connection

 Row address A0 to A12
 Column address A0 to A8

Data Sheet E0225E20 (Ver. 2.0)

3

EBS26UC6APS

Serial PD Matrix

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

0

1 Total SPD memory size 0 0 0 0 1 0 0 0 08H 256 bytes

2 Memory type 0 0 0 0 0 1 0 0 04H SDRAM

3 Number of row addresses bits 0 0 0 0 1 1 0 1 0DH 13

4 Number of column addresses bits 0 0 0 0 1 0 0 1 09H 9

5 Number of banks 0 0 0 0 0 0 1 0 02H 2

6 Module data width 0 1 0 0 0 0 0 0 40H 64

7 Module data width (continued) 0 0 0 0 0 0 0 0 00H 0

8 Module interface signal levels 0 0 0 0 0 0 0 1 01H LVTTL

9

(-80/80L) 1 0 0 0 0 0 0 0 80H 8ns

10

(-80/80L) 0 1 1 0 0 0 0 0 60H 6ns

11 Module configuration type 0 0 0 0 0 0 0 0 00H None.

12 Refresh rate/type 1 0 0 0 0 0 1 0 82H 7.8µs
13 SDRAM width 0 0 0 1 0 0 0 0 10H × 16

14 Error checking SDRAM width 0 0 0 0 0 0 0 0 00H None.

15

16

17

18

19

20

21 SDRAM device attributes 0 0 0 0 0 0 0 0 00H

22 SDRAM device attributes: General 0 0 0 0 1 1 1 0 0EH

23

(-75/75L, -80/80L) 1 0 1 0 0 0 0 0 A0H 10ns

24

(-75/75L, -80/80L) 0 1 1 0 0 0 0 0 60H 6ns

25 to 26 0 0 0 0 0 0 0 0 00H

27

(-75/75L, -80/80L) 0 0 0 1 0 1 0 0 14H 20ns

Number of bytes used by module
manufacturer

SDRAM cycle time at CL = 3
(highest /CAS latency)
(-7A/7AL, -75/75L)

SDRAM access from Clock at CL = 3
(highest /CAS latency)
(-7A/7AL, -75/75L)

SDRAM device attributes:
minimum clock delay for back-to­back random column addresses

SDRAM device attributes:
Burst lengths supported

SDRAM device attributes: number of
banks on SDRAM device

SDRAM device attributes:
/CAS latency

SDRAM device attributes:
/CS latency

SDRAM device attributes:
/WE latency

SDRAM cycle time at CL = 2
(2nd highest /CAS latency)
(-7A/7AL)

SDRAM access from Clock at CL = 2
(2nd highest /CAS latency)
(-7A/7AL)

Minimum row precharge time
(-7A/7AL)

1 0 0 0 0 0 0 0 80H 128 bytes

0 1 1 1 0 1 0 1 75H 7.5ns

0 1 0 1 0 1 0 0 54H 5.4ns

0 0 0 0 0 0 0 1 01H 1 CLK

1 0 0 0 1 1 1 1 8FH 1,2,4,8,F

0 0 0 0 0 1 0 0 04H 4

0 0 0 0 0 1 1 0 06H 2,3

0 0 0 0 0 0 0 1 01H 0

0 0 0 0 0 0 0 1 01H 0

0 1 1 1 0 1 0 1 75H 7.5ns

0 1 0 1 0 1 0 0 54H 5.4ns

0 0 0 0 1 1 1 1 0FH 15ns

Data Sheet E0225E20 (Ver. 2.0)

4

EBS26UC6APS

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

28

(-80/80L) 0 0 0 1 0 0 0 0 10H 16ns

29

(-75/75L, -80/80L) 0 0 0 1 0 1 0 0 14H 20ns

30

(-80/80L) 0 0 1 1 0 0 0 0 30H 48ns

31 Density of each bank on module 0 0 1 0 0 0 0 0 20H 128MB

32

(-80/80L) 0 0 1 0 0 0 0 0 20H 2ns

33

(-80/80L) 0 0 0 1 0 0 0 0 10H 1ns

34

(-80/80L) 0 0 1 0 0 0 0 0 20H 2ns

35

(-80/80L) 0 0 0 1 0 0 0 0 10H 1ns

36 to 61 Superset information 0 0 0 0 0 0 0 0 00H

62 SPD data revision code 0 0 0 1 0 0 1 0 12H 1.2

63

(-75/75L) 1 0 1 1 1 0 1 0 BAH

(-80/80L) 1 1 1 1 1 0 1 1 FBH

64 Manufacturer’s JEDEC ID code 1 1 1 1 1 1 1 0 FEH Elpida Memory

65 to 71 Manufacturer’s JEDEC ID code 0 0 0 0 0 0 0 0 00H

72 Manufacturing location

73 to 90 Manufacturer’s part number

91 to 92 Revision code

93 to 94 Manufacturing date

95 to 98 Assembly serial number

99 to 125 Manufacturer specific data

126

127

Row active to row active min
(-7A/7AL, -75/75L)

/RAS to /CAS delay min
(-7A/7AL)

Minimum /RAS pulse width
(-7A/7AL, -75/75L)

Address and command signal input
setup time
(-7A/7AL, -75/75L)

Address and command signal input
hold time
(-7A/7AL, -75/75L)

Data signal input setup time
(-7A/7AL, -75/75L)

Data signal input hold time
(-7A/7AL, -75/75L)

Checksum for Bytes 0 to 62
(-7A/7AL)

Reserved (Intel specification
frequency)

Reserved (Intel specification /CAS#
latency support)

0 0 0 0 1 1 1 1 0FH 15ns

0 0 0 0 1 1 1 1 0FH 15ns

0 0 1 0 1 1 0 1 2DH 45ns

0 0 0 1 0 1 0 1 15H 1.5ns

0 0 0 0 1 0 0 0 08H 0.8ns

0 0 0 1 0 1 0 1 15H 1.5ns

0 0 0 0 1 0 0 0 08H 0.8ns

0 1 1 1 1 0 0 1 79H

0 1 1 0 0 1 0 0 64H 100MHz

1 1 0 0 0 1 1 1 C7H

Data Sheet E0225E20 (Ver. 2.0)

5