ELPID EBS25UC8APFA-7A, EBS25UC8APFA-75 Datasheet

DATA SHEET

256MB Unbuffered SDRAM DIMM

EBS25UC8APFA (32M words ×××× 64 bits, 1 bank)

Description

The EBS25UC8APFA is 32M words × 64 bits, 1 bank

Synchronous Dynamic RAM Registered Module,
mounted 8 pieces of 256M bits SDRAM sealed in
TSOP package. This module provides high density
and large quantities of memory in a small space
without utilizing the surface mounting technology.
Decoupling capacitors are mounted on power supply
line for noise reduction.

Features

• Fully compatible with 8 bytes DIMM: JEDEC

standard outline

• 168-pin socket type dual in line memory module

(DIMM)

 PCB height: 34.93mm (1.38inch )
 Lead pitch: 1.27mm

• 3.3V power supply

• Clock frequency: 133MHz (max.)

• LVTTL interface

• Data bus width: × 64 non-ECC

• Single pulsed /RAS

• 4 Banks can operates simultaneously and

independently

• Burst read/write operation and burst read/single write

operation capability

• Programmable burst length (BL): 1, 2, 4, 8

• 2 variations of burst sequence
 Sequential
 Interleave

• Programmable /CAS latency (CL): 2, 3

• Byte control by DQMB

• Refresh cycles: 8192 refresh cycles/64ms

• 2 variations of refresh
 Auto refresh
 Self refresh

Document No. E0210E20 (Ver. 2.0)
Date Published June 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2001-2002

EBS25UC8APFA

Ordering Information

Part number

EBS25UC8APFA-7A
EBS25UC8APFA-75 *

Note: 100MHz operation at /CAS latency = 2.

Pin Configurations

Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name

1 VSS 43 VSS 85 VSS 127 VSS

2 DQ0 44 NC 86 DQ32 128 CKE0

3 DQ1 45 /CS2 87 DQ33 129 NC

4 DQ2 46 DQMB2 88 DQ34 130 DQMB6

5 DQ3 47 DQMB3 89 DQ35 131 DQMB7

6 VDD 48 NC 90 VDD 132 NC

7 DQ4 49 VDD 91 DQ36 133 VDD

8 DQ5 50 NC 92 DQ37 134 NC

9 DQ6 51 NC 93 DQ38 135 NC

10 DQ7 52 NC 94 DQ39 136 NC

11 DQ8 53 NC 95 DQ40 137 NC

12 VSS 54 VSS 96 VSS 138 VSS

13 DQ9 55 DQ16 97 DQ41 139 DQ48

14 DQ10 56 DQ17 98 DQ42 140 DQ49

15 DQ11 57 DQ18 99 DQ43 141 DQ50

16 DQ12 58 DQ19 100 DQ44 142 DQ51

17 DQ13 59 VDD 101 DQ45 143 VDD

18 VDD 60 DQ20 102 VDD 144 DQ52

19 DQ14 61 NC 103 DQ46 145 NC

20 DQ15 62 NC 104 DQ47 146 NC

21 NC 63 NC 105 NC 147 NC

22 NC 64 VSS 106 NC 148 VSS

23 VSS 65 DQ21 107 VSS 149 DQ53

24 NC 66 DQ22 108 NC 150 DQ54

25 NC 67 DQ23 109 NC 151 DQ55

26 VDD 68 VSS 110 VDD 152 VSS

27 /WE 69 DQ24 111 /CAS 153 DQ56

28 DQMB0 70 DQ25 112 DQMB4 154 DQ57

29 DQMB1 71 DQ26 113 DQMB5 155 DQ58

30 /CS0 72 DQ27 114 NC 156 DQ59

Clock frequency
MHz (max.)

133
133

/CAS latency Package

2, 3
3

1 pin 10 pin11 pin 40 pin 41 pin 84 pin

85 pin 94 pin 95 pin 124 pin 125 pin 168 pin

168-pin DIMM Gold EDS2508APTA

Contact pad

Mounted devices

Data Sheet E0210E20 (Ver. 2.0)

2

EBS25UC8APFA

Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name

31 NC 73 VDD 115 /RAS 157 VDD

32 VSS 74 DQ28 116 VSS 158 DQ60

33 A0 75 DQ29 117 A1 159 DQ61

34 A2 76 DQ30 118 A3 160 DQ62

35 A4 77 DQ31 119 A5 161 DQ63

36 A6 78 VSS 120 A7 162 VSS

37 A8 79 CLK2 121 A9 163 CLK3

38 A10 (AP) 80 NC 122 BA0 164 NC

39 BA1 81 NC 123 A11 165 SA0

40 VDD 82 SDA 124 VDD 166 SA1

41 VDD 83 SCL 125 CLK1 167 SA2

42 CLK0 84 VDD 126 A12 168 VDD

Pin Description

Pin name Function

Address input

A0 to A12

BA0, BA1 Bank select address

DQ0 to DQ63 Data input/output

/CS0, /CS2 Chip select input

/RAS Row enable (/RAS) input

/CAS Column enable (/CAS) input

/WE Write enable input

DQMB0 to DQMB7 Byte data mask

CLK0 to CLK3 Clock input

CKE0 Clock enable input

SDA Data input/output for serial PD

SCL Clock input for serial PD

SA0 to SA2 Serial address input

VDD Primary positive power supply

VSS Ground

NC No connection

 Row address A0 to A12
 Column address A0 to A9

Data Sheet E0210E20 (Ver. 2.0)

3

EBS25UC8APFA

Serial PD Matrix

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

0

1 Total SPD memory size 0 0 0 0 1 0 0 0 08H 256 bytes

2 Memory type 0 0 0 0 0 1 0 0 04H SDRAM

3 Number of row addresses bits 0 0 0 0 1 1 0 1 0DH 13

4 Number of column addresses bits 0 0 0 0 1 0 1 0 0AH 10

5 Number of banks 0 0 0 0 0 0 0 1 01H 1

6 Module data width 0 1 0 0 0 0 0 0 40H 64 bits

7 Module data width (continued) 0 0 0 0 0 0 0 0 00H 0

8 Module interface signal levels 0 0 0 0 0 0 0 1 01H LVTTL

9

10

11 Module configuration type 0 0 0 0 0 0 0 0 00H None.

12 Refresh rate/type 1 0 0 0 0 0 1 0 82H 7.8µs

13 SDRAM width

14 Error checking SDRAM width

15

16

17

18

19

20

21 SDRAM device attributes 0 0 0 0 0 0 0 0 00H

22 SDRAM device attributes: General 0 0 0 0 1 1 1 0 0EH

23

(-75) 1 0 1 0 0 0 0 0 A0H 10ns

24

(-75) 0 1 1 0 0 0 0 0 60H 6ns

25 to 26 0 0 0 0 0 0 0 0 00H

27

(-75) 0 0 0 1 0 1 0 0 14H 20ns

28

(-75) 0 0 0 0 1 1 1 1 0FH 15ns

Number of bytes used by module
manufacturer

SDRAM cycle time at CL = 3
(highest /CAS latency)

SDRAM access from Clock at CL = 3
(highest /CAS latency)

SDRAM device attributes:
minimum clock delay for back-to­back random column addresses

SDRAM device attributes:
Burst lengths supported

SDRAM device attributes: number of
banks on SDRAM device

SDRAM device attributes:
/CAS latency

SDRAM device attributes:
/CS latency

SDRAM device attributes:
/WE latency

SDRAM cycle time at CL = 2
(2nd highest /CAS latency)
(-7A)

SDRAM access from Clock at CL = 2
(2nd highest /CAS latency)
(-7A)

Minimum row precharge time
(-7A)

Row active to row active min
(-7A)

1 0 0 0 0 0 0 0 80H 128 bytes

0 1 1 1 0 1 0 1 75H 7.5ns

0 1 0 1 0 1 0 0 54H 5.4ns

0 0 0 0 1 0 0 0 08H × 8

0 0 0 0 0 0 0 0 00H None.

0 0 0 0 0 0 0 1 01H 1 CLK

1 0 0 0 1 1 1 1 8FH 1, 2, 4, 8, F

0 0 0 0 0 1 0 0 04H 4

0 0 0 0 0 1 1 0 06H 2, 3

0 0 0 0 0 0 0 1 01H 0

0 0 0 0 0 0 0 1 01H 0

0 1 1 1 0 1 0 1 75H 7.5ns

0 1 0 1 0 1 0 0 54H 5.4ns

0 0 0 0 1 1 1 1 0FH 15ns

0 0 0 0 1 1 1 1 0FH 15ns

Data Sheet E0210E20 (Ver. 2.0)

4

EBS25UC8APFA

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

29

(-75) 0 0 0 1 0 1 0 0 14H 20ns

30 Minimum /RAS pulse width 0 0 1 0 1 1 0 1 2DH 45ns

31 Density of each bank on module 0 1 0 0 0 0 0 0 40H 256MB

32

33

34 Data signal input setup time 0 0 0 1 0 1 0 1 15H 1.5ns

35 Data signal input hold time 0 0 0 0 1 0 0 0 08H 0.8ns

36 to 61 Superset information 0 0 0 0 0 0 0 0 00H

62 SPD data revision code 0 0 0 1 0 0 1 0 12H 1.2

63

(-75) 1 1 0 1 0 0 1 0 D2H

64 to 65 Manufacturer’s JEDEC ID code 0 1 1 1 1 1 1 1 7FH Continuation code

66 Manufacturer’s JEDEC ID code 1 1 1 1 1 1 1 0 FEH Elpida Memory

67 to 71 Manufacturer’s JEDEC ID code 0 0 0 0 0 0 0 0 00H

72 Manufacturing location

73 to 90 Manufacturer’s part number

91 to 92 Revision code

93 to 94 Manufacturing date

95 to 98 Assembly serial number

99 to 125 Manufacturer specific data

126

127

/RAS to /CAS delay min
(-7A)

Address and command signal input
setup time

Address and command signal input
hold time

Checksum for Bytes 0 to 62
(-7A)

Reserved (Intel specification
frequency)

Reserved (Intel specification /CAS#
latency support)

0 0 0 0 1 1 1 1 0FH 15ns

0 0 0 1 0 1 0 1 15H 1.5ns

0 0 0 0 1 0 0 0 08H 0.8ns

1 0 0 1 0 0 0 1 91H

0 1 1 0 0 1 0 0 64H 100MHz

1 1 1 1 1 1 1 1 FFH

Data Sheet E0210E20 (Ver. 2.0)

5