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ELPID
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EBD11ED8ABFB-6B
Datasheet
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ELPID EBD11ED8ABFB-7B, EBD11ED8ABFB-7A, EBD11ED8ABFB-6B Datasheet

PRELIMINARY DATA SHEET
1GB Unbuffered DDR SDRAM DIMM
(128M words ×××× 72 bits, 2 Banks)

Description

The EBD11ED8ABFB is 128M words × 72 bits, 2
banks Double Data Rate (DDR) SDRAM unbuffered module, mounted 18 pieces of 512M bits DDR SDRAM sealed in TSOP package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each TSOP on the module board.

Features

• 184-pin socket type dual in line memory module
(DIMM)
PCB height: 31.75mm Lead pitch: 1.27mm
• 2.5V power supply
• Data rate: 333Mbps/266Mbps (max.)
• 2.5 V (SSTL_2 compatible) I/O
• Double Data Rate architecture; two data transfers per
clock cycle
• Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at the receiver
• Data inputs and outputs are synchronized with DQS
• 4 internal banks for concurrent operation
(Component)
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
referenced to both edges of DQS
• Auto precharge option for each burst access
• Programmable burst length: 2, 4, 8
• Programmable /CAS latency (CL): 2, 2.5
• Refresh cycles: (8192 refresh cycles /64ms) 7.8µs maximum average periodic refresh interval
• 2 variations of refresh Auto refresh Self refresh
Document No. E0295E20 (Ver. 2.0) Date Published August 2002 (K) Japan URL: http://www.elpida.com Elpida Memory , Inc. 2002
EBD11ED8ABFB

Ordering Information

Part number
EBD11ED8ABFB -6B EBD11ED8ABFB -7A EBD11ED8ABFB -7B

Pin Configurations

Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name
1 VREF 47 DQS8 93 VSS 139 VSS
2 DQ0 48 A0 94 DQ4 140 DM8/DQS17
3 VSS 49 CB2 95 DQ5 141 A10
4 DQ1 50 VSS 96 VDDQ 142 CB6
5 DQS0 51 CB3 97 DM0/DQS9 143 VDDQ
6 DQ2 52 BA1 98 DQ6 144 CB7
7 VDD 53 DQ32 99 DQ7 145 VSS
8 DQ3 54 VDDQ 100 VSS 146 DQ36
9 NC 55 DQ33 101 NC 147 DQ37
10 NC 56 DQS4 102 NC 148 VDD
11 VSS 57 DQ34 103 NC 149 DM4/DQS13
12 DQ8 58 VSS 104 VDDQ 150 DQ38
13 DQ9 59 BA0 105 DQ12 151 DQ39
14 DQS1 60 DQ35 106 DQ13 152 VSS
15 VDDQ 61 DQ40 107 DM1/DQS10 153 DQ44
16 CK1 62 VDDQ 108 VDD 154 /RAS
17 /CK1 63 /WE 109 DQ14 155 DQ45
18 VSS 64 DQ41 110 DQ15 156 VDDQ
19 DQ10 65 /CAS 111 CKE1 157 /CS0
20 DQ11 66 VSS 112 VDDQ 158 /CS1
21 CKE0 67 DQS5 113 NC 159 DM5/DQS14
22 VDDQ 68 DQ42 114 DQ20 160 VSS
23 DQ16 69 DQ43 115 A12 161 DQ46
24 DQ17 70 VDD 116 VSS 162 DQ47
25 DQS2 71 NC 117 DQ21 163 NC
26 VSS 72 DQ48 118 A11 164 VDDQ
27 A9 73 DQ49 119 DM2/DQS11 165 DQ52
28 DQ18 74 VSS 120 VDD 166 DQ53
Data rate Mbps (max.)
333 266 266
Component JEDEC speed bin (CL-tRCD-tRP)
DDR333B (2.5-3-3) DDR266A (2-3-3) DDR266B (2.5-3-3)
Front side
1 pin
93 pin 144 pin 145 pin184 pin
Back side
52 pin53 pin 92 pin
Package
184-pin DIMM
Contact pad
Gold EDD5108ABTA
Mounted devices
Preliminary Data Sheet E0295E20 (Ver. 2.0)
2
EBD11ED8ABFB
Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name
29 A7 75 /CK2 121 DQ22 167 NC
30 VDDQ 76 CK2 122 A8 168 VDD
31 DQ19 77 VDDQ 123 DQ23 169 DM6/DQS15
32 A5 78 DQS6 124 VSS 170 DQ54
33 DQ24 79 DQ50 125 A6 171 DQ55
34 VSS 80 DQ51 126 DQ28 172 VDDQ
35 DQ25 81 VSS 127 DQ29 173 NC
36 DQS3 82 VDDID 128 VDDQ 174 DQ60
37 A4 83 DQ56 129 DM3/DQS12 175 DQ61
38 VDD 84 DQ57 130 A3 176 VSS
39 DQ26 85 VDD 131 DQ30 177 DM7/DQS16
40 DQ27 86 DQS7 132 VSS 178 DQ62
41 A2 87 DQ58 133 DQ31 179 DQ63
42 VSS 88 DQ59 134 CB4 180 VDDQ
43 A1 89 VSS 135 CB5 181 SA0
44 CB0 90 NC 136 VDDQ 182 SA1
45 CB1 91 SDA 137 CK0 183 SA2
46 VDD 92 SCL 138 /CK0 184 VDDSPD
Preliminary Data Sheet E0295E20 (Ver. 2.0)
3
EBD11ED8ABFB

Pin Description

Pin name Function
Address input
A0 to A12
BA0, BA1 Bank select address
DQ0 to DQ63 Data input/output
CB0 to CB7 Check bit (Data input/output)
/RAS Row address strobe command
/CAS Column address strobe command
/WE Write enable
/CS0, /CS1 Chip select
CKE0, CKE1 Clock enable
CK0 to CK2 Clock input
/CK0 to /CK2 Differential clock input
DQS0 to DQS8 Input and output data strobe
DM0 to DM8/DQS9 to DQS17 Input mask
SCL Clock input for serial PD
SDA Data input/output for serial PD
SA0 to SA2 Serial address input
VDD Power for internal circuit
VDDQ Power for DQ circuit
VDDSPD Power for serial EEPROM
VREF Input reference voltage
VSS Ground
VDDID VDD identification flag
NC No connection
Row address A0 to A12 Column address A0 to A9, A11
Preliminary Data Sheet E0295E20 (Ver. 2.0)
4
EBD11ED8ABFB

Serial PD Matrix

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
0
1
2 Memory type 0 0 0 0 0 1 1 1 07H DDR SDRAM
3 Number of row address 0 0 0 0 1 1 0 1 0DH 13
4 Number of column address 0 0 0 0 1 0 1 1 0BH 11
5 Number of DIMM banks 0 0 0 0 0 0 1 0 02H 2
6 Module data width 0 1 0 0 1 0 0 0 48H 72 bits
7 Module data width continuation 0 0 0 0 0 0 0 0 00H 0
8 Voltage interface level of this assembly 0 0 0 0 0 1 0 0 04H SSTL2
9
-7A, -7B 0 1 1 1 0 1 0 1 75H 7.5ns*1
10
-7A, -7B 0 1 1 1 0 1 0 1 75H 0.75ns*1
11 DIMM configuration type 0 0 0 0 0 0 1 0 02H ECC
12 Refresh rate/type 1 0 0 0 0 0 1 0 82H 7.6µs 13 Primary SDRAM width 0 0 0 0 1 0 0 0 08H × 8 14 Error checking SDRAM width 0 0 0 0 1 0 0 0 08H × 8
15
16
17
18
19
20
21 SDRAM module attributes 0 0 1 0 0 0 0 0 20H
22 SDRAM device attributes: General 1 1 0 0 0 0 0 0 C0H VDD ± 0.2V
23
-7B 1 0 1 0 0 0 0 0 A0H 10ns*1
24
-7A, -7B 0 1 1 1 0 1 0 1 75H 0.75ns*1
25 to 26 0 0 0 0 0 0 0 0 00H
27
-7A, -7B 0 1 0 1 0 0 0 0 50H 20ns
Number of bytes utilized by module manufacturer
Total number of bytes in serial PD device
DDR SDRAM cycle time, CL = 2.5
-6B
SDRAM access from clock (tAC)
-6B
SDRAM device attributes: Minimum clock delay back-to-back column access
SDRAM device attributes: Burst length supported
SDRAM device attributes: Number of banks on SDRAM device
SDRAM device attributes: /CAS latency
SDRAM device attributes: /CS latency
SDRAM device attributes: /WE latency
Minimum clock cycle time at CL = 2
-6B, -7A
Maximum data access time (tAC) from clock at CL = 2
-6B
Minimum row precharge time (tRP)
-6B
1 0 0 0 0 0 0 0 80H 128 bytes
0 0 0 0 1 0 0 0 08H 256 bytes
0 1 1 0 0 0 0 0 60H 6.0ns*
0 1 1 1 0 0 0 0 70H 0.7ns*1
0 0 0 0 0 0 0 1 01H 1 CLK
0 0 0 0 1 1 1 0 0EH 2,4,8
0 0 0 0 0 1 0 0 04H 4
0 0 0 0 1 1 0 0 0CH 2, 2.5
0 0 0 0 0 0 0 1 01H 0
0 0 0 0 0 0 1 0 02H 1
0 1 1 1 0 1 0 1 75H 7.5ns*
0 1 1 1 0 0 0 0 70H 0.7ns*1
0 1 0 0 1 0 0 0 48H 18ns
1
Differential Clock
1
Preliminary Data Sheet E0295E20 (Ver. 2.0)
5
EBD11ED8ABFB
Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
Minimum row active to row active
28
-7A, -7B 0 0 1 1 1 1 0 0 3CH 15ns
29
-7A, -7B 0 1 0 1 0 0 0 0 50H 20ns
30
-7A, -7B 0 0 1 0 1 1 0 1 2DH 45ns
31 Module bank density 1 0 0 0 0 0 0 0 80H 512M bytes
32
-7A, -7B 1 0 0 1 0 0 0 0 90H 0.9ns*1
33
-7A, -7B 1 0 0 1 0 0 0 0 90H 0.9ns*1
34
-7A, -7B 0 1 0 1 0 0 0 0 50H 0.5ns*1
35
-7A, -7B 0 1 0 1 0 0 0 0 50H 0.5ns*1
36 to 40 Superset information 0 0 0 0 0 0 0 0 00H Future use
41
-7A, -7B 0 1 0 0 0 1 0 0 44H 68ns*1
42
-7A, -7B 0 1 0 0 1 0 1 1 4BH 75ns*1
43 SDRAM tCK cycle max. (tCK max.) 0 0 1 1 0 0 0 0 30H 12ns*1
44
-7A, -7B 0 0 1 1 0 0 1 0 32H 500ps*1
45
-7A, -7B 0 1 1 1 0 1 0 1 75H 750ps*1
46 to 61 Superset information 0 0 0 0 0 0 0 0 00H Future use
62 SPD Revision 0 0 0 0 0 0 0 0 00H
63
-7A 0 0 0 0 1 1 1 0 0EH
-7B 0 0 1 1 1 0 0 1 39H
64 to 65 Manufacturer’s JEDEC ID code 0 1 1 1 1 1 1 1 7FH
delay (tRRD)
-6B
Minimum /RAS to /CAS delay (tRCD)
-6B
Minimum active to precharge time (tRAS)
-6B
Address and command setup time before clock (tIS)
-6B
Address and command hold time after clock (tIH)
-6B
Data input setup time before clock (tDS)
-6B
Data input hold time after clock (tDH)
-6B
Active command period (tRC)
-6B
Auto refresh to active/ Auto refresh command cycle (tRFC)
-6B
Dout to DQS skew
-6B
Data hold skew (tQHS)
-6B
Checksum for bytes 0 to 62
-6B
0 0 1 1 0 0 0 0 30H 12ns
0 1 0 0 1 0 0 0 48H 18ns
0 0 1 0 1 0 1 0 2AH 42ns
0 1 1 1 0 1 0 1 75H 0.75ns*1
0 1 1 1 0 1 0 1 75H 0.75ns*1
0 1 0 0 0 1 0 1 45H 0.45ns*1
0 1 0 0 0 1 0 1 45H 0.45ns*1
0 0 1 1 1 1 0 0 3CH 60ns*
1
0 1 0 0 1 0 0 0 48H 75ns*1
0 0 1 0 1 1 0 1 2DH 450ps*
0 1 0 1 0 1 0 1 55H 550ps*
1
1
0 1 0 1 0 1 0 0 54H
Continuation code
Preliminary Data Sheet E0295E20 (Ver. 2.0)
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