ELANT EL4585CS, EL4585CN Datasheet
EL4585C
Horizontal Genlock, 8 F
EL4585C March 1996 Rev C
SC
Features
# 36 MHz, general purpose PLL
# 8F
timing. (Use the EL4584
SC
for4F
SC
)
# Compatible with EL4583C Sync
Separator
# VCXO, Xtal, or LC tank
oscillator
k
#
2nS jitter (VCXO)
# User-controlled PLL capture and
lock
# Compatible with NTSC and PAL
TV formats
# 8 pre-programmed popular TV
scan rate clock divisors
# Single 5V, low current operation
Applications
# Pixel Clock regeneration
# Video compression engine
(MPEG) clock generator
# Video Capture or digitization
# PIP (Picture In Picture) timing
generator
# Text or Graphics overlay timing
Ordering Information
Part No. Temp. Range Package Outline
EL4585CNb40§Cto
EL4585CS
For 3Fsc and 4Fsc clock frequency operation,
see EL4584 datasheet.
a
85§C 16-Pin DIP MDP0031
b
40§Ctoa85§C 16-Lead SO MDP0027
Demo Board
A demo PCB is available for this
product. Request ‘‘EL4584/5 Demo
Board’’.
General Description
The EL4585C is a PLL (Phase Lock Loop) sub system, designed
for video applications, but also suitable for general purpose use
up to 36 MHz. In a video application this device generates a
TTL/CMOS compatible Pixel Clock (Clk Out) which is a multiple of the TV Horizontal scan rate, and phase locked to it.
The reference signal is a horizontal sync signal, TTL/CMOS
format, which can be easily derived from an analog composite
video signal with the EL4583 Sync Separator. An input signal
to ‘‘coast’’ is provided for applications where periodic disturbances are present in the reference video timing such as VTR
head switching. The Lock detector output indicates correct lock.
The divider ratio is four ratios for NTSC and four similar ratios
for the PAL video timing standards, by external selection of
three control pins. These four ratios have been selected for common video applications including 8 F
,6FSC, 27 MHz (CCIR
SC
601 format) and square picture elements used in some workstation graphics. To generate 4 F
,3FSC, 13.5 MHz (CCIR 601
SC
format) etc., use the EL4584, which does not have the additional divide by 2 stage of the EL4585.
For applications where these frequencies are inappropriate or
for general purpose PLL applications the internal divider can be
by passed and an external divider chain used.
FREQUENCIES and DIVISORS
Function 6Fsc CCIR 601 Square 8Fsc
Divisor* 1702 1728 1888 2270
Ý
PAL Fosc (MHz) 26.602 27.0 29.5 35.468
Divisor* 1364 1716 1560 1820
NTSC Fosc (MHz) 21.476 27.0 24.546 28.636
CCIR 601 divisors yield 1440 pixels in the active portion of each line for NTSC and PAL.
Square pixels format gives 640 pixels for NTSC and 768 pixels for PAL.
6Fsc frequencies do not yield integer divisors.
*Divisor does not include
d
2 block.
Connection Diagram
EL4585 SO, P-DIP Packages
4585– 17
Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a ‘‘controlled document’’. Current revisions, if any, to these
specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation.
©
1995 Elantec, Inc.
Ý
4585C
EL4585C
Horizontal Genlock, 8 F
SC
Absolute Maximum Ratings
Supply 7V
V
CC
Storage Temperature
b
65§Ctoa150§C
Lead Temperature 260
Pin Voltages
Operating Ambient Temperature Range
Important Note:
All parameters having Min/Max specifications are guaranteed. The Test Level column indicates the specific device testing actually
performed during production and Quality inspection. Elantec performs most electrical tests using modern high-speed automatic test
equipment, specifically the LTX77 Series system. Unless otherwise noted, all tests are pulsed tests, therefore T
Test Level Test Procedure
I 100% production tested and QA sample tested per QA test plan QCX0002.
II 100% production tested at T
III QA sample tested per QA test plan QCX0002.
IV Parameter is guaranteed (but not tested) by Design and Characterization Data.
V Parameter is typical value at T
T
MAX
and T
b
0.5V to V
b
A
per QA test plan QCX0002.
MIN
DC Electrical Characteristics
Parameter Conditions Temp Min Typ Max
I
DD
V
Input Low Voltage 25§C 1.5 I V
IL
e
V
5V (Note 1) 25§C24ImA
DD
e
(T
25§C)
A
C
§
a
0.5V
CC
40§Ctoa85§C
e
25§C and QA sample tested at T
e
25§C for information purposes only.
A
e
(V
DD
5V, T
e
A
Operating Junction Temp 125
Power Dissipation 400mW
Oscillator Frequency 36MHz
e
e
T
J
C
e
25§C,
A
25§C unless otherwise noted)
Test
Level
TA.
C
§
Units
VIHInput High Voltage 25§C 3.5 I V
IILInput Low Current All inputs except COAST, V
IIHInput High Current All inputs except COAST, V
IILInput Low Current COAST pin, V
IIHInput High Current COAST pin, V
VOLOutput Low Voltage Lock Det, I
VOHOutput High Voltage Lock Det, I
VOLOutput Low Voltage CLK, I
VOHOutput High Voltage CLK, I
VOLOutput Low Voltage OSC Out, I
VOHOutput High Voltage OSC Out, I
IOLOutput Low Current Filter Out, V
IOHOutput High Current Filter Out, V
IOL/IOHCurrent Ratio Filter Out, V
I
Filter Out Coast Mode, V
LEAK
e
1.5V 25§C
in
e
3.5V 25§C 60 100 I mA
in
e
1.6mA 25§C 0.4 I V
OL
eb
1.6mA 25§C 2.4 I V
OH
e
3.2mA 25§C 0.4 I V
OL
eb
3.2mA 25§C 2.4 I V
OH
e
200mA25
OL
eb
200mA25
OH
e
2.5V 25§C 200 300 I mA
OUT
e
2.5V 25§C
OUT
e
2.5V 25§C 1.05 1.0 0.95 I
OUT
l
V
DD
OUT
e
1.5V 25§C
in
e
3.5V 25§C 100 I nA
in
l
0V 25§C
b
100 I nA
b
C 0.4 I V
§
C 2.4 I V
§
b
100
100
b
60 I mA
b
b
300
g
200 I mA
1 100 I nA
Note 1: All inputs to 0V, COAST floating.
TD is 3.5in
2
EL4585C
Horizontal Genlock, 8 F
e
AC Electrical Characteristics
Parameter Conditions Temp Min Typ Max
VCO Gain@20 MHz Test circuit 1 25§C 15.5 V dB
H-sync S/N Ratio V
Jitter VCXO Oscillator 25§C1 Vns
Jitter LC Oscillator (Typ) 25§C10 Vns
Note 2: Noisy video signal input to EL4583C, H-sync input to EL4585C. Test for positive signal lock.
e
5V (Note 2) 25§C35 V dB
DD
(V
DD
Pin Description
Pin No. Pin Name Function
16, 1, 2 Prog A,B,C Digital inputs to selectdN value for internal counter. See table below for values.
3 Osc/VCO Out Output of internal inverter/oscillator. Connect to external crystal or LC tank VCO circuit.
4V
5 Osc/VCO In Input from external VCO.
6V
7 Charge Pump Connect to loop filter. If the H-sync phase is leading or H-sync frequencylCLKd2N, current is
8 Div Select Divide select input. When high, the internal divider is enabled and EXT DIV becomes a test pin,
9 Coast Tri-state logic input. Low(k(/3*VCC)enormal mode, Hi Z(or (/3 to )/3*VCC)efast lock mode,
10 H-sync In Horizontal sync pulse (CMOS level) input.
11 VDD(D) Positive supply for digital, I/O circuits.
12 Lock Det Lock Detect output. Low level when PLL is locked. Pulses high when out of lock.
13 Ext Div External Divide input when DIV SEL is low, internald2N output when DIV SEL is high.
14 VSS(D) Ground for digital, I/O circuits.
15 CLK Out Buffered output of the VCO.
(A) Analog positive supply for oscillator, PLL circuits.
DD
(A) Analog ground for oscillator, PLL circuits.
SS
Out
pumped into the filter capacitor to increase VCO frequency. If H-sync phase is lagging or frequency
k
CLKd2N, current is pumped out of the filter capacitor to decrease VCO frequency. During coast
mode or when locked, charge pump goes to a high impedance state.
outputting CLK
externaldN.
l
High(
d
2N. When low, the internal divider is disabled and EXT DIV is an input from an
)/3*VCC)ecoast mode.
Table 5. VCO Divisors
Prog A Prog B Prog C Div Value
Pin 16 Pin 1 Pin 2 N
0 0 0 1702
0 0 1 1728
0 1 0 1888
0 1 1 2270
1 0 0 1364
1 0 1 1716
1 1 0 1560
1 1 1 1820
e
5V, T
25§C unless otherwise noted)
A
Test
Level
SC
Units
TD is 3.5in TD is 3.5in
3
EL4585C
Horizontal Genlock, 8 F
Timing Diagrams
PLL Locked Condition (Phase Errore0)
SC
Out of Lock Condition
4585– 2
T
i
e
i
E
T
H
e
T
H-sync period
H
e
phase error period
T
i
c
360
§
Typical Performance Curves
4585– 3
Test Circuit 1
4585– 5
4
EL4585C
Horizontal Genlock, 8 F
SC
Typical Performance Curves
Idd vs Fosc
Typical Varactor
Ð Contd.
4585– 4
OSC Gain vs Fosc
OSC Gain@20 MHz vs Temp
Charge Pump Duty Cycle Vs i
4585– 6
E
4585– 9
4585– 7
EL4585 Block Diagram
4585– 8
4585– 1
5
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