ELANT EL4581CS, EL4581CN Datasheet

EL4581C

Sync Separator, 50% Slice, S-H, Filter

EL4581C January 1996 Rev B

Features

# NTSC, PAL and SECAM sync

separation

# Single supply,

a

5V

# Precision 50% slicing, internal

caps

# Built-in color burst filter
# Decodes non-standard verticals
# Pin compatible with LM1881
# Low power
# Typically 1.5 mA supply current
# Resistor programmable scan rate
# Few external components
# Available in 8-pin DIP and SO-8

pkg.

Applications

# Video special effects
# Video test equipment
# Video distribution
# Displays
# Imaging
# Video data capture
# Video triggers

Ordering Information

Part No. Temp. Range Package Outline

EL4581CNb40§Ctoa85§C 8-Pin DIP MDP0031

EL4581CSb40§Ctoa85§C 8-Lead SO MDP0027

General Description

The EL4581C extracts timing information from standard nega­tive going video sync found in NTSC, PAL, and SECAM broad­cast systems. It can also be used in non standard formats and
with computer graphics systems at higher scan rates, by adjust­ing a single external resistor. When the input does not have
correct serration pulses in the vertical interval, a default verti­cal output is produced.

Outputs are composite sync, vertical sync, burst/back porch
output, and odd/even output. The later operates only in inter­laced scan formats.

The EL4581C provides a reliable method of determining correct
sync slide level by setting it to the mid-point between sync tip
and blanking level at the back porch. This 50% level is deter­mined by two internal self timing sample and hold circuits that
track sync tip and back porch levels. This also provides a degree
of hum and noise rejection to the input signal, and compensates
for varying input levels of 0.5 p-p to 2.0 Vp-p.

A built in linear phase, third order, low pass filter attenuates
the chroma signal in color systems to prevent incorrectly set
color burst from disturbing the 50% sync slide.

This device may be used to replace the industry standard
LM1881, offering improved performance and reduced power
consumption.

The EL4581C video sync separator is manufactured using
Elantec’s high performance analog CMOS process.

Ý

Connection Diagram

Demo Board

EL4581C SO, P-DIP Packages

A dedicated demo board is not
available. However, this device can
be placed on the EL4584/5 Demo
Board.

Top View

Manufactured under U.S. Patent No. 5,528,303

Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a ‘‘controlled document’’. Current revisions, if any, to these
specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation.

©

1993 Elantec, Inc.

4581– 1

EL4581C

Sync Separator, 50% Slice, S-H, Filter

Absolute Maximum Ratings

VCCSupply 7V

b

Storage Temperature

65§Ctoa150§C

Lead Temperature 260

Important Note:
All parameters having Min/Max specifications are guaranteed. The Test Level column indicates the specific device testing actually
performed during production and Quality inspection. Elantec performs most electrical tests using modern high-speed automatic test
equipment, specifically the LTX77 Series system. Unless otherwise noted, all tests are pulsed tests, therefore T

Test Level Test Procedure

I 100% production tested and QA sample tested per QA test plan QCX0002.

II 100% production tested at T

III QA sample tested per QA test plan QCX0002.
IV Parameter is guaranteed (but not tested) by Design and Characterization Data.

V Parameter is typical value at T

T

MAX

and T

MIN

A

per QA test plan QCX0002.

DC Electrical Characteristics

Parameter Description Temp Min Typ Max

I

DD

Clamp Voltage Pin 2, Unloaded 25§C 1.3 1.5 1.9 I V

Discharge Current Pin 2e2V 25§C 6 10 20 I mA

Clamp Charge Current Pin 2, V

Ref Voltage Pin 6, V

VOLOutput Low Voltage I

VOHOutput High Voltage I

Note 1: No video signal, outputs unloaded.
Note 2: Tested for V

5Vg5% which guarantees timing of output pulses over this range.

DD

e

V

5V (Note 1) 25§C 0.75 1.7 3 I mA

DD

e

IN

e

DD

e

1.6 mA 25§C 800 I mV

OL

eb

40 mA

OH

eb

I

1.6 mA 2.4 I

OH

e

(T

25§C)

A

Pin Voltages

Operating Temperature Range

C

§

e

25§C and QA sample tested at T

e

25§C for information purposes only.

A

Unless otherwise state V

1V 25§C2 3 I mA

5V (Note 2) 25§C 1.5 1.8 2.1 I V

25

C

§

e

25§C,

A

e

DD

4IV

5V, T

e

A

25§C, R

b

0.5V to V

e

set

CC

b

40§Ctoa85§C

e

e

T

TA.

J

C

680 kX.

Test

Level

a

0.5V

Units

V

TDis 1.8in

2

EL4581C

Sync Separator, 50% Slice, S-H, Filter

Dynamic Characteristics

e

V

5V, IVpk-pk video, T

DD

Parameter Description Temp Min Typ Max

Vertical Sync Width, t

Burst/Back Porch Width, t

Vertical Sync Default Delay t

Filter Attenuation F

Composite Sync Prop Delay V

Input Dynamic Range p-p NTSC Signal

Slice Level Input Voltagee1V

Note 3: C/S, Vertical and Burst outputs are all active lowbV
Note 4: Attenuation is a function of Rset (PIN6).
Note 5: Typical min. is 0.3 V
Note 6: Refers to threshold level of sync. tip to back porch amplitude.

Pin Descriptions

Pin No. Pin Name Function

1 Composite Sync Out Composite sync pulse output. Sync pulses start on a falling edge and end on a rising edge.

2 Composite Video in AC coupled composite video input. Sync tip must be at the lowest potential (Positive

3 Vertical Sync Out Vertical sync pulse output. The falling edge of Vert Sync is the start of the vertical period.

4 GND Supply ground.

5 Burst/Back Porch Output Burst/Back porch output. Low during burst portion of composite video.

6R

SET

7 Odd/Even Output Odd/Even field output. Low during odd fields, high during even fields. Transitions occur at

8VDD5V Positive supply. (5V)

Note: R

must be a 1% resistor.

SET

e

A

VS

B

VSD

.

P-P

e

25§C, C

15 pF, I

L

(Note 3) 25§C 190 230 300 I ms

(Note 3) 25§C 2.5 3.5 4.5 I ms

e

IN

b

Composite Sync

IN

(Note 3)

(Note 5)

(Note 6) Full 40% 50% 60% IV

picture phase).

An external resistor to ground sets all internal timing. 681k, 1% resistor will provide correct
timing for NTSC signals.

start of Vert Sync pulse.

eb

1.6 mA, I

OH

3.4 MHz (Note 4) 25§C24 VdB

P-P

OH

e

1.6 mA. Signal voltages are peak to peak.

OL

Test

Level

25§C4055 70 I ms

25

C 260 400 I ns

§

25

C 0.5 2 I V

§

25§C 40% 50% 60% I

e

2.4V, V

OL

e

0.8V.

Units

TDis 2.0in

3

EL4581C

Sync Separator, 50% Slice, S-H, Filter

Typical Performance Characteristics

RSET vs Horizontal
Frequency

Vertical Default Delay
Time vs RSET

Back Porch Clamp
On Time vs RSET

Vertical Pulse Width
vs Temperature

e

Input Signal
EL4581 Filter Characteristic
Constant Delay 240 ns

300 mV

P-P

Vertical Pulse Width
vs RSET

Supply Current
vs Temperature

4581– 2

4