ELAN EM84502BP, EM84502BM, EM84502AP, EM84502AM Datasheet
GENERAL DESCRIPTION
The EM84502 Mouse Controller is specially designed to control PS/2 mouse device.This single chip can
interface three key-switches and four photo-couples direct to 8042. EM84502 can receive command and echo
status or data format which are compatible with IBM PS/2 mode mouse. Key debouncing circuit is provided
to prevent false entry and improve the accuracy.
In the conventional mouse, a great number of noises are generated when the grid is partially closed or opened.
These noise are usually mistaken for movement signals by conventional mouse controller and the cursor of the
dispaly screen is thus moved frequently up and down or back and forth. This will consumes a great amount of
energy.The EM84502 PS/2 mouse controller provides noise immunity circuits to eliminate these noise
in order to reduce energy consumption.
FEATURES
• Being compatiable with PS/2 mouse mode.
• Built-in noise immunity circuit.
• Low power dissipation.
• RC oscillation.
• Three key-switches and four photo-couples inputs.
• Both key-press and key-release debounce interval 12 ms.
• Through three key-switches input, EM84502 can exert seven different output.
• The motion detector of the EM84502 could sense 8 m/sec maximun with 200 DPI wheels.
EM84502
PS/2 MOUSE CONTROLLER
PS/2 MOUSE CONTROLLER
EM84502
APPLICATIONS
• Optical mouse or pen-mouse.
• Mechanical mouse or pen-mouse.
• Optomechanical mouse or pen-mouse.
• Mechanical track ball.
• Optomechanical track ball.
PIN ASSIGNMENT
EM84502AP
V
DD
OP
OSC.OUT
CLK
DATA
VSS
R
EM84502BP
V
DD
OP
NC
NC
OSC.OUT
CLK
DATA
VSS
EM84502AM
1
2
3
4
5
6
7
OSCR
14
Y2
13
Y1
12
X2
11
X1
10
L
9
M
8
V
OSC.OUT
CLK
DATA
VSS
OP
DD
1
2
3
4
5
6
7
R
OSCR
14
Y2
13
Y1
12
X2
11
X1
10
L
9
M
8
EM84502BM*
1
16
2
3
4
5
6
7
8
OSCR
15
Y2
14
Y1
13
X2
12
X1
11
L
10
M
9
R
V
OP
NC
NC
OSC.OUT
CLK
DATA
VSS
DD
1
16
2
3
4
5
6
7
8
OSCR
15
Y2
14
Y1
13
X2
12
X1
11
L
10
M
9
R
* (Under developed)
* This specification are subject to be changed without notice.
8.3.2001
1
FUNCTIONAL BLOCK DIAGRAM
T
OP
D
X1
X2
Y1
Y2
L
M
R
OSCR
OSC OU
I
E
M
M
N
T
M
O
O
E
U
T
I
C
N
I
S
T
IT
O
E
O
Y
N
R
D
E
B
O
U
N
C
E
COUNTER
TIMING
CONTROLLER
SYSTEM
CLOCK
GENERATOR
D
A
T
A
PIN DESCRIPTIONS
Symbol I/O Function
C
O
N
V
E
R
T
E
R
DATA
PS/2 MOUSE CONTROLLER
EM84502
D
C
E
O
C
M
O
M
D
A
E
N
R
D
I/O
DATA
CLK
V
DD
Power
OP I X, Y inputs.
Floating : Comparator input.
GND : Schmitt trigger input.
Short to OSC OUT : Testing Mode.
OSCOUT O Clock output.
CLK I/O 8042 auxiliary port CLK line.
DATA I/O 8042 auxiliary port DATA line.
V
SS
Ground
R I Three key-switches exert seven different combinations totally. Both key-pressed
M and key-released signals will be sent accomplanied with horizontal and vertical
L state. The status of the key-switches will be preserved, whenever the value of
horizontal or vertical counters will present at DATA. And the debounce interval
for both key-press and key-release is 12 ms.
X1 I Four photo-couple signals denote UP, DOWN, LEFT, and RIGHT state.
X2 During the scaning period, as long as the photo-couples change their states, the
Y1 value of vertical or horizontal counter will increase or decrease accordingly.
Y2
OSCR I 30 Kohm ±5% pull low for 35 KHz oscillation.
FUNCTION DESCRIPTIONS
A) Operating mode
There are four operating modes in PS/2 mouse:
i). Reset Mode:
In this mode a self-test is initiated during power-on or by a Reset command. After reset signal, PS/2
mouse will send:
1). Completion code AA & ID code 00.
* This specification are subject to be changed without notice.
8.3.2001
2
2). Set default:
sampling rate: 100 reports/s
non-autospeed
stream mode
2 dot/count
disable
ii). Stream Mode:
The maximum rate of transfer is the programmed sample rate.
Data report is transmitted if
1). switch is pressed
2). movement has been detect
iii). Remote Mode:
Data is transmitted only in response to a Read Data command.
iv). Wrap Mode:
PS/2 MOUSE CONTROLLER
EM84502
Any byte of data sent by the system, except hex EC ( Reset wrap mode ) or hex FF ( Reset ), is returned
by EM84502.
B). PS/2 Mouse Data Report:
i). In stream mode: A data report is sent at the end of a sample interval.
ii). In remote mode: A data report is sent in response to Read Data command.
iii). Data report format:
Byte Bit Description
1 0 Left button status; 1 = pressed
1 Right button status; 1 = pressed
2 Middle button status; 1 = pressed
3 Reserve
4 X data sign; 1 = negative
5 Y data sign; 1 = negative
6 X data overflow; 1 = overflow
7 Y data overflow; 1 = overflow
2 0-7 X data ( D0 - D7 )
3 0-7 Y data ( D0 - D7 )
C) PS/2 mouse Data Transmission:
i). EM84502 generates the clocking signal when sending data to and receiving data from the system.
ii). The system requests EM84502 receive system data output by forcing the DATA line to an inactive
level and allowing CLK line to go to an active level.
iii). Data transmission frame:
* This specification are subject to be changed without notice.
8.3.2001
3
PS/2 MOUSE CONTROLLER
Bit Function
1 Start bit ( always 0 )
2-9 Data bits ( D0 - D7 )
10 Parity bit ( odd parity )
11 Stop bit ( always 1 )
iv). Data Output ( data from EM84502 to system ):
If CLK is low ( inhibit status ) , data is no transmission.
If CLK is high and DATA is low ( request-to-send ), data is updated. Data is received from the system
and no transmission are started by EM84502 until CLK and DATA both high. If CLK and DATA are both
high, the transmission is ready. DATA is valid prior to the falling edge of CLK and beyond the rising edge
of CLK. During transmission, EM84502 check for line contention by checking for an inactive level on CLK
at intervals not to exceed 100u sec. Contention occurs when the system lowers CLK to inhibit EM84502
output after EM84502 has started a transmission. If this occurs before the rising edge of the tenth clock,
EM84502 internal store its data in its buffer and returns DATA and CLK to an active level. If the contention
does not occur by the tenth clock, the transmission is complete.
Following a transmission, the system inhibits EM84502 by holding CLK low until it can service the input
or until the system receives a request to send a response from EM84502.
EM84502
v). Data Input ( from system to EM84502 ):
System first check if EM84502 is transmitting data. If EM84502 is transmitting, the system can override
the output forcing CLK to an inactive level prior to the tenth clock. If EM84502 transmission is beyond
the tenth clock, the system receives the data. If EM84502 is not transmitting or if the system choose to
override the output, the system force CLK to an inactive level for a period of not less than 100µ sec while
preparing for output. When the system is ready to output start bit (0), it allows CLK go to active level. If
request-to-send is detected, EM84502 clocks 11 bits. Following the tenth clock EM84502 checks for
an active level on the DATA line, and if found, force DATA low , and clock once more. If occurs framing
error, EM84502 continue to clock until DATA is high, then clocks the line control bit and request a
Resend. When the system sends out a command or data transmission that requires a response, the system
waits for EM84502 to response before sending its next output.
D). PS/2 Mouse Error Handling:
i). A Resend command ( FE ) following receipt of an invalid input or any input with incorrect parity.
ii). If two invalid input are received in succession, an error code of hex FC send to the system.
iii). The counter accumulators are cleared after receiving any command except “Resend”.
iv). EM84501 receives a Resend command ( FE ), it transmit its last packet of data.
v). In the stream mode “Resend” is received by EM84502 following a 3-byte data packet transmission
to the system. EM84502 resend the 3-byte data packet prior to clearing the counter.
vi). A response is sent within 25 ms if
* This specification are subject to be changed without notice.
8.3.2001
4
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