ELAN EM83040BBQ, EM83040BAQ, EM83040BH Datasheet

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* This specification are subject to be changed without notice.

9.14.2001

EM83040B

LCD CONTROLLER

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GENERAL DESCRIPTION

The EM83040B is a dot matrix LCD driver, which is fabricated by low power CMOS technology. This chip
includes 80-bits shift register, 80 bits data latch and 80 bits level driver. A LCD RAM inside can be mapping
to LCD signal. It converts RAM data to parallel data and output waveform to LCD.

FEATURES

(1) Supply power: 2.5~5.5V
(2) LCD drive voltage: 3.6 to15V
(3) Internal RAM: 2.5k x 4 bits
(4) RAM can be controlled by eight signals including four bits data bus.
(5) Duty: 1/32, 1/48, 1/64, 1/80
(6) Build in DC/DC converter: double, triple, quad and five times.
(7) Modularized function: connect to another 83040B to extent LCD matrix
(8) One DC converter enabled and other 83040B can share with this.
(9) Internal regulator output for DC/DC converter controlled by control register.
(10) Chip form (EM83040BH), 128 pin package (14mm x 20mm EM83040BAQ), 160 pin package

(EM83040BBQ)
(11) Bias: 1/5 (32 COMMON), 1/7 (48 COMMON), 1/9 (64 and 80 COMMON) fixed by internal circuit.
(12) Internal RC clock about 250 KHz.

APPLICATION

(1) Data Bank
(2) LCD toy
(3) Education computer

* This specification are subject to be changed without notice.

EM83040B

LCD CONTROLLER

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PIN ASSIGNMENTS

EM83040BAQ

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

39404142434445464748495051525354555657585960616263

64

102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

MAIN

M1
M0
EN
NC
NC
NC
NC

RAMEN

RAMADS

RAMW

RAMR
RAMD3
RAMD2
RMAD1
RAMD0

LOAD

VDD
GND

VOUT

VSS4
VSS3

CB
CA

VSS2+

VSS2-

V1
V2

VREG

NC
NC
NC
NC
NC

V3
V4
V5
O0

O1O2O3O4O5O6O7O8O9

O10

O11

O12

O13

O14

O15

O16

O17

O18

O19

O20

O21

O22

O23

O24

O25

O26

O53
O52
O51
NC
NC
NC
NC
NC
O50
O49
O48
O47
O46
O45
O44
O43
O42
O41
O40
O39
O38
O37
O36
O35
O34
O33
O32
O31
O30
NC
NC
NC
NC
NC
NC
O29
O28
O27

O79

O78

O77

O76

O75

O74

O73

O72

O71

O70

O69

O68

O67

O66

O65

O64

O63

O62

O61

O60

O59

O58

O57

O56

O55

O54

EM83040BAQ

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* This specification are subject to be changed without notice.

9.14.2001

EM83040B

LCD CONTROLLER

PreliminaryPreliminary

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Preliminary

EM83040BBQ

EM83040BBQ

VSS4
VSS3

+

-

VREG

VOUT

* This specification are subject to be changed without notice.

EM83040B

LCD CONTROLLER

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BLOCK DIAGRAM

VREG

V1

REG(5~0)

BIAS

MUX

: : : : :

M1,M0

Buffer1
Buffer2
Buffer3
Buffer4
Buffer5

Regulator

IR(2~0)

Resistance

ratio

VOUT
VSS4
VSS3
CA
CB
VSS2+
VSS2-

5

* This specification are subject to be changed without notice.

9.14.2001

EM83040B

LCD CONTROLLER

PreliminaryPreliminary

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PIN DESCRIPTIONS

Symbol I/O Function

VDD Power System power supply
GND Power Ground
VOUT Power Voltage converter input/output pin

Connect this pin to GND through capacitor
EN=1,VOUT=VDD

VSS4 Power Step-up capacitor

EN=1, VSS4=VDD

VSS3 Power Step-up capacitor

EN=1, VSS3=VDD

VSS2+ Power Step-up capacitor

EN=1, VSS2=VDD
VSS2- Power Step-up capacitor
VREG Power Output voltage regulator terminal. Provides the voltage between V1 and GND

through a resistive voltage divider.
MAIN I Master or slave control signal.

MAIN=1, master unit

MAIN=0, slave unit
EN I This pin control whole chip power. This chip will work when this pin is connected

to ground. And whole chip will disable when connect to VDD voltage.

EN=0 and MAIN=1 the chip will generate VSS2+, VSS2-

VSS3, VSS4, VOUT, LOAD signal and internal RC clock.

EN=1, standby mode
M1 I Mode select
M0 I Mode select
RAMEN RAM read and write control signal.

1 => can not read and write. 0=> can read and write.
RAMADS RAM data select signal

1=> RAM Data, 0=>Address
RAMW RAM write signal, low write
RAMR RAM read signal, low read
RAMD3~RAM RAM data or address bus
D0
LOAD I/O LCD load signal between one COMMON signal to another.

MAIN=1, the master unit will output LOAD signal.

MAIN=0, the slave will accept the signal from master unit.
CA I Coupling capacitor
CB I Coupling capacitor
V1~V5 I Reference voltage input, highest V1°K lowest V5
O1~O80 O LCD waveform output

* This specification are subject to be changed without notice.

EM83040B

LCD CONTROLLER

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FUNCTION DESCRIPTIONS

(1)User can use MAIN pin to chose master unit or slave unit.

MAIN Unit Function

1 MASTER Generate these signals:

Load, CA, CB, VSS2+, VSS2-, VSS3, VSS4, VOUT
Internal RC clock

0 SLAVE Accept these Master unit signals

Load, VOUT, V1, V2, V3, V4, V5
No internal RC clock

(2)User can use M1,M2 to choose four modes. As followed

MASTER MAIN M1 M0 Segment Common BIAS

Mode1 1 0 0 O(16:1)=S(16:1) O(80:17)=C(64:1) 1/9
Mode2 1 0 1 O(80:1)=C(80:1) 1/9
Mode3 1 1 0 O(32:1)=S(32:1) O(80:33)=C(48:1) 1/7
Mode4 1 1 1 O(48:1)=S(48:1) O(80:49)=C(32:1) 1/5

SLAVE MAIN M1 M0 Segment Common BIAS

Mode1 0 0 0 O(80:1)=S(80:1) 1/9
Mode2 0 0 1 O(80:1)=S(80:1) 1/9
Mode3 0 1 0 O(80:1)=S(80:1) 1/7

Mode4 0 1 1 O(80:1)=S(80:1) 1/5
* S=Segment, C=Common
* (M1, M0) for Master must same as Slave unit

(3)RAM control

Write mode

FIG. 3
LCD RAM can be written or read with control signal. The RAMEN pin can select a RAM which can be read or
write. The RAMADS pin can select whether

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* This specification are subject to be changed without notice.

9.14.2001

EM83040B

LCD CONTROLLER

PreliminaryPreliminary

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RAMD(3:0) are data or address of RAM. At the address mode, RAMADS is low and user should sent address
three times, from address (11:8) to address (3:0). Then it will go into data mode when RAMADS is high. In data
mode, user can sent one or more nibble data which address can be increased by internal counter.
Once the RAMEN pin is high, the RAM can not read and write.

(4)Read control

RAMEN

RAMADS

RAMD(3:0)

RAMW

RAMR

A3 A2 A1 D1 D2 D3

RAM enable

RAM disable

ADDRESS

DATA

A3=address (11:8)
A2=address(7:4)

A1=address(3:0)

Ten

Tdv

Tdh

Tdd

FIG. 4
As same as write mode, user has to sent address three times. And read data from RAM one by one which address
can be increased by internal counter. Note!! Be sure to make RAMR low pulse 2uS (Tdv +data) width and 2uS
(Tdd) high width at least.

(5)RAM mapping

RAM address is from 0 to address 2562
User fill “1” to LCD RAM, LCD driver will generate “light” waveform. Otherwise, it will generate a “dark”
waveform. The LCD RAM area is mapped to segment 1 to segment 80 from address 0 to address 19. And user
can refer to fig.5 and Table 1 to get the idea of LCD ram mapping. The other RAM can use as general RAM for
data storage if not mapping to LCD display. And the RAM of address 2560, 2561 and 2562 is control registers.

Table 1: LCD mapping RAM area

Common Segment Master/slave Display area

32 48 Master 1,2,3
32 80 Slave 1,2,3,4
48 32 Master 1,2,5,6
48 80 Slave 1,2,3,4,5,6,7
64 16 Master 1,5,8
64 80 Slave 1,2,3,4,5,6,7,8,9
80 0 Master No mapping RAM
80 80 Slave 1,2,3,4,5,6,7,8,9,10

Any Any Any Area 11 is general RAM