ELAN EM78P458, EM78P459 User Manual

EM78P458/459

OTP ROM

1. GENERAL DESCRIPTION

EM78P458 and EM78P459 are 8-bit microprocessors designed and developed with low-power and high-speed CMOS technology. It is equipped with a 4K*13-bit Electrical One Time Programmable Read Only Memory (OTP-ROM). With its OTP-ROM feature, it is able to offer a convenient way of developing and verifying user’s programs. Moreover, user can take advantage of EMC Writer to easily program his development code.

This specification is subject to change without prior notice. 2002/03/01

2. FEATURES

• Operating voltage range: 2.3V~5.5V

• Operating temperature range: 0°C~70°C(commercial)

-40°C~85°C(industrial)

• Operating frequency range(base on 2 clocks): * Crystal mode: DC ~ 20MHz/2clks,5V; DC ~ 8MHz/2clks,3V * RC mode: DC ~ 4MHz/2clks,5V; DC ~ 4MHz/2clks,3V

• Low power consumption:

EM78P458/459

OTP ROM

* Less than 1.5 mA at 5V/4MHz * Typically 15 µA, at 3V/32KHz * Typically 1 µA, during sleep mode

• 4K × 13 bits on chip ROM

• 84 × 8 bits on chip registers (SRAM)

• 2 bi-directional I/O ports

• 8 level stacks for subroutine nesting

• 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt

• 8-bit multichannel Analog-to-Digital Converter with 8-bit resolution

• Dual Pulse Width Modulation (PWM ) with 10-bit resolution

• One pair of comparators

• Power-down (SLEEP) mode

• Six available interruptions * TCC overflow interrupt * Input-port status changed interrupt (wake up from the sleep mode) * External interrupt * ADC completion interrupt * PWM period match completion * Comparator high interrupt

• Programmable free running watchdog timer

• 8 Programmable pull-down I/O pins

• 7 programmable pull-high I/O pins

• 8 programmable open-drain I/O pins

This specification is subject to change without prior notice. 2002/03/01

• Two clocks per instruction cycle

• Package types: * 20 pin DIP 300mil : EM78P458AP * 20 pin SOP 300mil : EM78P458AM * 24 pin skinny DIP 300mil : EM78P459AK * 24 pin SOP 300mil : EM78P459AM

• Power on voltage detector available (2.0V± 0.15V)

EM78P458/459

OTP ROM

This specification is subject to change without prior notice. 2002/03/01

3. PIN ASSIGNMENT

PWM1,

P56/CIN+

P57/CO

P60/ADC1

P61/ADC2

VSS

P62/ADC3

P63/ADC4

P64/ADC5

P65/ADC6

P66/ADC7

EM78P458

10 11

P55/CIN-

P54/TCC

OSCI

OSCO

VDD

P53/VREF

P52/PWM2

P51/PWM1

P50/INT

P67/ADC8

P56/CIN+

P57/CO

P60/ADC1

P61/ADC2

ENTCC

VSS

P62/ADC3

P63/ADC4

P64/ADC5

P65/ADC6

P66/ADC7

EM78P458/459

OTP ROM

P55/CIN-

P54/TCC

OSCI

OSCO

EM78P459

12 13

RESET

VDD

P53/VREF

P52/PWM2

P51/PWM1

P50/INT

P67/ADC8

Fig. 1 Pin Assignment

Table 1 EM78P458 Pin Description

Symbol Pin No. Type Function

VDD 16 - Power supply. OSCI 18 I

* XTAL type: Crystal input terminal or external clock input pin. * RC type: RC oscillator input pin. *XTAL type: Output terminal for crystal oscillator or external clock input pin.

OSCO 17 O

*RC type: Clock output with a period of one instruction cycle time, the prescaler is determined by the CONT register. * External clock signal input.

P50 12 I

13~15

P51 ~ P57

19, 20,

1, 2

P60 ~ P67

3, 4,

6~11

* General-purpose Input only. * Default value while power-on reset.

* General-purpose I/O pin.

I/O

* Default value while power-on reset. * General-purpose I/O pin.

I/O

* Default value while power-on reset.

INT 12 I * External interrupt pin triggered by falling edge. ADC1~ADC8

3, 4,

6 ~ 11

* Analog to Digital Converter.

* Defined by AD-CMPCON (IOCA0)<2:4>.

13, 14 O * Pulse width modulation outputs.

This specification is subject to change without prior notice. 2002/03/01

PWM2 * Defined by PWMCON (IOC51)<6, 7>

* Real time clock/counter with Schmitt trigger input pin; it must be tied to

VREF 15 I

CIN-, CIN+, CO

20, 1,2

* External reference voltage for ADC * Defined by AD-CMPCON (IOCA0)<7>. * “-“ -> the input pin of Vin- of the comparator.

* “+”-> the input pin of Vin+ of the comparator.

* Pin CO is the output of the comparator. * Defined by AD-CMPCON (IOCA0) <5, 6>

EM78P458/459

OTP ROM

TCC 19 I VSS 5 - Ground.

Table 2 EM78P459 Pin Description

Symbol Pin No. Type Function

VDD 19, 18 - Power supply. OSCI 22 I

OSCO 21 O

P50 14 I

15~17

P51 ~ P57

P60 ~ P67 INT 14 I * External interrupt pin triggered by falling edge. ADC1~ADC8

PWM1, PWM2

VREF 17 I

CIN-, CIN+, CO

/RESET 20 I

TCC 23 I ENTCC 5 I 1: Enable TCC; 0: Disable TCC.

VSS 6, 7 - Ground.

23, 24

1, 2 3, 4, 8~13

3, 4, 8~13

15, 16 O

24, 1, 2 I

VDD or VSS if it is not in use.

* XTAL type: Crystal input terminal or external clock input pin. * RC type: RC oscillator input pin.

* XTAL type: Output terminal for crystal oscillator or external clock input pin. * RC type: Clock output with a period of one instruction cycle time, the prescaler is determined by the CONT register. * External clock signal input.

* General-purpose Input only. * Default value while power-on reset.

* General-purpose I/O pin.

I/O

* Default value while power-on reset. * General-purpose I/O pin.

I/O

* Default value while power-on reset. * Analog to Digital Converter.

* Defined by AD-CMPCON (IOCA0)<2:4>. * Pulse width modulation outputs.

* Defined by PWMCON (IOC51)<6, 7> * External reference voltage for ADC * Defined by AD-CMPCON (IOCA0)<7>. * ‘-’ -> the Vin- input pins of the comparators. * ‘+’ -> the Vin+ input pins of the comparators. * Pin CO is the output of the comparator. * Defined by AD-CMPCON (IOCA0) <5, 6> * If it remains at logic low, the device will be reset. * Wake up from sleep mode when pins status changes. * Voltage on /RESET/Vpp must not be over Vdd during normal mode. * Pull-high is on if /RESET is asserted. * Real time clock/counter with Schmitt trigger input pin; it must be tied to VDD or VSS if it is not in use.

This specification is subject to change without prior notice. 2002/03/01

4. FUNCTION DESCRIPTION

EM78P458/459

OTP ROM

ENTCC

Oscillator/

Timming

Control

Sleep

Wake Up

Control

WDT

Time-out

Prescaler

R1(TCC)

Comparators 8 ADC2 PWMs

P 5 0

Fig. 2 The Functional Block Diagram of EM78P458/459

4.1 Operational Registers

IOC5

RAM

/INT

Interrupt Control

WDT Timer

DATA & CONTROL BUS

ROM

Instruction

Decoder

P C

STACK 0 STACK 1 STACK 2 STACK 3 STACK 4 STACK 5 STACK 6 STACK 7

ALU

ACCR3

IOC6

1. R0 (Indirect Addressing Register)

R0 is not a physically implemented register. Its major function is to perform as an indirect addressing pointer. Any instruction using R0 as a pointer, actually accesses data pointed by the RAM Select Register (R4).

2. R1 (Time Clock /Counter)

• Increased by an external signal edge through the TCC pin, or by the instruction cycle clock.

• The signals to increase the counter are decided by Bit 4 and Bit 5 of the CONT register.

• Writable and readable as any other registers.

3. R2 (Program Counter) & Stack

• R2 and hardware stacks are 12-bit wide. The structure is depicted in Fig. 4.

• Generates 4K×13 bits on-chip ROM addresses to the relative programming instruction codes. One program page is 1024 words long.

This specification is subject to change without prior notice. 2002/03/01

EM78P458/459

OTP ROM

• The contents of R2 are set to all "0"s upon a RESET condition.

• "JMP" instruction allows the direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC to jump to any location within a page.

• "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere within a page.

• "RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the top of stack.

• "ADD R2, A" allows a relative address to be added to the current PC, and the ninth and tenth bits of the PC are cleared.

• "MOV R2, A" allows to load an address from the "A" register to the lower 8 bits of the PC, and the ninth and tenth bits of the PC are cleared.

• Any instruction that is written to R2 (e.g. "ADD R2, A", "MOV R2, A", "BC R2, 6",⋅⋅⋅⋅⋅) will cause the ninth bit and the tenth bit (A8~A9) of the PC to be cleared. Thus, the computed jump is limited to the first 256 locations of a page.

• In the case of EM78P458/459, the most two significant bits (A11 and A10) will be loaded with the content of PS1 and PS0 in the status register (R3) upon the execution of a "JMP", "CALL", or any other instructions set which write to R2.

• All instructions are single instruction cycle (fclk/2 or fclk/4) except for the instructions which write to R2, need one more instruction cycle.

A9 ~ A8A11~A10 A7 ~ A0

000

3 FF

400

7FF

800

Page 0

Page 1

Page 2

CALL K

RET

RETI

RETL K

Stack 0

Stack 1

Stack 2

Stack 3

Stack 4

Stack 5

Stack 6

Stack 7

BFF C00

FFF

Page 3

Fig. 3 Program Counter Organization

This specification is subject to change without prior notice. 2002/03/01

EM78P458/459

OTP ROM

4. R3 (Status Register)

7 6 5 4 3 2 1 0

CMPOUT PS1 PS0 T P Z DC C

• Bit 7 (CMPOUT) the result of the comparator output.

• Bit 6 (PS1) ~ 5 (PS0) Page select bits. PS0~PS1 are used to select a program memory page. When executing a "JMP", "CALL", or other instructions which cause the program counter to be changed (e.g. MOV R2, A), PS0~PS1 are loaded into the 11th and 12th bits of the program counter where it selects one of the available program memory pages. Note that RET (RETL, RETI) instruction does not change the PS0~PS1 bits. That is, the return will always be to the page from the place where the subroutine was called, regardless of the current setting of PS0~PS1 bits.

PS1 PS0 Program memory page [Address]

0 0 Page 0 [000-3FF] 0 1 Page 1 [400-7FF] 1 0 Page 2 [800-BFF] 1 1 Page 3 [C00-FFF]

• Bit 4 (T) Time-out bit. Set to 1 by the "SLEP" and "WDTC" commands, or during Power on and reset to 0 by WDT time-out.

• Bit 3 (P) Power-down bit. Set to 1 during power-on or by a "WDTC" command and reset to 0 by a "SLEP" command.

• Bit 2 (Z) Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero.

• Bit 1 (DC) Auxiliary carry flag

• Bit 0 (C) Carry flag

5. R4 (RAM Select Register)

• Bits 0~5 are used to select registers (address: 00~3F) in the indirect address mode.

• Bit 6 is used to select bank 0 or bank 1.

• Bit 7 is a general-purpose read/write bit.

• See the configuration of the data memory in Fig. 4.

6. R5 ~ R6 (Port 5 ~ Port 6)

• R5 and R6 are I/O registers.

7. R7 ~ R8

• All of these are 8-bit general-purpose registers.

This specification is subject to change without prior notice. 2002/03/01

EM78P458/459

OTP ROM

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F

10 11

R0 R1 (TCC) R2 (PC) R3 (Status) R4 (RSR) R5 (Port 5) R6 (Port 6) R7 R8

R9 (ADCON) RA (ADDATA) RB (TMR1L) RC (TMR1H) RD (TMR2L) RE (TMR2H) RF

16x8 Common Register

STACK 0 STACK 1 STACK 2 STACK 3 STACK 4 STACK 5 STACK 6 STACK 7

R9<5> (IOCS)

0 IOC50 IOC60

IOC90 (GCON)

IOCA0 (AD-CMPCON)

IOCB0 IOCC0

IOCD0 IOCE0 IOCF0

IOC51 (PWMCON) IOC61 (DT1L) IOC71 (DT1H) IOC81 (PRD1) IOC91 (DT2L)

IOCA1 (DT2H)

IOCB1 (PRD2)

IOCC1 (DL1L) IOCD1 (DL1H) IOCE1 (DL2L) IOCF1 (DL2H)

1E 1F

PSR7, PSR6

20 21

32x8

Bank

(Bank 0)

32x8

Bank

(Bank 1)

Fig. 4 Data Memory Configuration

This specification is subject to change without prior notice. 2002/03/01

EM78P458/459

8. R9 (ADCON: Analog to Digital Control)

7 6 5 4 3 2 1 0

- - IOCS ADRUN ADPD ADIS2 ADIS1 ADIS0

• Bit 7:Bit 6 Unemployed, read as ‘0’;

• Bit 5(IOCS): Select the Segment of IO control register.

1 = Segment 1 ( IOC51~IOCF1 ) selected; 0 = Segment 0 ( IOC50~IOCF0 ) selected;

• Bit 4 (ADRUN): ADC starts to RUN. 1 = an A/D conversion is started. This bit can be set by software; 0 = reset on completion of the conversion. This bit can not be reset though software;

• Bit 3 (ADPD): ADC Power-down mode. 1 = ADC is operating;

OTP ROM

0 = switch off the resistor reference to save power even while the CPU is operating.

• Bit2:Bit0 (ADIS2:ADIS0): Analog Input Select. 000 = AN0; 001 = AN1; 010 = AN2; 011 = AN3; 100 = AN4; 101 = AN5; 110 = AN6; 111 = AN7; They can only be changed when the ADIF bit and the ADRUN bit are both LOW.

9. RA (ADDATA: the converted value of ADC)

When the A/D conversion is complete, the result is loaded into the ADDATA. The START//END bit is cleared, and the ADIF is set.

10. RB

An 8-bit general-purpose register.

11. RC

A 2-bit, Bit 0and Bit 1 register.

12. RD

This specification is subject to change without prior notice. 2002/03/01

EM78P458/459

OTP ROM

An 8-bit general-purpose register.

13. RE

A 2-bit, Bit 0 and Bit 1 register.

14. RF (Interrupt Status Register)

7 6 5 4 3 2 1 0

- CMPIF PWM2IF PWM1IF ADIF EXIF ICIF TCIF

“1” means interrupt request, and “0” means no interrupt occurs.

• Bit 0 (TCIF) TCC overflow interrupt flag. Set when TCC overflows, reset by software.

• Bit 1 (ICIF) Port 6 input status change interrupt flag. Set when Port 6 input changes, reset by

software.

• Bit 2 (EXIF) External interrupt flag. Set by falling edge on /INT pin, reset by software.

• Bit 3 (ADIF) Interrupt flag for analog to digital conversion. Set when AD conversion is completed,

reset by software.

• Bit 4 (PWM1IF) PWM1 (Pulse Width Modulation) interrupt flag. Set when a selected period is

reached, reset by software.

• Bit 5 (PWM2IF) PWM2 (Pulse Width Modulation) interrupt flag. Set when a selected period is

reached, reset by software.

• Bit 6 (CMPIF) High-compared interrupt flag. Set when a change occurs in the output of Comparator,

reset by software.

• Bit 7 Unemployed, read as ‘0’;

• RF can be cleared by instruction but cannot be set.

• IOCF0 is the interrupt mask register.

• Note that to read RF will result to "logic AND" of RF and IOCF0.

15. R10 ~ R3F

• All of these are 8-bit general-purpose registers.

4.2 Special Purpose Registers

1. A (Accumulator)

• Internal data transfer, or instruction operand holding

• It can not be addressed.

This specification is subject to change without prior notice. 2002/03/01

EM78P458/459

2. CONT (Control Register)

7 6 5 4 3 2 1 0

INTE INT TS TE PAB PSR2 PSR1 PSR0

• Bit 0 (PSR0) ~ Bit 2 (PSR2) TCC/WDT prescaler bits.

PSR2 PSR1 PSR0 TCC Rate WDT Rate

0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1:16 1:8 1 0 0 1:32 1:16 1 0 1 1:64 1:32 1 1 0 1:128 1:64 1 1 1 1:256 1:128

• Bit 3 (PAB) Prescaler assignment bit.

OTP ROM

0: TCC; 1: WDT.

• Bit 4 (TE) TCC signal edge 0: increment if the transition from low to high takes place on the TCC pin; 1: increment if the transition from high to low takes place on the TCC pin.

• Bit 5 (TS) TCC signal source 0: internal instruction cycle clock. If P54 is used as I/O pin, TS must be 0. 1: transition on the TCC pin

• Bit 6 (INT) Interrupt enable flag 0: masked by DISI or hardware interrupt 1: enabled by the ENI/RETI instructions

• Bit 7 (INTE) INT signal edge 0: interrupt occurs at the rising edge on the INT pin 1: interrupt occurs at the falling edge on the INT pin

• CONT register is both readable and writable.

3. IOC50 ~ IOC60 (I/O Port Control Register)

• "1" puts the relative I/O pin into high impedance, while "0" defines the relative I/O pin as output.

• IOC50 and IOC60 registers are both readable and writable.

This specification is subject to change without prior notice. 2002/03/01

EM78P458/459

OTP ROM

4. IOC90 (GCON: I/O Configuration & Control of ADC )

7 6 5 4 3 2 1 0

OP2E OP1E G22 G21 G20 G12 G11 G10

• Bit 7 ( OP2E ) Enable the gain amplifier which input is connected to P64 and output is connected to

the 8-1 analog switch.

0 = OP2 is off ( default value ), and bypasses the input signal to the ADC; 1 = OP2 is on.

• Bit 6 ( OP1E ) Enable the gain amplifier whose input is connected to P60 and output is connected to

the 8-1 analog switch.

0 = OP1 is off (default value), and bypasses the input signal to the ADC; 1 = OP1 is on.

• Bit 5:Bit 3 (G22 and G20): Select the gain of OP2. 000 = IS x 1 (default value); 001 = IS x 2; 010 = IS x 4; 011 = IS x 8; 100 = IS x 16; 101 = IS x 32; Legend: IS = the input signal

• Bit 2:Bit 0 (G12 and G10 ): Select the gain of OP1. 000 = IS x 1 (default value); 001 = IS x 2; 010 = IS x 4; 011 = IS x 8; 100 = IS x 16; 101 = IS x 32; Legend: S = the input signal

5. IOCA0 ( AD-CMPCON ):

7 6 5 4 3 2 1 0

VREFS CE COE IMS2 IMS1 IMS0 CKR1 CKR0

• Bit 7: The input source of the Vref of the ADC. 0 = The Vref of the ADC is connected to Vdd (default value), and the P53/VREF pin carries out the function of P53;

This specification is subject to change without prior notice. 2002/03/01

EM78P458/459

OTP ROM

1 = The Vref of the ADC is connected to P53/VREF.

• Bit 6 (CE): Comparator enable bit 0 = Comparator is off (default value); 1 = Comparator is on.

• Bit 5 ( COE ): Set P57 as the output of the comparator 0 = the comparator acts as an OP if CE=1. 1 = act as a comparator if CE=1.

• Bit4:Bit2 (IMS2:IMS0): Input Mode Select. ADC configuration definition bit. The following Table describes how to define the characteristic of each pin of R6.

Table 3 Description of AD Configuration Control Bits

IMS2:IMS0 P60 P61 P62 P63 P64 P65 P66 P67

000 A D D D D D D D 001 A A D D D D D D

010 A A A D D D D D 011 A A A A D D D D 100 A A A A A D D D 101 A A A A A A D D 110 A A A A A A A D 111 A A A A A A A A

• Bit 1: Bit 0 (CKR1: CKR0): The prescaler of oscillator clock rate of ADC 00 = 1: 4 (default value); 01 = 1: 16; 10 = 1: 64; 11 = 1: WDT ring oscillator frequency.

6. IOCB0 (Pull-down Control Register)

7 6 5 4 3 2 1 0

/PD7 /PD6 /PD5 /PD4 /PD3 /PD2 /PD1 /PD0

• Bit 0 (/PD0) Control bit is used to enable the pull-down of the P60 pin. 0: Enable internal pull-down; 1: Disable internal pull-down.

• Bit 1 (/PD1) Control bit is used to enable the pull-down of the P61 pin.

• Bit 2 (/PD2) Control bit is used to enable the pull-down of the P62 pin.

• Bit 3 (/PD3) Control bit is used to enable the pull-down of the P63 pin.

• Bit 4 (/PD4) Control bit is used to enable the pull-down of the P64 pin.

This specification is subject to change without prior notice. 2002/03/01

EM78P458/459

• Bit 5 (/PD5) Control bit is used to enable the pull-down of the P65 pin.

• Bit 6 (/PD6) Control bit is used to enable the pull-down of the P66 pin.

• Bit 7 (/PD7) Control bit is used to enable the pull-down of the P67 pin.

• IOCB0 register is both readable and writable.

7. IOCC0 (Open-Drain Control Register)

7 6 5 4 3 2 1 0

/OD7 /OD6 /OD5 /OD4 /OD3 /OD2 /OD1 /OD0

• Bit 0 (OD0) Control bit used to enable the open-drain of the P64 pin. 0: Enable open-drain output 1: Disable open-drain output

• Bit 1 (OD1) Control bit is used to enable the open-drain of the P65 pin.

OTP ROM

• Bit 2 (OD2) Control bit is used to enable the open-drain of the P66 pin.

• Bit 3 (OD3) Control bit is used to enable the open-drain of the P67 pin.

• Bit 4 (OD4) Control bit is used to enable the open-drain of the P51 pin.

• Bit 5 (OD5) Control bit is used to enable the open-drain of the P52 pin.

• Bit 6 (OD6) Control bit is used to enable the open-drain of the P54 pin.

• Bit 7 (OD7) Control bit is used to enable the open-drain of the P57 pin.

• IOCC0 register is both readable and writable.

8. IOCD0 (Pull-high Control Register)

7 6 5 4 3 2 1 0

/PH7 /PH6 /PH5 - /PH3 /PH2 /PH1 /PH0

• Bit 0 (/PH0) Control bit is used to enable the pull-high of the P60 pin. 0: Enable internal pull-high; 1: Disable internal pull-high.

• Bit 1 (/PH1) Control bit is used to enable the pull-high of the P61 pin.

• Bit 2 (/PH2) Control bit is used to enable the pull-high of the P62 pin.

• Bit 3 (/PH3) Control bit is used to enable the pull-high of the P63 pin.

• Bit 4 Not used.

• Bit 5 (/PH5) Control bit is used to enable the pull-high of the P53 pin.

• Bit 6 (/PH6) Control bit is used to enable the pull-high of the P55 pin.

• Bit 7 (/PH7) Control bit is used to enable the pull-high of the P56 pin.

• IOCD0 register is both readable and writable.

This specification is subject to change without prior notice. 2002/03/01

EM78P458/459

OTP ROM

9. IOCE0 (WDT Control Register)

7 6 5 4 3 2 1 0

WDTE EIS - - - - - -

• Bit 7 (WDTE) Control bit is used to enable Watchdog Timer. 0: Disable WDT; 1: Enable WDT. WDTE is both readable and writable

• Bit 6 (EIS) Control bit is used to define the function of the P50 (/INT) pin. 0: P50, input pin only; 1: /INT, external interrupt pin. In this case, the I/O control bit of P50 (bit 0 of IOC50) must be set to "1". When EIS is "0", the path of /INT is masked. When EIS is "1", the status of /INT pin can also be read by way of reading Port 5 (R5). Refer to Fig. 7. EIS is both readable and writable.

• Bits 0~5 Not used.

10. IOCF0 (Interrupt Mask Register)

7 6 5 4 3 2 1 0

- CMPIE PWM2IE PWM1IE ADIE EXIE ICIE TCIE

• Bit 0 (TCIE) TCIF interrupt enable bit. 0: disable TCIF interrupt 1: enable TCIF interrupt

• Bit 1 (ICIE) ICIF interrupt enable bit. 0: disable ICIF interrupt 1: enable ICIF interrupt

• Bit 2 (EXIE) EXIF interrupt enable bit. 0: disable EXIF interrupt 1: enable EXIF interrupt

• Bit 3 (ADIE) ADIF interrupt enable bit. 0: disable ADIF interrupt 1: enable ADIF interrupt

• Bit 4 (PWM1IE) PWM1IF interrupt enable bit. 0: disable PWM1 interrupt 1: enable PWM1 interrupt

This specification is subject to change without prior notice. 2002/03/01

EM78P458/459

OTP ROM

• Bit 5 (PWM2IE) PWM2IF interrupt enable bit. 0: disable PWM2 interrupt 1: enable PWM2 interrupt

• Bit 6 (CMPIE) CMPIF interrupt enable bit. 0: disable CMPIF interrupt 1: enable CMPIF interrupt

• Bit 7: Unimplemented, read as ‘0’. Individual interrupt is enabled by setting its associated control bit in the IOCF0 to "1". Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to Fig.

11. IOCF0 register is both readable and writable.

11. IOC51 ( PWMCON ):

7 6 5 4 3 2 1 0

PWM2E PWM1E T2EN T1EN T2P1 T2P0 T1P1 T1P0

• Bit 7 (PWM2E): PWM2 enable bit 0 = PWM2 is off (default value), and its related pin carries out the P52 function. 1 = PWM2 is on, and its related pin will be set to output automatically.

• Bit 6 (PWM1E): PWM1 enable bit 0 = PWM1 is off (default value), and its related pin carries out the P51 function; 1 = PWM1 is on, and its related pin will be set to output automatically.

• Bit 5 (T2EN): TMR2 enable bit 0 = TMR2 is off (default value). 1 = TMR2 is on.

• Bit 4 (T1EN): TMR1 enable bit 0 = TMR1 is off (default value). 1 = TMR1 is on.

• Bit 3: Bit 2 ( T2P1:T2P0 ): TMR2 clock prescale option bits.

T2P1 T2P0 Prescale

0 0 1:2(Default) 0 1 1:8

1 0 1:32 1 1 1:64

This specification is subject to change without prior notice. 2002/03/01

EM78P458/459

OTP ROM

• Bit 1 : Bit 0 ( T1P1:T1P0 ): TMR1 clock prescale option bits.

T1P1 T1P0 Prescale

0 0 1:2(Default) 0 1 1:8 1 0 1:32 1 1 1:64

12. IOC61 ( DT1L: the Least Significant Byte ( Bit 7 ~ Bit 0) of Duty Cycle of PWM1 )

A specified value keeps the output of PWM1 to stay at high until the value matches with TMR1.

13. IOC71 ( DT1H: the Most Significant Byte ( Bit 1 ~ Bit 0 ) of Duty Cycle of PWM1 )

7 6 5 4 3 2 1 0

CALI1 SIGN1 VOF1[2] VOF1[1] VOF1[0] - PWM1[9] PWM1[8]

• Bit 7 (CALI1): Calibration enable bit 0 = Calibration disable; 1 = Calibration enable.

• Bit 6 (SIGN1): Polarity bit of offset voltage 0 = Negative voltage; 1 = Positive voltage.

• Bit 5:Bit 3 (VOF1[2]:VOF1[0]): Offset voltage bits.

• Bit 1:Bit 0 (PWM1[9]:PWM1[8]): The Most Significant Byte of PWM1 Duty Cycle A specified value keeps the PWM1 output to stay at high until the value matches with TMR1.

14. IOC81 ( PRD1: Period of PWM1 ):

The content of IOC81 is a period (time base) of PWM1. The frequency of PWM1 is the reverse of the period.

15. IOC91 ( DT2L: the Least Significant Byte ( Bit 7 ~ Bit 0 ) of Duty Cycle of PWM2 )

A specified value keeps the of PWM1 output to stay at high until the value matches with TMR2.

16. IOCA1 ( DT2H: the Most Significant Byte ( Bit 1 ~ Bit 0 ) of Duty Cycle of PWM2 )

7 6 5 4 3 2 1 0

CALI2 SIGN2 VOF2[2] VOF2[1] VOF2[0] - PWM2[9] PWM2[8]

• Bit 7 (CALI2): Calibration enable bit

This specification is subject to change without prior notice. 2002/03/01

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