ELAN EM78P156ELP, EM78P156ELM, EM78P156ELKM, EM78P156ELAS Datasheet

EM78P156EL

OTP ROM

1. GENERAL DESCRIPTION

EM78P156EL is an 8-bit microprocessor designed and developed with low-power and high-speed CMOS technology. It is equipped with 1K*13-bits Electrical One Time Programmable Read Only Memory (OTP-ROM). It provides a PROTECTION bit to prevent user’s code in the OTP memory from being intruded. 6 OPTION bits are also available to meet user’s requirements.

With its OTP-ROM feature, the EM78P156EL is able to offer a convenient way of developing and verifying user’s programs. Moreover, user can take advantage of EMC Writer to easily program his development code.

This specification is subject to change without prior notice. 2002/04/19 1

2. FEATURES

• Operating voltage range : 2.3V~5.5V

• Operating temperature range: 0°C~70°C

• Operating frequency rang (base on 2 clocks ): * Crystal mode: DC~20MHz at 5V, DC~8MHz at 3V, DC~4MHz at 2.3V. * ERC mode: DC~4MHz at 5V, DC~4MHz at 3V, DC~4MHz at 2.3V.

• Low power consumption: * Less then 1.6 mA at 5V/4MHz

EM78P156EL

OTP ROM

* Typically 15 µA at 3V/32KHz * Typically 1 µA during sleep mode

• 1K × 13 bits on chip ROM

• One security register to prevent intrusion of OTP memory codes

• One configuration register to accommodate user’s requirements

• 48× 8 bits on chip registers (SRAM, general purpose register)

• 2 bi-directional I/O ports

• 5 level stacks for subroutine nesting

• 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt

• Two clocks per instruction cycle

• Power down (SLEEP) mode

• Three available interruptions * TCC overflow interrupt * Input-port status changed interrupt (wake up from sleep mode) * External interrupt

• Programmable free running watchdog timer

• 8 programmable pull-high pins

• 7 programmable pull-down pins

• 8 programmable open-drain pins

• 2 programmable R-option pins

• Package types: * 18 pin DIP 300mil : EM78P156ELP * 18 pin SOP(SOIC) 300mil : EM78P156ELM

This specification is subject to change without prior notice. 2002/04/19 2

EM78P156EL

* 20 pin SSOP 209mil : EM78P156ELAS * 20 pin SSOP 209mil : EM78P156ELKM

• 99.9% single instruction cycle commands

• The transient point of system frequency between HXT and LXT is around 400KHz

OTP ROM

This specification is subject to change without prior notice. 2002/04/19 3

3. PIN ASSIGNMENTS

VSS

unter (with Schmitt trigger input pin), must be tied to

* Input pin with Schmitt trigger. If this pin remains at logic low, the controller

EM78P156EL

OTP ROM

/RESET

P60//INT

EM78P156ELP

EM78P156ELM

P52 P53

TCC

P61 P62 P63

1 2 3 4 5 6 7 8 9

DIP SOP

SOIC

18 17 16 15 14 13 12 11 10

P51 P50 OSCI OSCO VDD P67 P66 P65 P64

/RESET

EM78P156ELAS

NC P52 P53

TCC

P61 P62 P63

1 2 3 4 5 6 7 8 9 10

SSOP

Fig. 1 Pin Assignment

Table 1 EM78P156ELP and EM78P156ELM Pin Description

Symbol Pin No. Type Function

VDD 14 - * Power supply. OSCI 16 I

* XTAL type: Crystal input terminal or external clock input pin. * ERC type: RC oscillator input pin. * XTAL type: Output terminal for crystal oscillator or external clock input pin.

OSCO 15 I/O

* RC type: Instruction clock output. * External clock signal input.

TCC 3 I /RESET 4 I

P50~P53

17, 18,

1, 2

I/O

P60~P67 6~13 I/O

* The real time clock/co VDD or VSS if not in use.

will also remain in reset condition. * P50~P53 are bi-directional I/O pins. * P50 and P51 can also be defined as the R-option pins. * P50~P52 can be pulled-down by software. * P60~P67 are bi-directional I/O pins. * These can be pulled-high or can be open-drain by software programming.

* P60~P63 can also be pulled-down by software. /INT 6 I * External interrupt pin triggered by falling edge. VSS 5 - * Ground.

20 19 18 17 16 15 14 13 12 11

EM78P156ELKM

NC P51 P50 OSCI OSCO VDD P67 P60//INT P66 P65 P64

P52 P53

TCC

/RESET

P61 P62 P63

1 2 3 4 5 6 7 8 9 10

SSOP

20 19 18 17 16 15 14 13 12 11

P51 P50 OSCI OSCO VDD VDD P67 P60//INT P66 P65 P64

This specification is subject to change without prior notice. 2002/04/19 4

Table 2 EM78P156ELAS Pin Description

* The real time clock/counter (with Schmitt trigger input pin), must be tied to * Input pin with Schmitt trigger. If this pin remains at logic low, the controller

drain by software programming.

* The real time clock/counter (with Schmitt trigger input pin), must be tied to

drain by software programming.

Symbol Pin No. Type Function

VDD 15 - * Power supply. OSCI 17 I

OSCO 16 I/O

* XTAL type: Crystal input terminal or external clock input pin.

* ERC type: RC oscillator input pin.

* XTAL type: Output terminal for crystal oscillator or external clock input pin.

* RC type: Instruction clock output.

* External clock signal input.

EM78P156EL

OTP ROM

TCC 4 I /RESET 5 I

P50~P53

P60~P67 7~14 I/O

/INT 7 I * External interrupt pin triggered by falling edge. VSS 6 - * Ground.

Table 3 EM78P156ELKM Pin Description

Symbol Pin No. Type Function

VDD 15,16 - * Power supply. OSCI 18 I

OSCO 17 I/O

TCC 3 I /RESET 4 I

P50~P53

P60~P67 7~14 I/O

/INT 7 I * External interrupt pin triggered by falling edge. VSS 5, 6 - * Ground.

18, 19,

2, 3

19, 20,

1, 2

I/O

VDD or VSS if not in use.

will also remain in reset condition.

* P50~P53 are bi-directional I/O pins.

* P50 and P51 can also be defined as the R-option pins.

* P50~P52 can be pulled-down by software.

* P60~P67 are bi-directional I/O pins.

* These can be pulled-high or can be open-

* P60~P63 can also be pulled-down by software.

* XTAL type: Crystal input terminal or external clock input pin.

* ERC type: RC oscillator input pin.

* XTAL type: Output terminal for crystal oscillator or external clock input pin.

* RC type: Instruction clock output.

* External clock signal input.

VDD or VSS if not in use.

* Input pin with Schmitt trigger. If this pin remains at logic low, the controll

will also remain in reset condition.

* P50~P53 are bi-directional I/O pins.

* P50 and P51 can also be defined as the R-option pins.

* P50~P52 can be pulled-down by software.

* P60~P67 are bi-directional I/O pins.

* These can be pulled-high or can be open-

* P60~P63 can also be pulled-down by software.

This specification is subject to change without prior notice. 2002/04/19 5

4. FUNCTION DESCRIPTION

& Wake

OSCI OSCO /RESET

WDT Timer

Oscillator/Timing

Control

Internal C External R

oscillator

WDT

Time-out

Prescale

R1(TCC)

IOCA

Interrupt Control

EM78P156EL

OTP ROM

/INT TCC

STACK 1 STACK 2

STACK 3 STACK 4 STACK 5

ALU

ROM

Instruction

P C

Sleep

Control

P 5 0

IOC5

RAM

P 5 3

DATA & CONTROL BUS

Instruction

Decoder

IOC6

Fig. 2 Function Block Diagram

4.1 Operational Registers

1. R0 (Indirect Addressing Register)

R0 is not a physically implemented register. Its major function is to perform as an indirect addressing pointer. Any instruction using R0 as a pointer actually accesses data pointed by the RAM Select

2. R1 (Time Clock /Counter)

• Increased by an external signal edge, which is defined by TE bit (CONT-4) through the TCC pin, or by the instruction cycle clock.

• Writable and readable as any other registers.

This specification is subject to change without prior notice. 2002/04/19 6

EM78P156EL

OTP ROM

• Defined by resetting PAB(CONT-3).

• The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset.

• The contents of the prescaler counter will be cleared only when TCC register is written with a value.

3. R2 (Program Counter) & Stack

• Depending on the device type, R2 and hardware stack are 10-bit wide. The structure is depicted in Fig.3.

• Generating 1024×13 bits on-chip OTP ROM addresses to the relative programming instruction codes. One program page is 1024 words long.

• R2 is set as all "0"s when under RESET condition.

• "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC to go to any location within a page.

• "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere within a page.

• "RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the top-level stack.

• "ADD R2, A" allows the contents of ‘A’ to be added to the current PC, and the ninth and tenth bits of the PC are cleared.

• "MOV R2, A" allows to load an address from the "A" register to the lower 8 bits of the PC, and the ninth and tenth bits of the PC are cleared.

• Any instruction that writes to R2 (e.g., "ADD R2,A", "MOV R2,A", "BC R2,6",⋅⋅⋅⋅⋅) will cause the ninth and tenth bits (A8~A9) of the PC to be cleared. Thus, the computed jump is limited to the first 256

locations of a page.

• All instruction are single instruction cycle (fclk/2 or fclk/4) except for the instruction that would change the contents of R2. Such instruction will need one more instruction cycle.

A9 A8 A7 ~ A0

000

CALL RET

RETL RETL K

Stack 1 Stack 2 Stack 3

Stack 4 Stack 5

PAGE 0

3FF

Fig. 3 Program Counter Organization

This specification is subject to change without prior notice. 2002/04/19 7

00 R0

EM78P156EL

OTP ROM

01 02 03 04

05 06 07 08

09 0A 0B 0C 0D 0E 0F

R1(TCC) R2(PC) R3(Status) R4(RSR)

R5(Port5) R6(Port6)

RF R10

Stack (5 level)

IOC5 IOC6

IOCA IOCB IOCC IOCD IOCE IOCF

: : :

48x8 Common Register

R3F

Fig. 4 Data Memory Configuration

4. R3 (Status Register)

7 6 5 4 3 2 1 0

GP2 GP1 GP0 T P Z DC C

• Bit 0 (C) Carry flag

• Bit 1 (DC) Auxiliary carry flag

• Bit 2 (Z) Zero flag.

This specification is subject to change without prior notice. 2002/04/19 8

EM78P156EL

OTP ROM

Set to "1" if the result of an arithmetic or logic operation is zero.

• Bit 3 (P) Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command.

• Bit 4 (T) Time-out bit. Set to 1 with the "SLEP" and "WDTC" commands, or during power up and reset to 0 by WDT time-out.

• Bit5 ~7 (GP0 ~ 2) General-purpose read/write bits.

5. R4 (RAM Select Register)

• Bits 0~5 are used to select registers (address: 00~06, 0F~3F) in the indirect addressing mode.

• Bits 6~7 are not used (read only).

• The Bits 6~7 set to “1” at all time.

• Z flag of R3 will set to “1” when R4 content is equal to “3F.” When R4=R4+1, R4 content will select

as R0.

• See the configuration of the data memory in Fig. 4.

6. R5 ~ R6 (Port 5 ~ Port 6)

• R5 and R6 are I/O registers.

• Only the lower 4 bits of R5 are available.

7. RF (Interrupt Status Register)

7 6 5 4 3 2 1 0

- - - - - EXIF ICIF TCIF

“1” means interrupt request, and “0” means no interrupt occurs.

• Bit 0 (TCIF) TCC overflow interrupt flag. Set when TCC overflows, reset by software.

• Bit 1 (ICIF) Port 6 input status change interrupt flag. Set when Port 6 input changes, reset by

software.

• Bit 2 (EXIF) External interrupt flag. Set by falling edge on /INT pin, reset by software.

• Bits 3 ~ 7 Not used.

• RF can be cleared by instruction but cannot be set.

• IOCF is the interrupt mask register.

• Note that the result of reading RF is the "logic AND" of RF and IOCF.

8. R10 ~ R3F

• All of these are 8-bit general-purpose registers.

This specification is subject to change without prior notice. 2002/04/19 9

4.2 Special Purpose Registers

1. A (Accumulator)

• Internal data transfer, or instruction operand holding

• It cannot be addressed.

2. CONT (Control Register)

7 6 5 4 3 2 1 0

- /INT TS TE PAB PSR2 PSR1 PSR0

• Bit 0 (PSR0) ~ Bit 2 (PSR2) TCC/WDT prescaler bits.

PSR2 PSR1 PSR0 TCC Rate WDT Rate

0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1:16 1:8 1 0 0 1:32 1:16 1 0 1 1:64 1:32 1 1 0 1:128 1:64 1 1 1 1:256 1:128

EM78P156EL

OTP ROM

• Bit 3 (PAB) Prescaler assignment bit. 0: TCC 1: WDT

• Bit 4 (TE) TCC signal edge 0: increment if the transition from low to high takes place on TCC pin 1: increment if the transition from high to low takes place on TCC pin

• Bit 5 (TS) TCC signal source 0: internal instruction cycle clock 1: transition on TCC pin

• Bit 6 (/INT) Interrupt enable flag 0: masked by DISI or hardware interrupt 1: enabled by ENI/RETI instructions

• Bit 7 Not used.

• CONT register is both readable and writable.

3. IOC5 ~ IOC6 (I/O Port Control Register)

• "1" put the relative I/O pin into high impedance, while "0" defines the relative I/O pin as output.

• Only the lower 4 bits of IOC5 can be defined.

• IOC5 and IOC6 registers are both readable and writable.

This specification is subject to change without prior notice. 2002/04/19 10

EM78P156EL

4. IOCA (Prescaler Counter Register)

• IOCA register is readable.

• The value of IOCA is equal to the contents of Prescaler counter.

• Down counter.

5. IOCB (Pull-down Control Register)

7 6 5 4 3 2 1 0

/PD7 /PD6 /PD5 /PD4 - /PD2 /PD1 /PD0

• Bit 0 (/PD0) Control bit is used to enable the pull-down of P50 pin. 0: Enable internal pull-down 1: Disable internal pull-down

• Bit 1 (/PD1) Control bit is used to enable the pull-down of P51 pin.

OTP ROM

• Bit 2 (/PD2) Control bit is used to enable the pull-down of P52 pin.

• Bit 3 Not used.

• Bit 4 (/PD4) Control bit is used to enable the pull-down of P60 pin.

• Bit 5 (/PD5) Control bit is used to enable the pull-down of P61 pin.

• Bit 6 (/PD6) Control bit is used to enable the pull-down of P62 pin.

• Bit 7 (/PD7) Control bit is used to enable the pull-down of P63 pin.

• IOCB Register is both readable and writable.

6. IOCC (Open-drain Control Register)

7 6 5 4 3 2 1 0

OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0

• Bit 0 (OD0) Control bit is used to enable the open-drain of P60 pin. 0: Disable open-drain output 1: Enable open-drain output

• Bit 1 (OD1) Control bit is used to enable the open-drain of P61 pin.

• Bit 2 (OD2) Control bit is used to enable the open-drain of P62 pin.

• Bit 3 (OD3) Control bit is used to enable the open-drain of P63 pin.

• Bit 4 (OD4) Control bit is used to enable the open-drain of P64 pin.

• Bit 5 (OD5) Control bit is used to enable the open-drain of P65 pin.

• Bit 6 (OD6) Control bit is used to enable the open-drain of P66 pin.

• Bit 7 (OD7) Control bit is used to enable the open-drain of P67 pin.

• IOCC Register is both readable and writable.

This specification is subject to change without prior notice. 2002/04/19 11

EM78P156EL

7. IOCD (Pull-high Control Register)

7 6 5 4 3 2 1 0

/PH7 /PH6 /PH5 /PH4 /PH3 /PH2 /PH1 /PH0

• Bit 0 (/PH0) Control bit is used to enable the pull-high of P60 pin. 0: Enable internal pull-high 1: Disable internal pull-high

• Bit 1 (/PH1) Control bit is used to enable the pull-high of P61 pin.

• Bit 2 (/PH2) Control bit is used to enable the pull-high of P62 pin.

• Bit 3 (/PH3) Control bit is used to enable the pull-high of P63 pin.

• Bit 4 (/PH4) Control bit is used to enable the pull-high of P64 pin.

• Bit 5 (/PH5) Control bit is used to enable the pull-high of P65 pin.

OTP ROM

• Bit 6 (/PH6) Control bit is used to enable the pull-high of P66 pin.

• Bit 7 (/PH7) Control bit is used to enable the pull-high of P67 pin.

• IOCD Register is both readable and writable.

8. IOCE (WDT Control Register)

7 6 5 4 3 2 1 0

WDTE EIS - ROC - - - -

• Bit 7 (WDTE) Control bit used to enable Watchdog timer. 0: Disable WDT. 1: Enable WDT. WDTE is both readable and writable.

• Bit 6 (EIS) Control bit is used to define the function of P60 (/INT) pin. 0: P60, bi-directional I/O pin. 1: /INT, external interrupt pin. In this case, the I/O control bit of P60 (bit 0 of IOC6) must be set to "1". When EIS is "0", the path of /INT is masked. When EIS is "1", the status of /INT pin can also be read by way of reading Port 6 (R6). Refer to Fig. 7(a). EIS is both readable and writable.

• Bit 4 (ROC) ROC is used for the R-option. Setting the ROC to "1" will enable the status of R-option pins (P50∼P51) that are read by the controller. Clearing the ROC will disable the R-option function. If the R-option function is selected, user must connect the P51 pin or/and P50 pin to VSS with a 430KΩ external resistor (Rex). If the

Rex is connected/disconnected, the status of P50 (P51) is read as "0"/"1". Refer to Fig. 8.

• Bits 0~3,5 Not used.

This specification is subject to change without prior notice. 2002/04/19 12

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ELAN EM78P156ELP, EM78P156ELM, EM78P156ELKM, EM78P156ELAS Datasheet

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