ELAN EM78860 Datasheet

GENERAL DESCRIPTION

The EM78860 is an 8-bit RISC type microprocessor with low power , high speed CMOS technology .
Integrated onto a single chip are on_chip watchdog (WDT) , RAM , ROM , programmable real time clock /
counter , internal interrupt , power down mode , LCD driver and tri-state I/O . The EM78860 provides a single
chip solution to design a message display .

FEATURES

CPU

• Operating voltage range : 2.5V~5.5V

• 16Kx13 on chip ROM

• 2.8Kx8 on chip RAM

• Up to 32 bi-directional tri-state I/O ports

• 8 Level stack for subroutine nesting

• 8-bit real time clock/counter (TCC)

• Two sets of 8 bit counters can be interrupt sources

• Selective signal sources and with overflow interrupt

• Programmable free running on chip watchdog timer

• 99.9% single instruction cycle commands

• Four modes (internal clock 3.679MHz, external 32.768KHz)

1. Sleep mode : CPU and 3.679MHz clock turn off, 32.768KHz clock turn off

2. Idle mode : CPU and 3.679MHz clock turn off, 32.768KHz clock turn on

3. Green mode : 3.679MHz clock turn off, CPU and 32.768KHz clock turn on

4. Normal mode : 3.679MHz clock turn on , CPU and 32.768KHz clock turn on

• Low battery detector

• Input port wake up function

• 8 interrupt source , 4 external , 3 internal

• 100 pin QFP or chip

• Port key scan function

• Port interrupt , pull high and open drain functions

• Clock frequency 32.768KHz externally

EM78860

8-BIT MICRO-CONTROLLER

LCD

• LCD operation voltage chosen by software

• Common driver pins : 16

• Segment driver pins : 60

• 1/4 bias

• 1/8,1/16 duty

APPLICATION

1. adjunct units

2. data bank

* This specification are subject to be changed without notice.

6.24.1998

1

PIN ASSIGNMENTS

SEG41

SEG40

SEG39

SEG38

SEG37

SEG36

RESET

P7.7

P7.6

P7.5

P7.4

P7.3/INT3

P7.2/INT2

P7.1/INT1

P7.0/INT0

COM15/P6.7

COM14/P6.6

COM13/P6.5

COM12/P6.4

COM11/P6.3

COM10/P6.2

EM78860

8-BIT MICRO-CONTROLLER

COM9/P6.1

COM8/P6.0

COM7

COM6

COM5

COM4

COM3

GND

COM2

8079787776757473727170696867666564636261605958575655545352

SEG42

SEF43

TEST
SEG44/P8.0
SEG45/P8.1
SEG46/P8.2
SEG47/P8.3
SEG48/P8.4
SEG49/P8.5
SEG50/P8.6
SEG51/P8.7
SEG52/P9.0
SEG53/P9.1
SEG54/P9.2
SEG55/P9.3
SEG56/P9.4
SEG57/P9.5
SEG58/P9.6
SEG59/P9.7

VDD1

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

100

123456789

NC

NCNCNCNCNC

GND

PLLC

FUNCTIONAL BLOCK DIAGRAM

EM78860

101112131415161718192021222324252627282930

XIN

VDD

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

XOUT

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

VDD2

SEG16

51

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

SEG17

COM1
COM0
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18

CPU

CLK

TIMING
CONTROL

TIMER

* This specification are subject to be changed without notice.

ROM

RAM

I/O PORT

INPUT PORT

LCD
LATCH
& DRIVER

I/O PORT

INPUT PORT

LCD
OUTPUT

6.24.1998

2

EM78860

8-BIT MICRO-CONTROLLER

XIN XOUT

Oscillator/Timing

Control

Control of
sleep and

wake-up

on I/O ports

2.5K RAM

R1(TCC)

WDT Timer

Prescaler

GENERAL

RAM

RAM

R4

IOC6

Interrupt

Controller

DATA & CONTROL BUS

PORT6

R6

P60~P67

PORT7

IOC7

P70~P77

ROM

Instruction

register

Instruction

Decoder

R7

PORT8

IOC8

P80~P87

R2

R3
R5

R8

PORT9

IOC9

P90~P97

Stack

ALU

ACC

R9

PIN DESCRIPTIONS

Symbol Type Function

VDD POWER Power
GND POWER Gound
XTin I Input pin for 32.768 kHz oscillator
XTout O Output pin for 32.768 kHz oscillator
PLLC I Phase loop lock capacitor, connect a capacitor 0.01µ to 0.047µ with GND
COM0..COM7 O Common driver pins of LCD drivers
COM8..COM15 O (PORT6)
SEG0..SEG43 Segment driver pins of LCD drivers
SEG44..SEG51 O (PORT8)
SEG52..SEG59 O (PORT9) PORT9 AS FUNCTION KEY CAN WAKE UP WATCHDOG.
INT0 PORT7(0) PORT7(0)~PORT7(3) signal can be interrupt signals.
INT1 PORT7(1)
INT2 PORT7(2)
INT3 PORT7(3)
P7.0~P7.7 PORT7 PORT 7 can be INPUT or OUTPUT port each bit.

Internal Pull high function.
Key scan function.
Bit6,7 open drain function.

P6.0~P6.7 PORT6 PORT 6 can be INPUT or OUTPUT port each bit.

And shared with Common signal.

P8.0~P8.7 PORT8 PORT 8 can be INPUT or OUTPUT port each bit.

And shared with Common signal.

P9.0~P9.7 PORT9 PORT 9 can be INPUT or OUTPUT port each bit.

And shared with Common signal.
TEST I Test pin into test mode , normal low
RESET I

* This specification are subject to be changed without notice.

6.24.1998

3

FUNCTION DESCRIPTION

Operational Registers

R0 (Indirect Addressing Register)

R0 is not a physically implemented register. It is useful as indirect addressing pointer. Any instruction using
R0 as register actually accesses data pointed by the RAM Select Register (R4).

R1 (TCC)

• Increased by an internal signal edge applied to TCC , or by the instruction cycle clock.

• Written and read by the program as any other register.

R2 (Program Counter)

• The structure is depicted in Fig. 4.

• Generates 16Kx13 on-chip ROM addresses to the relative programming instruction codes.

• ”JMP” instruction allows the direct loading of the low 10 program counter bits.

• “CALL” instruction loads the low 10 bits of the PC, PC+1, and then push into the stack..

• “RET’’ (“RETL k”, “RETI”) instruction loads the program counter with the contents at the top of stack.

• ”MOV R2,A” allows the loading of an address from the A register to the PC, and the ninth and tenth bits are
cleared to “0'’.

• “ADD R2,A” allows a relative address be added to the current PC, and contents of the ninth and tenth bits are
cleared to “0'’.

• “TBL” allows a relative address be added to the current PC, and contents of the ninth and tenth bits don’t
change.

• The most significant bit (A10~A13) will be loaded with the content ofbit PS0~PS3 in the status register (R5)
upon the execution of a “JMP’’, “CALL’’, “ADD R2,A’’, or “MOV R2,A’’ instruction.

EM78860

8-BIT MICRO-CONTROLLER

A13 A12 A11 A10 A9 A8

PC

Fig.4 Program counter organization

A7~A0 Stack 1

0000 PAGE0 0000~03FF

0000 PAGE1 0400~07FF

0000 PAGE3 0800~0BFF

1110 PAGE14 3800~3BFF

1111 PAGE15 3C00~3FFF

CALL

RET
RETTL
RETI

Stack 2
Stack 3
Stack 4
Stack 5
Stack 6
Stack 7
Stack 8

* This specification are subject to be changed without notice.

6.24.1998

4

ADDRESS REGISTER

R0

00

R1(TCC)

01

R2(PC)

02

R3(STATUS)

03

R4(RSR)

04

R5(ROM PAGE)

05
06

R6(PORT6)

07

R7(PORT7)

08

R8(PORT8)

09

R9(PORT9)

0A

RA(CLK)

0B

RB()

0C

RC(2.5K RAM ADRESS)

0D

RD(2.5K RAM DATA)

0E

RE

0F

RF(INT FLAG)

10
:
1F

16x8
Common

Register

CONTROL REGISTER
(PAGE0)

page0

IOC6
IOC7
IOC8
IOC9
IOCA
IOCB(LCD ADDRESS)
IOCC(LCD DATA)
IOCD(PULL HIGH)
IOCE(IO, LCD)
IOCF(INT CONTROL)

RC(ADDRESS) RD(DATA)

EM78860

8-BIT MICRO-CONTROLLER

CONTROL REGISTER
(PAGE1)

page1

IOCB(COUNTER1)
IOCC(COUNTER2)

20
:
3F

BANK0~BANK3

32X8 ~ 32X8

REGISTER

255

0

:

BAND1

256X8

BAND1

256X8

. . . . . . . . . . . .

. . . . . . . . . . . .

BAND10

256X8

Fig.5 Data memory configuration

R3 ( Status Register )

76543210

- PAGE - T P Z DC C

• Bit 0 (C) : Carry flag

• Bit 1 (DC) : Auxiliary carry flag

• Bit 2 (Z) : Zero flag

• Bit 3 (P) : Power down bit. Set to 1 during power on or by a “WDTC” command and reset to 0 by a

“SLEP” command.

• Bit 4 (T) : Time-out bit. Set to 1 by the “SLEP” and “WDTC” command, or during power up and reset

to 0 by WDT time out.

EVENT T P REMARK
WDT TIME OUT 0 0
sleep mode
WDT time out (not sleep mode 0 1
/RESET wake up from sleep 1 0
power up 1 1
Low pulse on /RESET x x x . . don't care

• Bit 5 : unused

• Bit 6 PAGE : changed IOCB~IOCE to another page, 0/1→page0/page1

• Bit 7 unused

* This specification are subject to be changed without notice.

6.24.1998

5

8-BIT MICRO-CONTROLLER

R4 ( RAM Select Register )

• Bit 0 ~ 5 are used to select up to 64 register in the indirect addressing mode.

• Bit 6 ~ 7 determine which bank is actived among the 4 banks.

• See the configuration of the data memory in Fig.4.

R5 ( Program Page Select Register)

765 43210

- - - - PS3 PS2 PS1 PS0

• Bit 0 (pS0) ~ 3 (PS3) Page selec bits.

Page select bits

PS3 PS2 PS1 PS0 program memory page (Address)

0000 Page 0
0001 Page 1
0010 Page 2
0011 Page 3
0100 Page 4
0101 page 5
0110 Page 6
0111 Page 7
1000 Page 8
1001 Page 9
1010 Page 10
1011 Page 11
1100 Page 12
1101 Page 13
1110 Page 14
1111 Page 15

EM78860

• User can use PAGE instruction to change page. To maintain program page by user. Otherwise, user can use
far jump (FJMP) or far call (FCALL) instructions to program user's code. And the program page is maintained
by EMC's complier. It will change user's program by inserting instruction within program.

• Bit4~7 : unused

R6 ~R9 ( Port 6 ~ Port 9)

• Five 8-bit I/O registers.

RA

7654 3210

IDLE /358E /LPD /LOW-BAT 0 0 0 0

• Bit0 ~ Bit3 unused, please set to "0"

* This specification are subject to be changed without notice.

6.24.1998

6

EM78860

t

8-BIT MICRO-CONTROLLER

• Bit4(Read Only)(Low battery signal) 0/1 = Battery voltage is low/Normal .
If the battery voltage is under 3.6V then sends a ‘0’ signal to RA register bit4 or a ‘1’ signal to this Bit if VDD
is over 3.8V.

• Bit5(read/Write)(Low battery detect enable)
0/1 = low battery detect DISABLE/ENABLE.
The relation between /LPD,/POVD and /LOW_BAT can see Fig6.

Vdd

/POVD

s2
1 on
0 off

1 on

Vref

/LPD

1 on

+

-

to Low bat

To rese

s2
1 on
0 off

/LPD

Fig6. The relation between /LPD,/POVD

• Bit6(read/write)(PLL enable signal)
0/1=DISABLE/ENABLE

The relation between 32.768K and 3.679M can see Fig7.

PLL

32.768K

3.679M

/358E

switch

1

To system clock

0

Fig7. The relation between 32.768K and 3.679K .

• Bit7 IDLE: sleep mode selection bit
0/1=sleep mode/IDLE mode. This bit will decide SLEP instruction which mode to go.
These IDLE mode can be waken up by TCC clock or Watch Dog or PORT9 and run from “SLEP” next
instruction.
These SLEEP mode can be waken up by Watch Dog or PORT9 and run from address “00”.

SLEEP mode IDLE mode GREEN mode NORMAL mode

RA(7,6)=(0,0) RA(7,6)=(1,0) RA(7,6)=(x,0) RA(7,6)=(x,1)
+ SLEP + SLEP no SLEP no SLEP

TCC time out X Wake-up Interrupt Interrupt

+ Interrupt
+ Next instruction

WDT time out RESET Wake-up RESET RESET

+ Next instruction RESET RESET

Port9 wake-up RESET Wake-up

+ Next instruction

* This specification are subject to be changed without notice.

6.24.1998

7

8-BIT MICRO-CONTROLLER

RB

Empty register, please don't use.

RC(2.5k RAM address)(read/write)

76 5 4 3 2 1 0

CIDA7 CIDA6 CIDA5 CIDA4 CIDA3 CIDA2 CIDA1 CIDA0

• Bit 0 ~ Bit 7 select CALLER ID RAM address up to 256.

RD(2.5k RAM address)(read/write)

• Bit 0 ~ Bit 8 are CALLER ID RAM data transfer register.
User can see IOCA register how to select CID RAM banks.

RE(LCD Driver,WDT Control)(read/write)

76 5 4 3 2 1 0

- /WDTE /WUP9H /WUP9L /WURING LCD_C2 LCD_1 LCD_M

EM78860

• Bit0 (LCD_M):LCD_M decides the methods, including duty, bias, and frame frequency.

• Bit1~Bit2 (LCD_C#):LCD_C# decides the LCD display enable or blanking. change the display duty must
set the “LCD_C2,LCD_C1” to “00”.

LCD_C2,LCD_C1 LCD Display Control LCD_M duty bias
0 0 Change duty 0 1/16 1/4

Disable(turn off LCD) 1 1/8 1/4
0 1 Blanking : :
1 1 LCD display enable : :

• Bit3 unused. Please set to "0"

• Bit4(/WUP9L, PORT9 low nibble Wake Up Enable) : used to enable the wake-up function of low nibble in
PORT9, (1/0=enable/disable)

• Bit5 (/WUP9H, PORT9 high nibble WAKE Up Enable) : used to enable the wake-up function of high
nibble in PORT9, (1/0=enable/disable)

• Bit6 (/WDTE, Watch Dog Timer Enable)
Control bit used to enable Watchdog timer. (1/0=enable/disable)

• Bit7 unused

RF (Interrupt Status Register)

765432 1 0

INT3 - C8_2 C8_1 INT2 INT1 INT0 TCIF

• “1” means interrupt request, “0” means non-interrupt

• Bit 0 (TCIF) TCC timer overflow interrupt flag. Set when TCC timer overflows .

• Bit 1 (INT0) external INT0 pin interrupt flag .

• Bit 2 (INT1) external INT1 pin interrupt flag .

• Bit 3 (INT2) external INT2 pin interrupt flag .

• Bit 4 (C8_1) internal 8 bit counter interrupt flag .

• Bit 5 (C8_2) internal 8 bit counter interrupt flag .

* This specification are subject to be changed without notice.

6.24.1998

8