ELAN EM78811 Datasheet
GENERAL DESCRIPTION
The EM78811 is an 8-bit CID (Call Identification) RISC type microprocessor with low power , high speed
CMOS technology. Integrated onto a single chip are on_chip watchdog (WDT) , RAM , ROM , programmable
real time clock /counter , internal interrupt , power down mode , LCD driver , FSK decoder , DTMF generator
and tri-state I/O . The EM78811 provides a single chip solution to design a CID of calling message_display .
FEATURES
CPU
• Operating voltage range : 2.5V~5.5V
• 16K X13 on chip ROM
• 2.8K X 8 on chip RAM
• Up to 32 bi-directional tri-state I/O ports
• 8 level stack for subroutine nesting
• 8-bit real time clock/counter (TCC)
• Two sets of 8 bit counters can be interrupt sources
• Selective signal sources and trigger edges , and with overflow interrupt
• Programmable free running on chip watchdog timer
• 99.9% single instruction cycle commands
• Three modes (internal clock 3.679MHz)
1. sleep mode : CPU and 3.679MHz clock turn off, 32.768KHz clock turn off
2. Idle mode : CPU and 3.679 MHz clock turn off, 32.768KHz clock turn on
3. Green mode : 3.679MHz clock turn off, CPU and 32.768KHz clock turn on
4. Normal mode : 3.679MHz clock turn on , CPU and 32.768KHz clock turn on
• Ring on voltage detector and low battery detector
• Input port wake up function
• 8 interrupt source , 4 external , 4 internal
• 100 QFP or chip
• Port key scan function
• Port interrupt, Pull high and Open drain functions
• Clock frequency 32.768KHz
• Main clock can switch to 1.84MHz by code option
EM78811
EM78811
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
CID
• Operation Volltage 3.5 ~5.5V for FSK
• Operation Volltage 2.5 ~5.5V for DTMF
• Bell 202 , V.23 FSK demodulator
• DTMF generator
• Ring detector on chip
LCD
• LCD operation voltage chosen by software
• Common driver pins : 16
• Segment driver pins : 60
• 1/4 bias
• 1/8,1/16 duty
* This specification are subject to be changed without notice.
10.12.1998
1
APPLICATION
1. adjunct units
2. answering machines
3. feature phones
PIN ASSIGNMENTS
SEG59/P9.7
VDD1
SEG56/P9.4
SEG57/P9.5
SEG58/P9.6
EM78811
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
SEG44/P8.0
SEG45/P8.1
SEG46/P8.2
SEG47/P8.3
SEG48/P8.4
SEG49/P8.5
SEG50/P8.6
SEG51/P8.7
SEG52/P9.0
SEG53/P9.1
SEG54/P9.2
SEG55/P9.3
SEG42
SEF43
TEST
AVSS
DTMF
PLLC
RINGTIME
RDET1
RING
TIP
NC
XIN
XOUT
AVDD
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
VDD2
SEG17
FUNCTIONAL BLOCK DIAGRAM
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
SEG19
SEG18
SEG20
SEG21
SEG22
EM78811
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
COM0
81828384858687888990919293949596979899
50494847464544434241403938373635343332
COM1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
RESET
P7.7
P7.6
P7.5
P7.4
P7.3/INT3
P7.2/INT2
P7.1/INT1
P7.0/INT0
COM15/P6.7
COM14/P6.6
COM13/P6.5
COM12/P6.4
COM11/P6.3
COM10/P6.2
COM9/P6.1
COM8/P6.0
COM7
COM6
COM5
COM4
COM3
VSS2
COM2
CPU
CLK
FSK
INPUT
TIMING
CONTROL
TIMER
FSK
DEMODULATOR
DTMF
* This specification are subject to be changed without notice.
ROM
RAM
I/O PORT
INPUT PORT
LCD
LATCH
& DRIVER
I/O PORT
INPUT PORT
LCD
OUTPUT
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2
EM78811
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
Xin Xout
Oscillator/Timing
Control
sleep and
wake-up
on I/O ports
Control
WDT Timeout
R1(TCC)
CALLER ID
RAM
COM0˜COM7
SEG0˜SEG35
WDTTimer
Prescaler
RAM
R4
TCC
ROM
Interrupt
Controller
Instruction
register
Instruction
Decoder
DATA & CONTROLL BUS
LCD RAM
LCD Driver
RA
R2
IOC7
R7
Ring det
Carrier det
Data
/FSKPWR
R3
I/O
PORT
Stack
ALU
ACC
FSK
Decoder
P70˜P77
TIP
RING
RING DET1
RING TIME
IOC8
P80˜P87
SEG44˜SEG51
P90˜P97
SEG52˜SEG59
R8
IOC9
R9
I/O
PORT
8
I/O
PORT
9
* This specification are subject to be changed without notice.
IOC6
R6
RB
I/O
PORT
6
Row
Column
low battery
detect
DTMF
P60˜P67
COM8˜COM15
DTMF output
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3
EM78811
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
PIN DESCRIPTIONS
Symbol Type Function
VDD1,VDD2 POWER digital power
AVDD analog power
VSS1,VSS2 POWER digital ground
AVSS analog ground
XTin I Input pin for 32.768 kHz oscillator
XTout O Output pin for 32.768 kHz oscillator
COM0..COM7 O
COM8..COM15 O (PORT6) Common driver pins of LCD drivers
SEG0..SEG43 Segment driver pins of LCD drivers
SEG44..SEG51 0 (PORT8)
SEG52..SEG59 O (PORT9) PORT9 AS FUNCTION KEY CAN WAKE UP WATCHDOG.
PLLC I Phase loop lock capacitor, connect a capacitor 0.01µ to 0.047µ with AVSS.
TIP I Should be connected with TIP side of twisted pair lines
RING I Should be connected with TIP side of twisted pair lines
RDET1..RDET 2 I Detect the energy on the twisted pair lines.These two pins coupled to the twisted pair
lines through an attenuating network.
/RING TIME I Determine if the incoming ring is valid. An RC network may be connected to the pin.
INT0 PORT7(0) PORT7(0)~PORT7(3) signal can be interrupt signals.
INT1 PORT7(1)
INT2 PORT7(2)
INT3 PORT7(3)
PORT7(4:7) IO port
P7.0~P7.7 PORT7 PORT 7 can INPUT or OUTPUT port each bit.
Internal Pull high function.
Key scan function. Bit6,7 has open drain function
P6.0~P6.7 PORT6 PORT6 can be INPUT or OUTPUT port each bit.
And shared with common signal.
P8.0~P8.7 PORT8 PORT 8 can be INPUT or OUTPUT port each bit.
And shared with Segment signal.
P9.0~P9.7 PORT9 PORT 9 can be INPUT or OUTPUT port each bit.
And can be set to wake up watch dog timer.
And shared with Segment signal.
TEST I Test pin into test mode , normal low
DTMF O DTMF tone output
RESET I
FUNCTION DESCRIPTION
Operational Registers
R0 (Indirect Addressing Register)
* R0 is not a physically implemented register. It is useful as indirect addressing pointer. Any instruction using
R0 as register actually accesses data pointed by the RAM Select Register (R4).
R1 (TCC)
* Increased by an external signal edge applied to TCC , or by the instruction cycle clock Written and read by
the program as any other register.
* This specification are subject to be changed without notice.
10.12.1998
4
EM78811
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
R2 (Program Counter)
* The structure is depicted in Fig. 4.
* Generates 16Kx13 ( 14 on-chip ROM addresses to the relative programming instruction codes.
* "JMP" instruction allows the direct loading of the low 10 program counter bits.
* "CALL" instruction loads the low 10 bits of the PC, PC+1, and then push into the stack.
* "RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack.
* "MOV R2,A" allows the loading of an address from the A register to the PC, and the ninth and tenth bits
are cleared to "0''.
* "ADD R2,A" allows a relative address be added to the current PC, and contents of the ninth and tenth bits
are cleared to "0''.
* "TBL" allows a relative address be added to the current PC, and contents of the ninth and tenth bits don't
change. The most significant bit (A10~A13) will be loaded with the content of bit PS0~PS3 in the status
register (R5) upon the execution of a "JMP'', "CALL'', "ADD R2,A'', or "MOV R2,A'' instruction.
CALL
PC
A13 A12 A11 A10
A9 A8
A7~A0
RET
RETL
RETI
Stack 1
Stack 2
Stack 3
Stack 4
Stack 5
1000
2000
Page 8
0000
0000
Page 0
Stack 6
Stack 7
1001
23FF
2400
Page 9
0001
03FF
0400
Page 1
Stack 8
1010
1011
1100
1101
1110
1111
27FF
2800
2CFF
2D00
2FFF
3000
33FF
3400
37FF
3800
3CFF
3D00
3FFF
Page 10
Page 11
Page 12
Page 13
Page 14
Page 15
0010
0011
0100
0101
0110
0111
07FF
0800
0CFF
0D00
0FFF
1000
13FF
1400
1CFF
1D00
1FFF
Fig.4 Program counter organization
17FF
1800
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
* This specification are subject to be changed without notice.
10.12.1998
5
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
:
1F
20
:
3F
R0
R1(TCC)
R2(PC)
R3(STATUS)
R4(RSR)
R5(Program Page)
R6(PORT6)
R7(PORT7)
R8(PORT8)
R9(PORT9)
RA(FSK STATUS)
RB(DTMF)
RC(CID ADRESS)
RD(CID DATA)
RE(LCD,WDT,WUE)
RF(INTERRUPT)
16x8
Common
Register
00 BANK0
32X8
REGISTER
01 BANK1
32X8
REGISTER
EM78811
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
IOC6
IOC7
IOC8
IOC9
IOCA(RAM,IO,PAGE ctl )
IOCB(lcd address )
IOCC(lcd data )
IOCD(PULL HIGH control)
IOCE(IO,Vlcd control )
IOCF(interrupt control)
10 BANK2
32X8
REGISTER
11 BANK3
32X8
REGISTER
IOCB(COUNTER1)
IOCC(COUNTER2)
IOCE(OTHER )
IOCB IOCC
00h
ffH
0001
CALLER RAM
0010
0011
BAND3
BAND4
256X8
256X8
0100
BAND5
256X8
0101
BAND6
256X8
0110
BAND7
256X8
0111
BAND8
256X8
1000
BAND9
256X8
BAND10
0000
BAND1
256X8
BAND2
256X8
:
1001
256X8
00h
78h
:
:
:
LCD RAM
120x8
Fig.5 Data memory configuration
R3 ( Status Register )
76 5432 10
- page - T P Z DC C
• Bit 0 (C) : Carry flag
• Bit 1 (DC) : Auxiliary carry flag
• Bit 2 (Z) : Zero flag
• Bit 3 (P) : Power down bit. Set to 1 during power on or by a “WDTC” command and reset to 0 by a
SLEP” command.
• Bit 4 (T) : Time-out bit. Set to 1 by the “SLEP” and “WDTC” command, or during power up and reset
to 0 by WDT time out.
EVENT T P REMARK
WDT wake up from sleep mode 0 0
WDT time out (not sleep mode) 0 1
/RESET wake up from sleep 1 0
power up 1 1
• Bit 5 : unused
• Bit 6 PAGE : change IOCB~IOCE to another page, 0/1→page0/page1
• Bit 7 : unused
R4 ( RAM Select Register )
• Bit 0 ~ 5 are used to select up to 64 register in the indirect addressing mode.
• Bit 6 ~ 7 determine which bank is actived among the 4 banks.
• See the configuration of the data memory in Fig.5.
* This specification are subject to be changed without notice.
10.12.1998
6
R5 (Program Page Select Register)
76543210
- - - - PS3 PS2 PS1 PS0
• Bir0 (PS0) ~ 3 (PS3) Page select bits
Page selects bits
PS3 PS2 PS1 PS0 Program memory page (Address)
0 0 0 0 Page 0 ( 0000 - 03FF )
0 0 0 1 Page 1 ( 0400 - 07FF )
0 0 1 0 Page 2 ( 0800 - 0BFF )
0 0 1 1 Page 3 ( 0C00 - 0FFF )
0 1 0 0 Page 4 (1000 - 13FF )
0 1 0 1 Page 5 ( 1400 - 17FF )
0 1 1 0 Page 6 ( 1800 - 1BFF )
0 1 1 1 Page 7 ( 1C00 - 1FFF )
1 1 1 1 Page 8 ( 2000 - 23FF)
1 1 1 1 Page 9 (2400 - 27FF)
:::;:
1 1 1 1 Page 15 (3C00 - 3FFF)
EM78811
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
• User can use PAGE instruction to change page. To maintain program page by user. Otherwise, user can use
far jump (FJMP) or far call (FCALL) instructions to program user's code. And the program page is maintained
by EMC's complier. It will change user's program by inserting instructions within program.
• Bit4~7 : unused
R6 ~ R9 (Port 6 ~ Port 9)
• Five 8-bit I/O registers.
RA (FSK Status Register)(bit0,1,2,4 read only))
765 4 3 210
IDLE /358E /LPD /LOW-BAT /FSKPWR DATA /CD /RD
• Bit0 (Read Only) (Ring detect signal)
0/1 : Ring Valid/Ring Invalid
• Bit1(Read Only)(Carrier detect signal)
0/1 : Carrier Valid/Carrier Invalid
• Bit2(Read Only)(FSK demodulator output signal)
Fsk data transmitted in a baud rate 1200 Hz. Data from FSK demodulator when /CD is Low.
• Bit3(read/write)(FSK block power up signal)
1/0 : FSK demodulator block power up/FSK demodulator power down
The relation between Bit0 to Bit3 is shown in Fig.6.
* This specification are subject to be changed without notice.
10.12.1998
7
/RD and /CD ='1'
/RINGTIME='0'
or EXTERNAL KEYS
PRESSEDsleep mode
/RD and /CD ='1' and
nothing to do for 30
sec , /FSKPWR='0'
/FSKPWR='1'
EM78811
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
SLEEP MODE
Begin
set /FSKPWR='0'
/RINGTIME ='0'
No
or external keys
pressed
Yes
WAKE UP MODE
8-bit wake up andÁ
wake up
mode
set /FSKPWR='1'
accept data from
FSK decoder
FSK decoder
begin its work
STATE Diagram between 8-bit
and FSK decoder
DATA transfer
DATA transfer
to Micro
/RD and /CD ='1'
Yes
data end and 30
sec nothing to do.
Flow Diagram between 8-bit
and FSK decoder
No
Fig6. The relation between Bit0 to Bit3.
• Bit4(Read Only)(Low battery signal)
0/1 = Battery voltage is low/Normal . If the battery voltage is under 3.6V then sends a ‘0’ signal to RA register
bit4 or sends a '1' signal to this bit.
• Bit5(read/Write)(Low battery detect enable)
0/1 = low battery detect DISABLE/ENABLE. The relation between /LPD,/POVD and /LOW_BAT can see
Fig7.
Vdd
s2
1 on
0 off
1 on
Vref
+
-
/POVD
/LPD
to Low bat
1 on
To reset
s2
1 on
0 off
Fig7. The relation between /LPD,/POVD
• Bit6(read/write)(PLL enable signal)
0/1=DISABLE/ENABLE, The relation between 32.768K and 3.679M can see Fig8.
PLL
32.768K
3.679M
/358E
Fig8. The relation between 32.768K and 3.58K .
* This specification are subject to be changed without notice.
1
switch
0
/LPD
To system clock
10.12.1998
8
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
• Bit7 IDLE : Sleep mode selection bit
0/1=sleep mode/IDLE mode. This bit will decide SLEP instruction which mode to go.
These two modes can be waken up by TCC clock or Watch Dog or PORT9 and run from "SLEP" next
instruction.
SLEEP moe IDLE mode GREEN mode NORMAL mode
RA(7,6)=(0,0) RA(7,6)=(1,0) RA(7,6)=(x,0) RA(7,6)=(x,1)
+SLEP +SLEP no SLEP no SLEP
TCC time out X Wake-up Interrupt Interrupt
+Interrupt
+Next instruction
WDT time out RESET Wake-up RESET RESET
+Next instruction
Port9 wake-up RESET Wake-up RESET RESET
+Next instruction
RB(DTMF tone row and column register) (read/write)
EM78811
7 6543 210
c7 c6 c5 c4 r3 r2 r1 r0
• Bit 0 - Bit 3 are row-frequency tone.
• Bit 4 - Bit 7 are column-frequency tone.
• Initial RB is equal to high. Bit7~0 are all "1", turn off DTMF power.
bit3~0 Row freq
1110 699.2 Hz 1 2 3 A
1101 771.6 Hz 4 5 6 B
1011 854 Hz 7 8 9 C
0111 940.1 Hz * 0 # D
Column freq 1203 Hz 1331.8 Hz 1472 Hz 1645.2 Hz
bit 7~4 1110 1101 1011 0111
RC(CALLER ID address)(read/write)
765 432 1 0
CIDA7 CIDA6 CIDA5 CIDA4 CIDA3 CIDA2 CIDA1 CIDA0
• Bit 0 ~ Bit 7 select CALLER ID RAM address up to 256.
RD(CALLER ID RAM data)(read/write)
• Bit 0 ~ Bit 8 are CALLER ID RAM data transfer register.
User can see IOCA register how to select CID RAM banks.
RE(LCD Driver,WDT Control)(read/write)
76 5 4 3 2 1 0
- /WDTE /WUP9H /WUP9L /WURING LCD_C2 LCD_1 LCD_M
• Bit0 (LCD_M):LCD_M decides the methods, including duty, bias, and frame frequency.
• Bit1~Bit2 (LCD_C#):LCD_C# decides the LCD display enable or blanking.
change the display duty must set the “LCD_C2,LCD_C1” to “00”.
* This specification are subject to be changed without notice.
10.12.1998
9
EM78811
8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT
LCD_C2, LCD_C1 LCD Display Control LCD_M duty bias
0 0 change duty 0 1/16 1/4
Disable (turn off LCD) 1 1/8 1/4
0 1 Blanking : :
1 1 LCD display enable : :
• Bit3 (/WURING, RING Wake Up Enable): used to enable the wake-up function of /RINGTIME input pin.
(1/0=enable/disable)
• Bit4 (/WUP9L, PORT9 low nibble Wake Up Enable): used to enable the wake-up function of low nibble in
PORT9.(1/0=enable/disable)
• Bit5 (/WUP9H, PORT9 high nibble Wake Up Enable): used to enable the wake-up function of high nibble
in PORT9.(1/0=enable/disable)
• Bit6 (/WDTE,Watch Dog Timer Enable)
Control bit used to enable Watchdog timer.
(1/0=enable/disable)
The relation between Bit3 to Bit6 can see the diagram 9.
• Bit7 unused
/WURING
/RINGTIME
/WUP9L
PORT9(3:0)
/WUP9H
PORT9(7:4)
/WDTE
/WDTEN 1/0=enable/disable
fig.9 Wake up function and control signal
RF (Interrupt Status Register)
76543210
INT3 FSKDATA C8_2 C8_1 INT2 INT1 INT0 TCIF
*“1” means interrupt request, “0” means non-interrupt
* Bit 0 (TCIF) TCC timer overflow interrupt flag. Set when TCC timer overflows.
* Bit 1 (INT0) external INT0 pin interrupt flag .
* Bit 2 (INT1) external INT1 pin interrupt flag .
* Bit 3 (INT2) external INT2 pin interrupt flag .
* Bit 4 (C8_1) internal 8 bit counter interrupt flag .
* Bit 5 (C8_2) internal 8 bit counter interrupt flag .
* Bit 6 (FSKDATA) FSK data interrupt flag.
* Bit 7 (INT3) external INT3 pin interrupt flag.
* High to low edge trigger , Refer to the Interrupt subsection.
* IOCF is the interrupt mask register. User can read and clear.
R10~R3F (General Purpose Register)
• R10~R3F (Banks 0~3) all are general purpose registers.
* This specification are subject to be changed without notice.
10.12.1998
10
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