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EM78451
User Manual
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ELAN EM78451 User Manual

EM78451
MASK ROM
1. GENERAL DESCRIPTION
This specification is subject to change without prior notice. 2002/03/01
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2. FEATURES
• Operating voltage range: 2.3V~5.5V.
• Operating temperature range: 0°C~70°C.
• Operating frequency rang (base on2 clocks ): * Crystal mode: DC~20MHz at 5V, DC~8MHz at 3V, DC~4MHz at 2.3V. * RC mode: DC~4MHz at 5V, DC~4MHz at 3V, DC~4MHz at 2.3V.
• Low power consumption: * Less then 3 mA at 5V/4MHz
EM78451
MASK ROM
* Typically 10 µA during sleep mode
• Serial Peripheral Interface (SPI) available.
• 4K × 13 bits on chip ROM (EM78451).
• 11 special function registers.
• 140× 8 bits on chip general-purposed registers.
• 5 bi-directional I/O ports (35 I/O pins).
• 3 LED direct sinking pins with internal serial resistors.
• Built-in RC oscillator with external serial resistor, ±10% variation.
• Built-in power-on reset.
• Five stacks for subroutine nesting.
• 8-bit real time clock/counter (TCC) with overflow interrupt.
• Two machine clocks or four machine clocks per instruction cycle.
• Power down mode.
• Programmable wake up from sleep circuit on I/O ports.
• Programmable free running on-chip watchdog timer.
• 12 wake-up pins.
• 2 open-drain pins.
• 2 R-option pins.
• 32 programmable pull-high input pins.
• Package types: * 40 pin DIP 600mil : EM78451AP. * 44 pin QFP : EM78451AQ.
This specification is subject to change without prior notice. 2002/03/01
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• Four types of interrupts. * External interrupt (/INT). * SPI transmission completed interrupt. * TCC overflow interrupt. * Timer1 comparator match interrupt.
EM78451
MASK ROM
This specification is subject to change without prior notice. 2002/03/01
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3. PIN ASSIGNMENT
driving pin with internal serial resistor is used as output and is
high by software,
* General bi-directional I/O port. All of its pins can be pulled-high * *
EM78451
MASK ROM
VSS
INT
DATA
CLK
P90 P91
SDI/P92 SDO/P93 SCK/P94
SS/P95
P50 P51 P52 P53 P54 P55 P56 P57 P80 P81
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20
40
OSCO
39
R-OSCI
38
VDD
37
P70
36
P71
35
P72
34
P67
33
P66
32
P65
31
P64
30
P63
29
EM78451AP/WM
P62
28
P61
27
P60
26
P87
25
P86
24
P85
23
P84
22
P83
21
P82
P91
SDI/P92 SDO/P93 SCK/P94
SS/P95
P50 P51 P52 P53 P54
DATA
INT
CLK
VSS
4443424140393837363534
1 2 3 4 5 6 7 8
9 10 11
EM78451AQ
121314151617181920
P55
P80
P57
P56
OSCO
R-OSCI
NC
P81
VDD
P82
NCNCNC
21
P83
P85
P84
P70
22
P86
Fig. 1 Pin assignment
Table 1 Pin description
Symbol Pin No. Type Function Description
R-OSCI 39 I
* In XTAL mode: Crystal input; In internal C, external R mode: 56K ohm±5% pull high for 1.8432MHz.
OSCO 40 O * In XTAL mode: Crystal output; In RC mode: Instruction clock output.
* General bi-directional I/O port. All of its pins can be pulled-high by
P90~P95 5~10 I/O
software. * P90 and P91 are pin-change wake up pins.
* General bi-directional I/O port. All of its pins can be pulled-high by
P80~P87 19~26 I/O
software. * P80 and P81 are also used as the R-option pins.
P70~P72 37~35 I/O
CLK 4 I/O
* LED direct­software defined. * By connecting P74 and P76 together. * P74 can be pulled-high by software and it is also a pin-change wake up pin. * P76 can be defined as an open-drain output. * By connecting P75 and P77 together.
DATA 3 I/O
* P75 can be pulled-high by software and it is also a pin-change wake up pin.
* P77 can be defined as an open-drain output. P60~P67 27~34 I/O P50~P57 11~18 I/O
* General bi-directional port. All of its pins can be pulled-
and pin-change wake up pins.
33
P71P90
32
P72
31
P67
30
P66
29
P65
28
P64
27
P63
26
P62
25
P61
24
P60
23
P87
This specification is subject to change without prior notice. 2002/03/01
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Individually by software.
triggered pin. The function of interrupt triggers at the
VDD 38 - * Power supply pin. VSS 1 - * Ground pin.
* An interrupt schmitt­/INT 2 I
SDI 7 I/O * Serial data in for SPI SDO 8 I/O * Serial data out for SPI. SCK 9 I/O * Serial clock for SPI. /SS 10 I/O * /Slave select for SPI.
falling edge. Users can enable it by software. The internal pull-up resistor
is around 50K ohm.
EM78451
MASK ROM
This specification is subject to change without prior notice. 2002/03/01
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4. FUNCTION DESCRIPTION
EM78451
MASK ROM
Oscillator/
Timming
Control
Sleep
&
Wake Up
Control
WDT
Time-out
P
P
5
5
0
1
IOC5
R5
P
P
5
5
2
3
P 5 4
Prescaler
R1(TCC)
P
P
P
5
5
5
5
6
7
WDT Timer
/INT
Interrupt
Control
RAM
R4
IOC6
R6
P
P
P
P
P
P
P 6 0
P
6
6
6
6
6
6
6
1
2
3
4
5
6
7
IOC7
P 7 0
ROM
Instruction
Register
Instruction
Decoder
DATA & CONTROL BUS
R7
P
P
7
7
1
2
Fig. 2 Functional Block Diagram
P C
STACK 1 STACK 2 STACK 3 STACK 4 STACK 5
ALU
ACCR3
TMR1
IOC8
R8
P
P
P
P
P
P
P 8 0
P
8
8
8
8
8
8
8
1
2
3
4
5
6
7
IOC9
R9
P
P
P
P 9 0
P
P
9
9
9
5
9
4
3
2
5
1
/
/
/
/
S
S
S
/
D
C
D
S
O
K
I
S
SPI
ENGIN
4.1 Operational Registers
1. R0 (Indirect Address Register)
R0 is not a physically implemented register. It is used as an indirect addressing pointer. Any instruction using R0 as register actually accesses data pointed by the RAM Select Register (R4).
2. R1 (TCC)
• Increased by the instruction cycle clock.
• Written and read by program as any other register.
3. R2 (Program Counter) & Stack
• R2 and the hardware stacks are 12 bits wide.
• The structure is depicted in Fig. 3.
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EM78451
MASK ROM
• Generates 4K × 13 on-chip ROM addresses to the relative programming instruction codes. One program page is 1024 words long.
• All the R2 bits are set to "1"s as a RESET condition occurs.
• "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows jump to any location on one page.
• "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere within a page.
• "RET" ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack.
• "MOV R2, A" allows the loading of an address from the "A" register to the lower 8 bits of PC, and the ninth and tenth bits (A8~A9) of PC are cleared.
• "ADD R2, A" allows a relative address be added to the current PC, and the ninth and tenth bits of PC are cleared.
• Any instruction that is written to R2 (e.g. "ADD R2, A", "MOV R2, A", "BC R2,6",⋅⋅⋅⋅⋅) (except "TBL") will cause the ninth and tenth bits (A8~A9) of PC to be cleared. Thus, the computed jump is limited
to the first 256 locations of any program page.
• "TBL" allows a relative address be added to the current PC (R2+A→R2), and contents of the ninth and tenth bits (A8~A9) of PC are not changed. Thus, the computed jump can be on the second (or third, 4th) 256 locations on one program page.
• In case of EM78451, the most significant bit (A10,A11) will be loaded with the content of bit PS0 ~PS1 in the status register (R3) upon the execution of a "JMP", "CALL", or any other instructions which write to R2.
• All instructions are single instruction cycle (fclk/2 or fclk/4) except for the instruction that would change the contents of R2. Such instruction will need one more instruction cycle.
PC A11A10 A9A8 A7 ~ A0
00
01
10
11
000
3FF
400
7FF
800 BFF
C00 FFF
Page 0
Page 1
Page 2
Page 3
CALL
RET
RETL
RETI
001:Hareware interrupt location
002:Software interrupt (INT instruction) location
FFF:Reset location
Stack 1 Stack 2 Stack 3 Stack 4 Stack 5
Fig. 3 Program counter organization
This specification is subject to change without prior notice. 2002/03/01
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EM78451
MASK ROM
4. R3 (Status Register)
7 6 5 4 3 2 1 0
GP PS1 PS0 T P Z DC C
• Bit 0 (C) Carry flag
• Bit 1 (DC) Auxiliary carry flag
• Bit 2 (Z) Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero.
• Bit 3 (P) Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command.
• Bit 4 (T) Time-out bit. Set to 1 with the "SLEP" and the "WDTC" commands, or during power up and reset to 0 with WDT timeout.
• Bits 5 (PS0) ~ 6 (PS1) Page select bits. PS0~PS1 are used to pre-select a program memory page. When executing a "JMP", "CALL", or other instructions which causes the program counter to be changed (e.g. MOV R2, A), PS0~PS1 are loaded into the 11th and 12th bits of the program counter where it selects one of the available program memory pages. Note that RET (RETL, RETI) instruction does not change the PS0~PS1 bits. That is, the return will always be to the page from where the subroutine was called, regardless of the current setting of PS0~PS1 bits. PS1 bit is not used (read as "0") and cannot be modified in EM78451.
PS1 PS0 Program memory page [Address]
0 0 Page 0 [000-3FF] 0 1 Page 1 [400-7FF] 1 0 Page 2 [800-BFF] 1 1 Page 3 [C00-FFF]
• Bit 7 (GP) General read/write bit.
5. R4 (RAM Select Register)
• Bits 0~5 are used to select the registers (address: 00~3F) in the indirect addressing mode.
• Bits 6~7 determine which bank is activated among the 4 banks.
• If no indirect addressing is used, the RSR is used as an 8-bit general-purposed read/writer register.
• See the configuration of the data memory in Fig. 4.
6. R5~R8 (Port 5 ~ Port8)
• Four general 8 bits I/O registers
• Both P74 and P76 read or write data from the DATA pin, while both P75 and P77 read or write data from the CLK pin.
7. R9 (Port9)
• A general 6-bit I/O register. The values of the two most significant bits are read as "0".
This specification is subject to change without prior notice. 2002/03/01
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EM78451
MASK ROM
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
10 11
1E 1F
R0 R1 (TCC) R2 (PC) R3 (Status) R4 (RSR) R5 (Port 5) R6 (Port 6) R7 (Port 7) R8 (Port 8) R9 (Port 9) RA RB RC RD RE RF
16x8 Common Register
STACK 0 STACK 1 STACK 2 STACK 3 STACK 4
IOC5 IOC6 IOC7 IOC8 IOC9
IOCC IOCD IOCE IOCF
00 01 10 11 20 21
3E
3F
31x8 Bank
Register
(Bank 0)
R3F
31x8
Bank
Register
(Bank 1)
31x8 Bank
Register
(Bank 2)
31x8 Bank
Register
(Bank 3)
Fig. 4 Data Memory Configuration
This specification is subject to change without prior notice. 2002/03/01
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8. RA (SPIRB: SPI Read Buffer)
EM78451
MASK ROM
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0X0A SPIRB/RA SRB7 SRB6 SRB5 SRB4 SRB3 SRB2 SRB1 SRB0
• SRB7~SRB0 are the 8-bit data when transmission is completed through SPI.
9. RB (SPIWB: SPI Write Buffer)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0B SPIWB/RB SWB7 SWB6 SWB5 SWB4 SWB3 SWB2 SWB1 SWB0
• SWB7~SWB0 are the 8-bit data that wait for transmission through SPI.
10. RC (SPIS: SPI Status Register)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0C SPIS/RC
• TM1IF (bit 4): 1 = In timer1 mode, receiving completed, and an interrupt occurs if enabled. 0 = In timer1 mode, receiving not completed yet, and an interrupt does not occur.
• OD3 (bit 3): Open Drain Control bit 1 = Open-Drain enable for SDO, 0 = Open-Drain disable for SDO.
-- -- -- TM1IF OD3 OD4 RBFIF RBF
• OD4 (bit 2): Open-Drain Control bit 1 = Open-Drain enable for SCK, 0 = Open-Drain disable for SCK.
• RBFIF (bit 1): Read Buffer Full Interrupt flag 1 = Receive is finished, SPIRB is fully exchanged, and an interrupt occur if enable. 0 = Receive is not finish yet; SPIRB is not already fully exchanged.
• RBF (bit 0): Read Buffer Full flag 1 = Receiving completed; SPIRB is fully exchanged. 0 = Receiving not completed yet; and SPIRB has not fully exchanged.
11. RD (SPIC: SPI Control Register)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0D SPIC/RD CES SPIE SRO SSE - SBRS2 SBRS1 SBRS0
• CES (bit 7): Clock Edge Select bit 1 = Data shifts out on falling edge, and shifts in on rising edge. Data is on hold during the high level. 0 = Data shifts out on rising edge, and shifts in on falling edge. Data is on hold during the low level.
• SPIE (bit 6): SPI Enable bit
This specification is subject to change without prior notice. 2002/03/01
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EM78451
MASK ROM
1= Enable SPI mode 0= Disable SPI mode
• SRO (bit 5): SPI Read Overflow bit 1 = A new data is received while the previous data is still being held in the SPIB register. In this situation, the data in SPIS register will be destroyed. To avoid setting this bit, users had better read SPIRB register even if only the transmission is implemented. 0 = No overflow. <Note>: This can only occur in slave mode.
• SSE (bit 4): SPI Shift Enable bit 1 = Start to shift, and keep on 1 while the current byte is still being transmitted. 0 = Reset as soon as the shifting is complete, and the next byte is ready to shift. <Note>: This bit will reset to 0 at every one-byte transmission by the hardware
• SBRS (bit 2~bit 0): SPI Baud Rate Select bits SPI baud rate table is illustrated in the SPI section of this specification.
12. RE (TMR1: Timer1 register)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0X0E TMR1/RE TMR17 TMR16 TMR15 TMR14 TMR13 TMR12 TMR11 TMR10
• TMR17~TMR10 is bit set of timer1 register and it increases until the value matches PWP and then it
resets to 0.
13. RF (PWP: Pulse width preset register)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0F PWP/RF PWP7 PWP6 PWP5 PWP4 PWP3 PWP2 PWP1 PWP0
• PWP7~PWP0 is bit set of pulse width preset in advance for the desired baud clock width.
14. R20~R3E (General Purpose Register)
• RA~R1F, and R20~R3E (including Banks 0~3) are general-purpose registers.
15. R3F (Interrupt Status Register)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x3F ISR/R3F - - - - TM1IF SPIIF EXIF TCIF
• Bit 0 (TCIF) TCC timer overflow interrupt flag. Set as TCC overflow; flag cleared by software.
• Bit 1 (EXIF) External interrupt flag. Set by falling edge on /INT pin, flag cleared by software
• Bit 2 (SPIIF) SPI interrupt flag. Set by completion of data transmission, flag cleared by software.
• Bit 3 (TM1IF) Timer1 interrupt flag. Set by the comparator at Timer1 application, flag cleared by
software.
This specification is subject to change without prior notice. 2002/03/01
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• Bits 2~7 are not used and read as “0”.
• "1" means interrupt request, "0" means non-interrupt.
• R3F can be cleared by instruction, but cannot be set by instruction.
• IOCF is the interrupt mask register.
• Note that to read R3F will result of "logic AND" of R3F and IOCF.
4.2 Special Purpose Registers
1. A (Accumulator)
• Internal data transfer, or instruction operand holding.
• A non-addressable register.
2. CONT (Control Register)
EM78451
MASK ROM
7 6 5 4 3 2 1 0
/PHEN /INT - - PAB PSR2 PSR1 PSR0
• Bit 7 (/PHEN) I/O pin pull-high enable flag. 0: For P60~P67, P74~P75 and P90~P95, the pull-high function is enabled. 1: The pull-high function is disabled.
• Bit 6 (INT) An interrupt enable flag cannot be written by the CONTW instruction. 0: interrupt masked by the DISI instruction. 1: interrupt enabled by the ENI or RETI instruction.
• Bit4, 5 Not used, and to be read as “0”.
• Bit 3 (PAB) Prescaler assignment bit. 0: TCC 1: WDT
• Bit 0 (PSR0) ~ Bit 2 (PSR2) TCC/WDT prescaler bits.
PSR2 PSR1 PSR0 TCC Rate WDT Rate
0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1:16 1:8 1 0 0 1:32 1:16 1 0 1 1:64 1:32 1 1 0 1:128 1:64 1 1 1 1:256 1:128
• Bits 0~3, and 7 of the CONT register are readable and writable.
3. IOC5 ~ IOC9 (I/O Port Control Register)
This specification is subject to change without prior notice. 2002/03/01
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EM78451
MASK ROM
• "1" put the relative I/O pin into high impedance, while "0" put the relative I/O pin as output.
• Both P74 and P76 should not be defined as output pins at the same time, This also applies to both
P75 and P77.
• Only the lower 6 bits of the IOC9 register are used.
4. IOCC (T1CON: Timer1 control register)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0C T1CON/IOCC 0 0 0 0 0 TM1E TM1P1 TM1P0
• TM1E (bit2): Timer1 Function Enable bit 1 = Enable timer1 function. 0 = Disable timer1 function as default.
• TM1P (bit1~bit0): Timer1 Prescaler bit Timer1 prescaler table for FOSC will be illustrated in the Section on Timer1 in later pages.
5. IOCD (Pull-high Control Register)
7 6 5 4 3 2 1 0
S7 - - - /PU9 /PU8 /PU6 /PU5
• The default values of /PU5, /PU6, /PU8, and /PU9 are one which means the pull-high function is
disabled.
• /PU6 and /PU9 are “AND” gating with /PHEN, that is, when each one is written as“0,” pull high is
enabled.
• S7 defines the driving ability of the P70-P72. 0: Normal output. 1: Enhance the driving ability of LED.
6. IOCE (WDT Control Register)
7 6 5 4 3 2 1 0
- ODE WDTE SLPC ROC - - /WUE
• Bit 0 (/WUE) Control bit used to enable the wake-up function of P60~P67, P74~P75, and P90~P91. 0: Enable the wake-up function. 1: Disable the wake-up function. The /WUE bit can be read and written.
• Bit 3 (ROC) ROC is used for the R-option. Setting ROC to "1" will enable the status of R-option pins
(P80, P81) to be read by the controller. Clearing ROC will disable the R-option function. Otherwise, the R-option function is introduced. Users must connect the P81 pin or/and P80 pin to VSS by a
This specification is subject to change without prior notice. 2002/03/01
13
EM78451
MASK ROM
560KΩ external resistor (Rex). If Rex is connected/disconnected with VDD, the status of P80 (P81) will be read as "0"/"1" (refer to Fig. 7(b)). The ROC bit can be read and written.
• Bit 4 (SLPC) This bit is set by hardware at the falling edge of wake-up signal and is cleared in
software. SLPC is used to control the oscillator operation. The oscillator is disabled (oscillator is stopped, and the controller enters the SLEEP2 mode) on the high-to-low transition and is enabled (the controller is awakened from SLEEP2 mode) on low-to-high transition. In order to ensure the stable output of the oscillator, once the oscillator is enabled again, there is a delay for approximately 18 ms (oscillator start-up timer (OST)) before the next program instruction is executed. The OST is always activated by wake-up from sleep mode whether the Code Option bit ENWDT is "0" or not. After waking up, the WDT is enabled if Code Option ENWDT is "1". The block diagram of SLEEP2 mode and wake-up caused by input triggered is depicted in Fig. 5. The SLPC bit can be read and written.
• Bit 5 (WDTE) Control bit used to enable Watchdog timer. The WDTE bit can be used only if ENWDT, the CODE Option bit, is "1". If the ENWDT bit is "1", then WDT can be disabled/enabled by the WDTE bit. 0: Disable WDT. 1: Enable WDT. The WDTE bit is not used if ENWDT, the CODE Option bit ENWDT, is "0". That is, if the ENWDT bit is "0", WDT is always disabled no matter what the WDTE bit is. The WDTE bit can be read and written.
• Bit 6 (ODE) Open-drain control bit. 0: Both P76 and P77 are normally I/O pins. 1: Both P76 and P77 pins have the open-drain function inside. The ODE bit can be read and written.
• Bits 1~2, and 7 Not used.
7. IOCF (Interrupt Mask Register)
7 6 5 4 3 2 1 0
- - - - TM1IE SPIIE EXIE TCIE
• Bit 0 (TCIE) TCIF interrupt enable bit. 0: disable TCIF interrupt 1: enable TCIF interrupt
• Bit 1 (EXIE) EXIF interrupt enable bit. 0: disable EXIF interrupt
This specification is subject to change without prior notice. 2002/03/01
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1: enable EXIF interrupt
P R C
4
8
• Bit 2 (SPIIE) SPI interrupt enable bit. 0: disable SPI interrupt 1: enable SPI interrupt
• Bit 3 (TM1IE) TM1IE interrupt enable bit. 0: disable TM1IE interrupt 1: enable TM1IE interrupt
• Bits 4~7 Not used.
• Individual interrupt is enabled by setting its associated control bit in IOCF to "1".
• The IOCF Register could be read and written.
EM78451
MASK ROM
Oscillator
Enable Disable
Q D
CLK
Q
L
Clear
from S/W
Set
/WUE
/WUE
Reset
VCC
/WUE
P60~P67
VCC
/WUE
/PHEN
P74~P75, P90~P91
Fig. 5 Block Diagram of Sleep Mode and Wake-up Circuits on I/O Ports
This specification is subject to change without prior notice. 2002/03/01
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