EM78447S
MASK ROM
1. GENERAL DESCRIPTION
EM78447S is an 8-bit microprocessor with low-power and high-speed CMOS technology. Integrated into
a single chip are on-chip watchdog timer (WDT), RAM, ROM, real time clock/counter, external and
interrupt, power down mode, and tri-state I/O.
This specification is subject to change without prior notice. 2002/03/01 1
2. FEATURES
• Operating voltage range: 2.3V~5.5V.
• Operating in temperature range: 0°C~70°C.
• Operating frequency range ( base on 2 clocks)
* Crystal mode: DC~20MHz at 5V, DC~8MHz at 3V, DC~4MHz at 2.3V.
* RC mode: DC~4MHz at 5V, DC~4MHz at 3V, DC~4MHz at 2.3V.
• Low power consumption:
* Less then 2.2 mA at 5V/4MHz
EM78447S
MASK ROM
* Typically 30 µA at 3V/32KHz
* Typically 1 µA during sleep mode
• 4K × 13 bits on chip ROM
• One configuration register to accommodate user’s requirements
• 148× 8 bits on chip registers (SRAM, general purpose register)
• 3 bi-directional I/O ports
• 5 level stacks for subroutine nesting
• 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt
• Two clocks per instruction cycle
• Power down (SLEEP) mode
• Two available interruptions
* TCC overflow interrupt
* External interrupt
• Programmable free running watchdog timer
• 10 programmable pull-high pins
• 2 programmable open-drain pins
• 2 programmable R-option pins
• Package types:
* 28 pin DIP 600mil :EM78447SAP
* 28 pin SOP(SOIC) 300mil :EM78447SAM
* 28 pin SSOP 209mil :EM78447SAS
* 32 pin DIP 300mil :EM78447SBP
* 32 pin SOP(SOIC) 450mil :EM78447SBWM
This specification is subject to change without prior notice. 2002/03/01 2
• 99.9% single instruction cycle commands
• The transient point of system frequency between HXT and LXT is around 400KHz
EM78447S
MASK ROM
This specification is subject to change without prior notice. 2002/03/01 3
3. PIN ASSIGNMENT
NC
NC
SOIC
* The real time clock/counter (with Schmitt trigger input pin), must be tied to
* Input pin with Schmitt trigger. If this pin remains at logic low, the controller
EM78447S
MASK ROM
TCC
VDD
VSS
/INT
P50
P51
P52
P53
P60
P61
P62
P63
P64
EM78447SAP
EM78447SAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DIP
SOP
SOIC
/RESET
OSCI
OSCO
P77
P76
P75
P74
P73
P72
P71
P70
P67
P66
P65
VSS
TCC
VDD
/INT
P50
P51
P52
P53
P60
P61
P62
P63
P64
VSS
EM78447SAS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SSOP
/RESET
OSCI
OSCO
P77
P76
P75
P74
P73
P72
P71
P70
P67
P66
P65
Fig. 1 Pin assignment
EM78447SBP
EM78447SBWM
P55
P54
TCC
VDD
VSS
/INT
P50
P51
P52
P53
P60
P61
P62
P63
P64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DIP
SOP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P56
P57
/RESET
OSCI
OSCO
P77
P76
P75
P74
P73
P72
P71
P70
P67
P66
P65
Table 1 EM78447SAP and EM78447SAM Pin Description
Symbol Pin No. Type Function
VDD 2 - * Power supply.
OSCI 27 I
* XTAL type: Crystal input terminal or external clock input pin.
* RC type: RC oscillator input pin.
* XTAL type: Output terminal for crystal oscillator or external clock input
OSCO 26 I/O
pin.
* RC type: Instruction clock output.
* External clock signal input.
TCC 1 I
/RESET 28 I
P50~P53 6~9 I/O * P50~P53 are bi-directional I/O pins.
P60~P67 10~17 I/O
VDD or VSS if not in use.
will also remain in reset condition.
* P60~P67 are bi-directional I/O pins. These can be pulled-high internally
by software control.
* P70~P77 are bi-directional I/O pins.
P70~P77 18~25 I/O
* P74~P75 can be pulled-high internally by software control.
* P76~P77 can have open-drain output by software control.
* P70 and P71 can also be defined as the R-option pins.
This specification is subject to change without prior notice. 2002/03/01 4
/INT 5 I * External interrupt pin triggered by falling edge.
* The real time clock/counter (with Schmitt trigger input pin), must be tied to
* Input pin with Schmitt trigger. If this pin remains at logic low, the controller
VSS 4 - * Ground.
NC 3 - * No connection.
Table 2 EM78447SAS Pin Description
Symbol Pin No. Type Function
VDD 3 - * Power supply.
OSCI 27 I
OSCO 26 I/O
* XTAL type: Crystal input terminal or external clock input pin.
* RC type: RC oscillator input pin.
* XTAL type: Output terminal for crystal oscillator or external clock input
pin.
* RC type: Instruction clock output.
* External clock signal input.
EM78447S
MASK ROM
TCC 2 I
/RESET 28 I
P50~P53 5~8 I/O * P50~P53 are bi-directional I/O pins.
P60~P67
P70~P77 18~25 I/O
/INT 4 I * External interrupt pin triggered by falling edge.
VSS 1,14 - * Ground.
Table 3 EM78447SBP and EM78447SBWM Pin Description
Symbol Pin No. Type Function
VDD 4 - * Power supply.
OSCI 29 I
OSCO 28 I/O
TCC 3 I
/RESET 30 I
P50~P57
P60~P67 12~19 I/O
P70~P77 20~27 I/O
/INT 7 I * External interrupt pin triggered by falling edge.
VSS 6 - * Ground.
NC 5 - * No connection.
9~13,
15~17
8~11,2~1,
32~31
I/O
VDD or VSS if not in use.
will also remain in reset condition.
* P60~P67 are bi-directional I/O pins. These can be pulled-high internally
by software control.
* P70~P77 are bi-directional I/O pins.
* P74~P75 can be pulled-high internally by software control.
* P76~P77 can have open-drain output by software control.
* P70 and P71 can also be defined as the R-option pins.
* XTAL type: Crystal input terminal or external clock input pin.
* RC type: RC oscillator input pin.
* XTAL type: Output terminal for crystal oscillator or external clock input
pin.
* RC type: Instruction clock output.
* External clock signal input.
* The real time clock/counter (with Schmitt trigger input pin), must be tied
to VDD or VSS if not in use.
* Input pin with Schmitt trigger. If this pin remains at logic low, the
controller will also remain in reset condition.
I/O * P50~P57 are bi-directional I/O pins.
* P60~P67 are bi-directional I/O pins. These can be pulled-high internally
by software control.
* P70~P77 are bi-directional I/O pins.
* P74~P75 can be pulled -high internally by software control.
* P76~P77 can have open-drain output by software control.
* P70 and P71 can also be defined as the R-option pins.
This specification is subject to change without prior notice. 2002/03/01 5
4. FUNCTION DESCRIPTION
EM78447S
MASK ROM
OSCI OSCO /RESET
Oscillator/Timing
Control
WDT
Time- out
Prescale
R1(TCC)
Sleep
&
Wake-up
Control
IOC5
R5
P
P
P
P
P
P
P
P
5
5
5
5
5
5
5
5
0
1
2
3
4
5
6
7
r
WDT Timer
RAM
R4
/INTTCC
Interrupt
Control
DATA & CONTROL BUS
IOC6
R6
P
P
P
P
P
P
P
P
6
6
6
6
6
6
6
6
0
1
2
3
4
5
6
7
ROM
Instruction
Register
Instruction
Decoder
P C
P
7
0
P
P
7
7
1
2
R3
IOC7
R7
P
P
P
7
7
7
3
4
5
STACK 1
STACK 2
STACK 3
STACK 4
STACK 5
ALU
ACC
P
P
7
7
6
7
Fig. 2 Functional block diagram
4.1 Operational Registers
1. R0 (Indirect Addressing Register)
R0 is not a physically implemented register. Its major function is as indirect addressing pointer. Any
instruction using R0 as a pointer actually accesses data pointed by the RAM Select Register (R4).
2. R1 (Time Clock /Counter)
• Increased by an external signal edge, which is defined by TE bit (CONT-4) through the TCC pin, or
by the instruction cycle clock.
• Writable and readable as any other registers.
• Defined by resetting PAB (CONT-3).
• The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset.
This specification is subject to change without prior notice. 2002/03/01 6
EM78447S
MASK ROM
• The contents of the prescaler counter will be cleared only when TCC register is written with a value.
3. R2 (Program Counter) & Stack
• Depending on the device type, R2 and hardware stack are 10-bit wide. The structure is depicted in
Fig.3.
• Generating 1024×13 bits on-chip ROM addresses to the relative programming instruction codes.
One program page is 1024 words long.
• R2 is set as all "0"s when under RESET condition.
• "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC
to go to any location within a page.
• "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus,
the subroutine entry address can be located anywhere within a page.
• "RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the top-level
stack.
• "ADD R2,A" allows the contents of ‘A’ to be added to the current PC, and the ninth and tenth bits of
the PC are cleared.
• "MOV R2,A" allows to load an address from the "A" register to the lower 8 bits of the PC, and the
ninth and tenth bits of the PC are cleared.
• Any instruction that writes to R2 (e.g. "ADD R2,A", "MOV R2,A", "BC R2,6",⋅⋅⋅⋅⋅) will cause the ninth
and tenth bits (A8~A9) of the PC to be cleared. Thus, the computed jump is limited to the first 256
locations of a page.
• All instruction are single instruction cycle (fclk/2 or fclk/4) except for the instruction that would
change the contents of R2. Such instruction will need one more instruction cycle.
PC A11A10 A9A8 A7 ~ A0
00
01
10
11
000
3FF
400
7FF
800
BFF
C00
FFF
Page 0
Page 1
Page 2
Page 3
CALL
RET
RETL
RETI
001:Hareware in terrupt location
002:Software interrupt (INT instruction)
location
FFF:Reset location
Stack 1
Stack 2
Stack 3
Stack 4
Stack 5
Fig. 3 Program Counter Organization
This specification is subject to change without prior notice. 2002/03/01 7
EM78447S
MASK ROM
4. R3 (Status Register)
7 6 5 4 3 2 1 0
GP PS1 PS0 T P Z DC C
• Bit 0 (C) Carry flag
• Bit 1 (DC) Auxiliary carry flag
• Bit 2 (Z) Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero.
• Bit 3 (P) Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a
"SLEP" command.
• Bit 4 (T) Time-out bit. Set to 1 with the "SLEP" and "WDTC" commands, or during power up and
reset to 0 by WDT timeout.
• Bits 5 (PS0) ~ 6 (PS1) Page select bits. PS0~PS1 are used to pre-select a program memory page.
When executing a "JMP", "CALL", or other instructions which causes the program counter to
change (e.g. MOV R2, A), PS0~PS1 are loaded into the 11th and 12th bits of the program counter
where it selects one of the available program memory pages. Note that RET (RETL, RETI)
instruction does not change the PS0~PS1 bits. That is, the return will always be to the page from
where the subroutine was called, regardless of the current setting of PS0~PS1 bits.
PS1 PS0 Program memory page [Address]
0 0 Page 0 [000-3FF]
0 1 Page 1 [400-7FF]
1 0 Page 2 [800-BFF]
1 1 Page 3 [C00-FFF]
• Bit 7 (GP) General read/write bit.
5. R4 (RAM Select Register)
• Bits 0~5 are used to select the registers (address: 00~3F) in the indirect addressing mode.
• Bits 6~7 determine which bank is activated among the 4 banks.
• If no indirect addressing is used, the RSR is used as an 8-bit general-purposed read/writer register.
• See the configuration of the data memory in Fig. 4.
6. R5~R7 (Port 5 ~ Port7)
• R5, R6 and R7 are I/O registers
7. R8~R1F and R20~R3E (General-Purpose Register)
• R8~R1F, and R20~R3E (including Banks 0~3) are general-purpose registers.
8. R3F (Interrupt Status Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
- - - - EXIF - - TCIF
• Bit 0 (TCIF) TCC overflow interrupt flag. Set as TCC overflows; flag cleared by software.
This specification is subject to change without prior notice. 2002/03/01 8
EM78447S
04 05 06 07 08 09 0A 0B
0E 0F 10
20
3F
01
MASK ROM
• Bit 3(EXIF) External interrupt flag. Set by falling edge on /INT pin, flag cleared by software
• Bits 1,2,4~7 are not used and read as “0”.
• "1" means interrupt request, "0" means non-interrupt.
• R3F can be cleared by instruction, but cannot be set by instruction.
• IOCF is the interrupt mask register.
• Note that to read R3F will obtain the result of "logic AND" of R3F and IOCF.
00
01
02
03
R0
R1(TCC)
R2(PC)
R3(Status)
R4(RSR)
Stack
(5 level)
0C
0D
1F
R5(Port5)
R6(Port6)
R7(Port7)
IOC5
IOC6
IOC7
R8
R9
RA
RB
IOCB
RC
RD
RE
RF
:
:
16x8
Common
Register
00
10 11
IOCE
IOCF
:
:
31x8
Bank
Register
(Bank 0)
31x8
Bank
Register
(Bank 1)
31x8
Bank
Register
(Bank 2)
31x8
Bank
Register
(Bank 3)
3E
R3F
Fig. 4 Data Memory Configuration
This specification is subject to change without prior notice. 2002/03/01 9
9. R20~R3E (General-Purpose Register)
• RA~R1F, and R20~R3E (including Banks 0~3) are general-purpose registers.
10. R3F (Interrupt Status Register)
7 6 5 4 3 2 1 0
- - - - EXIF - TCIF
“1” means interrupt request, and “0” means no interrupt occur.
• Bit 0 (TCIF) TCC overflow interrupt flag. Set when TCC overflows, reset by software.
• Bit 3 (EXIF) External interrupt flag. Set by falling edge on /INT pin, reset by software.
• Bits 1, 2 and 3 ~ 7 Not used.
• R3F can be cleared by instruction but cannot be set.
• IOCF is the interrupt mask register.
EM78447S
MASK ROM
• Note that the result of reading R3F is the "logic AND" of R3F and IOCF.
4.2 Special Purpose Registers
1. A (Accumulator)
• Internal data transfer, or instruction operand holding.
• It can not be addressed.
2. CONT (Control Register)
7 6 5 4 3 2 1 0
/PHEN /INT TS TE PAB PSR2 PSR1 PSR0
• Bit 0 (PSR0) ~ Bit 2 (PSR2) TCC/WDT prescaler bits.
PSR2 PSR1 PSR0 TCC Rate WDT Rate
0 0 0 1:2 1:1
0 0 1 1:4 1:2
0 1 0 1:8 1:4
0 1 1 1:16 1:8
1 0 0 1:32 1:16
1 0 1 1:64 1:32
1 1 0 1:128 1:64
1 1 1 1:256 1:128
• Bit 3 (PAB) Prescaler assignment bit.
0: TCC
1: WDT
• Bit 4 (TE) TCC signal edge
0: increment if the transition from low to high takes place on TCC pin
1: increment if the transition from high to low takes place on TCC pin
This specification is subject to change without prior notice. 2002/03/01 10
• Bit 5 (TS) TCC signal source
0: internal instruction cycle clock
1: transition on TCC pin
• Bit 6 (/INT) Interrupt enable flag
0: masked by DISI or hardware interrupt
1: enabled by ENI/RETI instructions
• Bit 7 (/PHEN) Control bit used to enable the pull-high of P60~P67, P74 and P75 pins
0: Enable internal pull-high.
1: Disable internal pull-high.
• CONT register is both readable and writable.
3. IOC5 ~ IOC7 (I/O Port Control Register)
EM78447S
MASK ROM
• "1" put the relative I/O pin into high impedance, while "0" defines the relative I/O pin as output.
• IOC5 and IOC7 registers are both readable and writable.
4. IOCB (Wake-up Control Register for Port 6)
7 6 5 4 3 2 1 0
/WUE7 /WUE6 /WUE5 /WUE4 /WUE3 /WUE2 /WUE1 /WUE0
• Bit 0 (/WUE0) Control bit used to enable the wake-up function of P60 pin.
0: Enable internal wake-up.
1: Disable internal wake-up.
• Bit 1 (/WUE1) Control bit is used to enable the wake-up function of P61 pin.
• Bit 2 (/WUE2) Control bit is used to enable the wake-up function of P62 pin.
• Bit 3 (/WUE3) Control bit is used to enable the wake-up function of P63 pin.
• Bit 4 (/WUE4) Control bit is used to enable the wake-up function of P64 pin.
• Bit 5 (/WUE5) Control bit is used to enable the wake-up function of P65 pin.
• Bit 6 (/WUE6) Control bit is used to enable the wake-up function of P66 pin.
• Bit 7 (/WUE7) Control bit is used to enable the wake-up function of P67 pin.
• IOCB Register is both readable and writable.
6. IOCE (WDT Control Register)
7 6 5 4 3 2 1 0
- ODE WDTE SLPC ROC - - /WUE
• Bit 0 (/WUE) Control bit used to enable the wake-up function of P74 and P75.
0: Enable the wake-up function.
1: Disable the wake-up function.
The /WUE bit can be read and written.
This specification is subject to change without prior notice. 2002/03/01 11
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