ELAN EM73P461A Datasheet

GENERAL DESCRIPTIONGENERAL DESCRIPTION

GENERAL DESCRIPTION

GENERAL DESCRIPTIONGENERAL DESCRIPTION

EM73P461A is an advanced single chip CMOS 4-bit one-time programming (OTP) micro-controller. It contains
4K/8K-byte ROM, 244-nibble RAM, 4-bit ALU, 13-level subroutine nesting, 22-stage time base, two 12-bit timer/
counters for the kernel function. EM73P461A also contains 6 interrupt sources, 1 input port, 2 bidirection ports,
LCD display (32x4), and one high speed timer/counter with melody output.
EM73P461A has plentiful operating modes (SLOW, IDLE, STOP) intended to reduce the power consumption.

FEATURESFEATURES

FEATURES

FEATURESFEATURES

• Operation voltage : 2.4V to 3.6V.

• Clock source : Dual clock system. Low-frequency oscillator is Crystal or RC oscillator (32K Hz,

• Instruction set : 109 powerful instructions for 4K ROM / 107 powerful instructoins for 8K ROM.

• Instruction cycle time : Up to 2us for 4 MHz (high speed clock).

• ROM capacity : 4096 X 8 bits / 8192 X 8 bits ROM are choosed by mask option.

• RAM capacity : 244 X 4 bits.

• Input port : 1 port (P0). P0(0..3) and IDLE releasing function are available by mask option.

• Bidirection port : 2 ports (P4, P8). P4.0 and SOUND is available by mask option. P4.1 is shared with

• 12-bit timer/counter : Two 12-bit timer/counters are programmable for timer, event counter and pulse width

• High speed timer/counter : One 8-bit high speed timer/counters is programmable for auto load timer, melody

• Built-in time base counter : 22 stages.

• Subroutine nesting : Up to 13 levels.

• Interrupt : External . . . . . 2 input interrupt sources.

• LCD driver : 32 X 4 dots, 1/4duty, 1/3duty, 1/2duty, static, 1/2 bias, 1/3 bias; 6 options selectable.

• Power saving function : SLOW, IDLE, STOP operation mode.

• Package type : Chip form 61 pins.

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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

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connect an external resistor) by mask option and high-frequency oscillator is RC
oscillator (connect an external resistor).

122 µs or 244µs by frequency double mask option for 32768 Hz (low speed clock).

HTC external input. P8(0..3) and IDLE releasing function are available by mask
option.

measurement.

output and pulse width measurement.

Internal . . . . . . 2 Timer overflow interrupts, 1 time base interrupt.

1 high speed timer overflow interrupt.

QFP 100 pins.
PDIP 42 pins.

APPLICATIONSAPPLICATIONS

APPLICATIONS

APPLICATIONSAPPLICATIONS

EM73P461A is suitable for application in family applicance, consumer products, hand held games and the toy
controller.

* This specification are subject to be changed without notice.

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PIN ASSIGNMENTPIN ASSIGNMENT

PIN ASSIGNMENT

PIN ASSIGNMENTPIN ASSIGNMENT

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NCNCNCNCNCNCNCNCNC

8079787776757473727170696867666564636261605958575655545352

81

NC

82

NC

83

SEG5

84

SEG4

85

SEG3

86

SEG2

87

SEG1

88

SEG0

89

COM3

90

COM2

91

COM1

92

COM0

93

VB

94

VA

95

V3

96

V2

97

V1

98

NC

99

NC

100

NC

123456789

NCNCNC

NC

VSS

FUNCTION BLOCK DIAGRAMFUNCTION BLOCK DIAGRAM

FUNCTION BLOCK DIAGRAM

FUNCTION BLOCK DIAGRAMFUNCTION BLOCK DIAGRAM

RESET

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

EM73P461A

QFP 100

101112131415161718192021222324252627282930

NC

P4.3

P4.2

P4.1

VDD

CLK

P4.0

SOUND

LXOUT

CLK

LXIN

LXOUT

SEG12

SEG13

P8.3

SEG14

SEG15

SEG16

SEG17

NCNCNCNCNCNCNCNCNC

P8.2

P8.1

P8.0

RESET

LXIN

SEG18

SEG19

SEG20

SEG21NCNCNCNC

NC

51

50

NC

49

NC

48

NC

47

SEG22

46

SEG23

45

SEG24

44

SEG25

43

SEG26

42

SEG27

41

SEG28

40

SEG29

39

SEG30

38

SEG31

37

P0.0

36

P0.1

35

P0.2

34

P0.3

33

VPP

32

NC

31

NC

NC

LXOUT

VSS

CLK

LXIN

VDD

P4.3
P4.2
P4.1
P4.0
P8.3
P8.2
P8.1
P8.0

RESET

VPP
P0.3
P0.2
P0.1

1

V3

2

V2

3

V1

4
5
6
7
8
9
10

EM73P461A

11

PDIP42

12
13
14
15
16
17
18
19

20
21

VA

42

VB

41

COM0

40

COM1

39

COM2

38

COM3

37

SEG14

36

SEG15

35

SEG16

34

SEG17

33

SEG18

32

SEG19

31

SEG20

30

SEG21

29

SEG22

28

SEG23

27

SEG24

26

SEG25

25

SEG26

24

SEG27

23

P0.0

22

VA
VB

V1
V2
V3

Reset

Control

Interrupt

Control

Time
Base

LCD

COM0~COM3

Generator

Instruction Decoder
Instruction Register

Timer/Counter

(TA,TB)

SEG0~SEG31

Clock

ROM

PC
DP
SP

HTC

SOUND

Clock

Generator

(slow)

System Control

Data Bus

Timing

Generator

Data pointer

ACC

ALU

Flag

ZCS G

I/O Control

P4.2

P4.1TRGH

P4.0/SOUND

Sleep Mode

Control

Stack pointer

Stack

ROM

HR

LR

P4.3

P8.2(INT0)/WAKEUPC

P8.0(INT1)/WAKEUPA

P8.1(TRGB)/WAKEUPB

P8.3(TRGA)/WAKEUPD

P0.0/WAKEUP0
P0.1/WAKEUP1
P0.2/WAKEUP2
P0.3/WAKEUP3

* This specification are subject to be changed without notice.

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PIN DESCRIPTIONSPIN DESCRIPTIONS

PIN DESCRIPTIONS

PIN DESCRIPTIONSPIN DESCRIPTIONS

SymbolSymbol

Symbol

SymbolSymbol

V

DD

V

SS

RESET RESET-A System reset input signal, low active

CLK OSC-I RC clock source connecting pin
LXIN OSC-B/OSC-H1Crystal/RC connecting pin for low speed clock source
LXOUT OSC-B Crystal connecting pin for low speed clock source
P0(0..3)/WAKEUP0..3 INPUT-K 4-bit input port with IDLE releasing function

P4.0/SOUND I/O-R 1-bit bidirection I/O port or inverse sound effect output

P4.1/TRGH I/O-Q 1-bit bidirection I/O port with HTC external input

P4(2,3) I/O-Q 2-bit bidirection I/O port with high current source

Pin-typePin-type

Pin-type

Pin-typePin-type

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FunctionFunction

Function

FunctionFunction

Power supply (+)
Power supply (+) for programming OTP
Power supply (-)
Power supply (-) for programming OTP

Reset input signal for programming OTP
Always internal pull-up

P0.0/ACLK : address counter clock for programming OTP
P0.1/PGMB : program data to OTP cells for programming OTP
P0.2/OEB : data output enable for programming OTP
P0.3/DCLK : data in/out clock signal for programming OTP
mask option : wakeup enable, negative edge release, pull-up

wakeup enable, negative edge release, none
wakeup enable, positive edge release, pull-down
wakeup enable, positive edge release, none
wakeup disable, pull-up
wakeup disable, pull-down
wakeup disable, none

mask option : SOUND enable, high current push-pull

SOUND disable, open-drain
SOUND disable, low current push-pull
SOUND disable, normal current push-pull
SOUND disable, high current push-pull

mask option : NMOS open-drain

PMOS open-drain
low current push-pull
normal current push-pull
high current push-pull

mask option : NMOS open-drain

PMOS open-drain
low current push-pull
normal current push-pull
high current push-pull

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* This specification are subject to be changed without notice.

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PIN DESCRIPTIONSPIN DESCRIPTIONS

PIN DESCRIPTIONS

PIN DESCRIPTIONSPIN DESCRIPTIONS

SymbolSymbol

Symbol

SymbolSymbol

P8.0(INT1) I/O-S 2-bit bidirection I/O port with external interrupt source input and IDLE
/WAKEUPA/DIN, releasing function

P8.2(INT0)/WAKEUPC P8.0/DIN : data input for programming OTP

P8.1(TRGB) I/O-S 2-bit bidirection I/O port with time/counter A,B external input and IDLE
/WAKEUPB/DOUT, releasing function
P8.3(TRGA) P8.1/DOUT : data output for programming OTP
/WAKEUPD mask option : wakeup enable, low current push-pull

SOUND Melody output
VA,VB, V1, V2, V3 Connect the capacitors for LCD bias voltage
COM0~COM3 LCD common output pins
SEG0~SEG31 LCD segment output pins
TEST/VPP Test pin must be floating

Pin-type Pin-type

Pin-type

Pin-type Pin-type

FunctionFunction

Function

FunctionFunction

mask option : wakeup enable, low current push-pull

wakeup enable, normal current push-pull
wakeup disable, open-drain
wakeup disable, low current push-pull
wakeup disable, normal current push-pull

wakeup enable, normal current push-pull
wakeup disable, open-drain
wakeup disable, low current push-pull
wakeup disable, normal current push-pull

VPP : high vlotage (12V) power source for programming OTP

FUNCTION DESCRIPTIONSFUNCTION DESCRIPTIONS

FUNCTION DESCRIPTIONS

FUNCTION DESCRIPTIONSFUNCTION DESCRIPTIONS

PROGRAM ROM (4K X 8 bits)PROGRAM ROM (4K X 8 bits)

PROGRAM ROM (4K X 8 bits)

PROGRAM ROM (4K X 8 bits)PROGRAM ROM (4K X 8 bits)

4 K x 8 bits program ROM contains user's program and some fixed data.
The basic structure of program ROM can be divided into 5 parts.

1. Address 000h: Reset start address.

2. Address 002h - 00Ch : 6 kinds of interrupt service routine entry addresses.

3. Address 00Eh-086h : SCALL subroutine entry address, only available at 00Eh,016h,01Eh,026h, 02Eh,
036h, 03Eh, 046h, 04Eh, 056h, 05Eh, 066h, 06Eh, 076h, 07Eh, 086h.

4. Address 000h - 7FFh : LCALL subroutine entry address.

5. Address 000h - FFFh : Except used as above function, the other region can be used as user's program region.

* This specification are subject to be changed without notice.

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address 4096 x 8 bits

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000h Reset start address
002h INT0; External interrupt service routine entry address
004h HTCI; High speed timer interrupt service entry address
006h TRGA; Timer/counterA interrupt service routine entry address
008h TRGB; Timer/counter B interrupt service routine entry address
00Ah TBI; Time base interrupt service routine entry address
00Ch INT1; External interrupt service routine entry address
00Eh
086h

.

.

.

SCALL, subroutine call entry address

.

.

.

FFFh

User's program and fixed data are stored in the program ROM. User's program is according the PC value
to send next executed instruction code. Fixed data can be read out by two ways.

(1) Table-look-up instruction :

Table -look-up instruction is depended on the Data Pointer (DP) to indicate to ROM address, then to get the
ROM code data.

LDAXLDAX

LDAX

LDAXLDAX
LDAXILDAXI

LDAXI

LDAXILDAXI

Acc Acc

Acc

Acc Acc
Acc Acc

Acc

Acc Acc

←←

ROM[DP] ROM[DP]

←

ROM[DP]

←←

ROM[DP] ROM[DP]

←←

ROM[DP] ROM[DP]

←

ROM[DP]

←←

ROM[DP] ROM[DP]

LL

L

LL

,DP+1,DP+1

,DP+1

,DP+1,DP+1

HH

H

HH

DP is a 12-bit data register which can store the program ROM address to be the pointer for the ROM code
data. First, user load ROM address into DP by instruction "STADPL, STADPM, STADPH", then user can

get the lower nibble of ROM code data by instruction "LDAX" and higher nibble by instruction "LDAXI".

PROGRAM EXAMPLE: Read out the ROM code of address 777h by table-look-up instruction.

LDIA #07h;
STADPL ; DP3-0 ← 07h
STADPM ; DP5-4 ← 07h
STADPH ; DP8-6 ← 07h, Load DP=0777h
:
LDL #00h;
LDH #03h;
LDAX ; ACC ← 6h
STAMI ; RAM[30] ← 6h
LDAXI ; ACC ← 5h
STAM ; RAM[31] ← 5h
:
ORG 0777h;
DATA 56h;
:

* This specification are subject to be changed without notice.

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PROGRAM ROM (8K X 8 bits)PROGRAM ROM (8K X 8 bits)

PROGRAM ROM (8K X 8 bits)

PROGRAM ROM (8K X 8 bits)PROGRAM ROM (8K X 8 bits)

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8 K x 8 bits program ROM contains user's program and some fixed data .
The basic structure of program ROM can be divided into 6 parts.

1. Address 0000h: Reset start address.

2. Address 0002h - 000Ch : 6 kinds of interrupt service routine entry addresses .

3. Address 000Eh - 0086h : SCALL subroutine entry address, only available at 000Eh, 0016h, 001Eh, 0026h, 002Eh,
0036h, 003Eh, 0046h, 004Eh, 0056h, 005Eh, 0066h, 006Eh, 0076h, 007Eh, 0086h.

4. Address 0000h - 07FFh : LCALL subroutine entry address.

5. Address 0000h - 1FFFh : Except used as above function, the other region can be used as user's program region.

6. Address 1000h - 1FFFh : Fixed data stortage area.

address 8192 x 8 bits
000h Reset start address
002h INT0; External interrupt service routine entry address
004h HTCI; High speed timer interrupt service entry address
006h TRGA; Timer/counterA interrupt service routine entry address
008h TRGB; Timer/counter B interrupt service routine entry address LCALL entry address
00Ah TBI; Time base interrupt service routine entry address
00Ch INT1; External interrupt service routine entry address
00Eh
086h

SCALL, subroutine call entry address

800h 1000h

::
FFFh Bank 1 fixed data area
1FFFh

User's program and fixed data are stored in the program ROM. User's program is according the PC value
to send next executed instruction code. Fixed data can be read out by table-look-up instruction.
Please note that fixed data only can be stored in 8K ROM Bank 1.
The program counter is a 13-bit binary counter. The PC can defined 8K ROM.

Table-look-up instruction :

Table -look-up instruction is depended on the Data Pointer (DP) to indicate to ROM address, then to get the
ROM code data.

LDAXLDAX

LDAX

LDAXLDAX
LDAXILDAXI

LDAXI

LDAXILDAXI

Acc Acc

Acc

Acc Acc
Acc Acc

Acc

Acc Acc

←←

ROM[DP] ROM[DP]

←

ROM[DP]

←←

ROM[DP] ROM[DP]

←←

ROM[DP] ROM[DP]

←

ROM[DP]

←←

ROM[DP] ROM[DP]

LL

L

LL

,DP+1,DP+1

,DP+1

,DP+1,DP+1

HH

H

HH

DP is a 13-bit data register which can store the program ROM address to be the pointer for the ROM code
data. First, user load ROM address into DP by instruction "STADPL, STADPM, STADPH", then user can
get the lower nibble of ROM code data by instruction "LDAX" and higher nibble by instruction "LDAXI".

* This specification are subject to be changed without notice.

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PROGRAM EXAMPLE: Read out the ROM code of address 1777h by table-look-up instruction for 8K ROM.

LDIA #07h;
STADPL ; DP3-0 ← 07h
STADPM ; DP5-4 ← 07h
STADPH ; DP8-6 ← 07h, Load DP=1777h
:
LDL #00h;
LDH #03h;
LDAX ; ACC ← 6h
STAMI ; RAM[30] ← 6h
LDAXI ; ACC ← 5h
STAM ; RAM[31] ← 5h
:
BANK 1
ORG 1777h
DATA 56h;
:

DATA RAM ( 244-nibble ) DATA RAM ( 244-nibble )

DATA RAM ( 244-nibble )

DATA RAM ( 244-nibble ) DATA RAM ( 244-nibble )

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There is total 244 - nibble data RAM from address 00 to F3h
Data RAM includes 3 parts: zero page region, stacks and data area.

Increment

Address

00h~0Fh

zero page

10h~1Fh
20h~2Fh
30h~3Fh

LCD display RAM

40h~4Fh

:
B0h ~ BFh
C0h ~ CFh
D0h ~ DFh
E0h ~ EFh

F0h ~ F3h

level 0
level 4
level 8

level C

level 1
level 5
level 9

level 2
level 6

level A

level 3
level17
level B

* This specification are subject to be changed without notice.

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LCD display RAM:

RAM address from 20h ~ 3Fh are the LCD display RAM area, the RAM data of this region can't be operated
by instruction LDHL xx and EXHL.

ZERO-PAGE:

From 00h to 0Fh is the location of zero-page. It is used as the pointer in zero-page addressing mode for the
instruction of "STD #k,y; ADD #k,y; CLR y,b; CMP k,y".

PROGRAM EXAMPLE: To wirte immediate data "07h" to address "03h" of RAM and to clear bit 2 of RAM.

STD #07h, 03h ; RAM[03] ← 07h
CLR 0Eh,2 ; RAM[0Eh]2 ← 0

STACK:

There are 13-level (maximum) stack for user using for subroutine (including interrupt and CALL). User can
assign any level be the starting stack by giving the level number to stack pointer (SP).
When user using any instruction of CALL or subroutine, before entry the subroutine, the previous PC address
will be saved into stack until return from those subroutines, the PC value will be restored by the data saved
in stack.

DATA AREA:

Except the special area used by user, the whole RAM can be used as data area for storing and loading general
data.

ADDRESSING MODE

(1) Indirect addressing mode:

Indirect addressing mode indicates the RAM address by specified HL register.
For example: LDAM ; Acc ← RAM[HL]

STAM ; RAM[HL] ← Acc

(2) Direct addressing mode:

Direct addressing mode indicates the RAM address by immediate data.
For example: LDA x ; Acc← RAM[x]

STA x ; RAM[x] ← Acc

(3) Zero-page addressing mode

For zero-page region, user can using direct addressing to write or do any arithematic, comparsion or bit
manupulated operation directly.
For example: STD #k,y ; RAM[y] ← #k

ADD #k,y; RAM[y] ← RAM[y] + #k

* This specification are subject to be changed without notice.

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PROGRAM COUNTER (4K/8K ROM)PROGRAM COUNTER (4K/8K ROM)

PROGRAM COUNTER (4K/8K ROM)

PROGRAM COUNTER (4K/8K ROM)PROGRAM COUNTER (4K/8K ROM)

Program counter ( PC ) is composed by a 12-bit counter for 4K ROM/13-bit counter for 8K ROM which indicates
the next executed address for the instruction of program ROM.
For a 4K - byte size ROM, PC can indicate address form 000h - FFFh, for BRANCH and CALL instrcutions,
PC is changed by instruction indicating.
For a 8K - byte size ROM, PC can indicate address form 0000h - 1FFFh, for BRANCH and CALL instrcutions,
PC is changed by instruction indicating.

(1) Branch instruction:(1) Branch instruction:

(1) Branch instruction:

(1) Branch instruction:(1) Branch instruction:

SBR aSBR a

SBR a

SBR aSBR a

Object code: 00aa aaaa
Condition: SF=1; PC ← PC

PC Hold original PC value+1 aaaaaa (for 4K/8K ROM)

SF=0; PC ← PC +1( branch condition not satisified )

( branch condition satisified )

11-6.a

PC Original PC value + 1

LBR aLBR a

LBR a

LBR aLBR a

Object code: 1100 aaaa aaaa aaaa
Condition: SF=1; PC ← a ( branch condition satisified )

PC aaaaaaaaaaa a (for 4K/8K ROM)

SF=0 ; PC ← PC + 2 ( branch condition not satisified )

PC Original PC value + 2

SLBR aSLBR a

SLBR a

SLBR aSLBR a

Object code: 0101 0101 1100 aaaa aaaa aaaa (a : 1000 ~ 1FFFh)

0101 0111 1100 aaaa aaaa aaaa (a : 0000 ~ 0FFFh)

Condition: SF=1; PC ← a ( branch condition satisified )

PC aaaaaaaaaaa a (only for 8K ROM)

SF=0 ; PC ← PC + 2 ( branch condition not satisified )

PC Original PC value + 2

* This specification are subject to be changed without notice.

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(2) Subroutine instruction:(2) Subroutine instruction:

(2) Subroutine instruction:

(2) Subroutine instruction:(2) Subroutine instruction:

SCALL aSCALL a

SCALL a

SCALL aSCALL a

Object code: 1110 nnnn
Condition : PC ← a ; a=8n+6 ; n=1..15 ; a=86h, n=0

PC0000aaaaaaaa

LCALL aLCALL a

LCALL a

LCALL aLCALL a

Object code: 0100 0 aaa aaaa aaaa
Condition: PC ← a

PC0aaaaaaaaaaa

RETRET

RET

RETRET

Object code: 0100 1111
Condition: PC ← STACK[SP]; SP + 1

P C The return address stored in stack (for 4K ROM)

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P C The return address stored in stack (for 8K ROM)

RT IRT I

RT I

RT IRT I

Object code: 0100 1101
Condition : FLAG. PC ← STACK[SP]; EI ← 1; SP + 1

P C The return address stored in stack (for 4K ROM)

P C The return address stored in stack (for 8K ROM)

(3) Interrupt acceptance operation:(3) Interrupt acceptance operation:

(3) Interrupt acceptance operation:

(3) Interrupt acceptance operation:(3) Interrupt acceptance operation:

When an interrupt is accepted, the original PC is pushed into stack and interrupt vector will be loaded into
PC,The interrupt vectors are as following:

INT0INT0

INT0 (External interrupt from P8.2)

INT0INT0

PC000000000010 (for 4K ROM)

PC000000000001 0 (for 8K ROM)

TRGATRGA

TRGA (Timer A overflow interrupt)

TRGATRGA

PC000000000110 (for 4K ROM)

PC000000000011 0 (for 8K ROM)

* This specification are subject to be changed without notice.

12.27.2001

10

TRGBTRGB

TRGB (Time B overflow interrupt)

TRGBTRGB

PC000000001000 (for 4K ROM)

PC000000000100 0 (for 8K ROM)

TBITBI

TBI (Time base interrupt)

TBITBI

PC000000001010 (for 4K ROM)

PC000000000101 0 (for 8K ROM)

INT1INT1

INT1 (External interrupt from P8.0)

INT1INT1

PC000000001100 (for 4K ROM)

EM73P461AEM73P461A

EM73P461A

EM73P461AEM73P461A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

PreliminaryPreliminary

Preliminary

PreliminaryPreliminary

PC000000000110 0 (for 8K ROM)

(4) Reset operation:(4) Reset operation:

(4) Reset operation:

(4) Reset operation:(4) Reset operation:

PC000000000000 (for 4K ROM)

PC000000000000 0 (for 8K ROM)

(5) Other operations:(5) Other operations:

(5) Other operations:

(5) Other operations:(5) Other operations:

For 1-byte instruction execution: PC + 1
For 2-byte instruction execution: PC + 2

ACCUMULATORACCUMULATOR

ACCUMULATOR

ACCUMULATORACCUMULATOR

Accumulator is a 4-bit data register for temporary data. For the arithematic, logic and comparative opertion
.., ACC plays a role which holds the source data and result.

FLAGSFLAGS

FLAGS

FLAGSFLAGS

There are four kinds of flag, CF ( Carry flag ), ZF ( Zero flag ), SF ( Status flag ) and GF ( General flag ),

these 4 1-bit flags are affected by the arithematic, logic and comparative .... operation.

All flags will be put into stack when an interrupt subroutine is served, and the flags will be restored after
RTI instruction executed.

* This specification are subject to be changed without notice.

12.27.2001

11

EM73P461AEM73P461A

EM73P461A

EM73P461AEM73P461A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

PreliminaryPreliminary

Preliminary

PreliminaryPreliminary

(1) Carry Flag ( CF )

The carry flag is affected by following operation:
a. Addition : CF as a carry out indicator, when the addition operation has a carry-out, CF will be "1",

in another word, if the operation has no carry-out, CF will be "0".

b. Subtraction : CF as a borrow-in indicator, when the subtraction operation must has a borrow, in the CF

will be "0", in another word, if no borrow-in, CF will be "1".

c. Comparision: CF is as a borrow-in indicator for Comparision operation as the same as subtraction

operation.

d. Rotation: CF shifts into the empty bit of accumulator for the rotation and holds the shift out data after

rotation.

e. CF test instruction : For TFCFC instruction, the content of CF sends into SF then clear itself "0".

For TTSFC instruction, the content of CF sends into SF then set itself "1".

(2) Zero Flag ( ZF )

ZF is affected by the result of ALU, if the ALU operation generate a "0" result, the ZF will be "1",
otherwise, the ZF will be "0".

(3) Status Flag ( SF )

The SF is affected by instruction operation and system status.

a. SF is initiated to "1" for reset condition.

b. Branch instruction is decided by SF, when SF=1, branch condition will be satisified, otherwise,
branch condition will not be satisified by SF = 0.

@(4) General Flag ( GF )

GF is a one bit general purpose register which can be set, clear, test by instruction SGF, CGF and TGS.

PROGRAM EXAMPLE:

Check following arithematic operation for CF, ZF, SF

@ : just for 4K ROM.

* This specification are subject to be changed without notice.

12.27.2001

12