ELAN EM73P361AH, EM73P361AAQ Datasheet

1

* This specification are subject to be changed without notice.

12.17.2001

EM73P361AEM73P361A

EM73P361A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

GENERAL DESCRIPTIONGENERAL DESCRIPTION

GENERAL DESCRIPTION

EM73P361A is an advanced single chip CMOS 4-bit one-time programming (OTP) micro-controller. It contains 3K-byte OTP ROM, 52-nibble RAM, 4-bit ALU, 13-level subroutine nesting, 22-stage time base, two 12-bit timer/ counters for the kernel function. EM73P361A also contains 5 interrupt sources, 1 input port, 4 bidirection I/O ports, built-in watch-dog-timer counter, tone generator and LCD driver (27x3 to 13x3). Except low-power consumption and high speed, EM73P361A also have a sleep mode operation for power saving.

FEATURESFEATURES

FEATURES

• Operation voltage : 2.4V to 3.6V(clock frequency : 32K Hz).

• Clock source : Single clock system for crystal, connect a external resistor or external clock source available by mask option.

• Instruction set : 109 powerful instructions.

• Instruction cycle time : 122µs for 32K Hz.

• OTP ROM capacity : 3072 x 8 bits.

• RAM capacity : 52 x 4 bits.

• Input port : 1 port (P0)(Pull-up and pull-down resistor with wakeup function available by mask option).

• Bidirection port : 4 ports (P4, P5, P6, P7) are available by mask option. (each I/O pin is push-pull and open-drain available by mask option) P4.0 is high current pin (P4.0 and TONE available by mask option). P4.2~P4.3, P5, P6 and P7 are shared with SEG26-SEG13 by mask option.

• 12-bit timer/counter : Two 12-bit timer/counters are programmable for timer mode.

• Low voltage reset (LVR) : Reset at 2.2V, and reset release at 2.4V.

• Tone generator : There is a built-in tone generator.

• Built-in time base counter : 22 stages.

• Subroutine nesting : Up to 13 levels.

• Interrupt : External . . . . . 2 External interrupt (INT0, INT1).

Internal . . . . . . 2 Timer overflow interrupts.

1 Time base interrupt.

• LCD driver : 27 X 3 to 13 X 3 dots available by mask option. Capacitor divider and resistor divider are available by mask option.1/3, 1/2 and static three kinds of duty (1/2 bias) selectable. The programming method of LCD driver is I/O mapping.

• Built-in watch-dog-timer : The WDT is enabled or disabled by mask option.

• Power saving function : Sleep mode and Hold mode.

• Package type : EM73P361AH Chip form 47 pins. EM73P361AAQ QFP 100 pins.

APPLICATIONSAPPLICATIONS

APPLICATIONS

EM73P361A is suitable for application in family appliance, consumer products, hand held games and the toy controller.

2

* This specification are subject to be changed without notice.

12.17.2001

EM73P361AEM73P361A

EM73P361A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

PIN CONFIGURATIONSPIN CONFIGURATIONS

PIN CONFIGURATIONS

123456789

101112131415161718192021222324252627282930

50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31

8079787776757473727170696867666564636261605958575655545352

51

81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

100

NC NC NC

NC P7.1/SEG15 P7.2/SEG14 P7.3/SEG13

SEG12 SEG11 SEG10

SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3

NC

NCNCNCNCNCNCNC

NC

SEG2

SEG1

SEG0

COM1

COM0

VEE

VB

VA

XIN

XOUT

NCNCNCNCNCNCNCNCNC

NC NC NC NC NC P4.1/WDT P4.0/TONE TONE P0.3/WAKEUP3 P0.2(INT0)/WAKEUP2 P0.1/WAKEUP1 P0.0(INT1)/WAKEUP0

RESET

NC NC NC NC

NCNCNCNCNC

NC

TEST

VPPNCNCNCNCNCNCNCNC

NC

EM73P361AAQ

QFP 100

NC

VDD VSS

P4.3/SEG25

P4.2/SEG26

COM2

P5.0/SEG24

P5.2/SEG22

P5.1/SEG23

P6.0/SEG20

P5.3/SEG21

P6.2/SEG18

P6.1/SEG19

P7.0/SEG16

P6.3/SEG17

NC

3

* This specification are subject to be changed without notice.

12.17.2001

EM73P361AEM73P361A

EM73P361A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

FUNCTION BLOCK DIAGRAMFUNCTION BLOCK DIAGRAM

FUNCTION BLOCK DIAGRAM

Interrupt

Control

Time Base

12-bit

timer

counter

(TA,TB)

System Control

Instruction Decoder

Instruction Register

ROM

PC

Data Bus

Reset

Control

Frequency

doubler

Timing

Generator

Sleep Mode

Control

Data pointer

ACC

ALU

Flag

ZCS G

Stack pointer

Stack

RAM

HR

LR

I/O Control

P0.0(INT1)/WAKEUP0 P0.1/WAKEUP1 P0.2(INT0)/WAKEUP2 P0.3/WAKEUP3

RESET

Clock

Generator

XIN

XOUT

LCD

driver

Tone generator

WDT

VA VB VEE COM0~COM2 SEG0~SEG12

P4.0/TONE P4.1/WDT

TONE

P4,P5,P6,P7/SEG(26..13)

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* This specification are subject to be changed without notice.

12.17.2001

EM73P361AEM73P361A

EM73P361A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

SymbolSymbol

Symbol

Pin-typePin-type

Pin-type

FunctionFunction

Function

V

DD

Power supply (+) In programming OTP mode: Power supply (+)

VSS Power supply (-)

In programming OTP mode: Power supply (-)

RESET RESET-A System reset input signal, low active

Internal pull-up In programming OTP mode:

Reset input pin, low active XIN OSC-A/OSC-F Crystal/external resistor or external clock source connecting pin XOUT OSC-A/OSC-F Crystal/external resistor connecting pin

P0.0(INT1)/WAKEUP0, INPUT-J 2-bit input port with external interrupt sources input and Sleep/Hold P0.2(INT0)/WAKEUP2 releasing function

mask option : wakeup enable, pull-up

wakeup enable, none wakeup disable, pull-up wakeup disable, none

wakeup disable, pull-down In programming OTP mode: P0.0/ACLK: address counter clock for programming OTP P0.2/OE: data output enable for programming OTP

P0.1/WAKEUP1, INPUT-H 2-bit input port with Sleep/Hold releasing function P0.3/WAKEUP3 mask option : wakeup enable, pull-up

wakeup enable, none

wakeup disable, pull-up

wakeup disable, pull-down

wakeup disable, none In programming OTP mode: P0.1/PGM: program data to OTP for programming OTP P0.3/DCLK: data in/out clock signal for programming OTP

P4.0/TONE I/O-O 1-bit bidirection I/O pin or inverse tone generator output

mask option : TONE enable, push-pull, high current PMOS

TONE disable, open-drain

TONE disable, push-pull, high current PMOS

TONE disable, push-pull, low current PMOS In programming OTP mode: P4.0/DIN : data input for programming OTP

PIN DESCRIPTIONSPIN DESCRIPTIONS

PIN DESCRIPTIONS

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* This specification are subject to be changed without notice.

12.17.2001

EM73P361AEM73P361A

EM73P361A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

FUNCTION DESCRIPTIONSFUNCTION DESCRIPTIONS

FUNCTION DESCRIPTIONS

PROGRAM ROM ( 3K X 8 bits )PROGRAM ROM ( 3K X 8 bits )

PROGRAM ROM ( 3K X 8 bits )

3 K x 8 bits program ROM contains user's program and some fixed data .

The basic structure of program ROM can be divided into 4 parts.

1. Address 000h: Reset start address.

2. Address 002h - 00Ch: 4 kinds of interrupt service routine entry addresses .

3. Address 00Eh-086h : SCALL subroutine entry address, only available at 00Eh,016h,01Eh,026h, 02Eh, 036h, 03Eh, 046h, 04Eh, 056h, 05Eh, 066h, 06Eh, 076h ,07Eh, 086h .

4. Address 000h - 7FFh : LCALL subroutine entry address

5. Address 000h - BFFh : Except used as above function, the other region can be used as user's program region.

address 3072 x 8 bits 000h Reset start address 002h INT0 ; External interrupt service toutine entry address 004h 006h TRGA; Timer/counter A interrupt service routine entry address 008h TRGB; Timer/counter B interrupt service routine entry address 00Ah TBI; Time base interrupt service routine entry address 00Ch INT1; External interrupt service routine entry address 00Eh 086h

BFFh

SymbolSymbol

Symbol

Pin-typePin-type

Pin-type

FunctionFunction

Function

P4.1/WDT I/O-D 1-bit bidirection I/O pin with watch-dog-timer output

mask option : open-drain

push-pull In programming OTP mode: P4.1/DOUT: data output for programming OTP

P4(2..3)/SEG(26..25) I/O-P 4-bit bidirection I/O ports are shared with LCD segment pins P5(0..3)/SEG(24..21) mask option : segment enable, open-drain P6(0..3)/SEG(20..17) segment disable, push-pull P7(0..3)/SEG(16..13) segment disable, open-drain TONE Built-in tone generator output VA, VB, VEE Connect the capacitors for LCD bias voltage COM0~COM2 LCD common output pins SEG0~SEG12 LCD segment output pins

TEST Internal pull down V PP Connect to VDD

In programming OTP mode: High voltage power source for programming OTP

SCALL, subroutine call entry address

.

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* This specification are subject to be changed without notice.

12.17.2001

EM73P361AEM73P361A

EM73P361A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

STACK:

There are 13 - level (maximum) stack for user using for subroutine (including interrupt and CALL). User can assign any level be the starting stack by giving the level number to stack pointer (SP).

ZERO- PAGE:

From 00h to 0Fh is the location of zero-page. It is used as the pointer in zero -page addressing mode for the instruction of "STD #k,y; ADD #k,y; CLR y,b; CMP k,y".

PROGRAM EXAMPLE: To wirte immediate data "07h" to address "03h" of RAM and to clear bit 2 of RAM.

STD #07h, 03h ; RAM[03] ← 07h CLR 0Eh,2 ; RAM[0Eh]2 ← 0

Increment

Address

20h - 2Fh 30h - 33h

Level 0 Level 4 Level 8 Level 12

Level 1 Level 5 Level 9

Level 2 Level 6 Level 10

Level 3 Level 7 Level 11

Increment

00h - 0Fh 10h - 1Fh

Stack Zero-page

DATA RAM ( 52-nibble ) DATA RAM ( 52-nibble )

DATA RAM ( 52-nibble )

There is total 52 - nibble data RAM from address 00 to 33h Data RAM includes 3 parts: zero page region, stacks and data area.

LDAXLDAX

LDAX

Acc Acc

Acc

←←

←

ROM[DP] ROM[DP]

ROM[DP]

LL

L

LDAXILDAXI

LDAXI

Acc Acc

Acc

←←

←

ROM[DP] ROM[DP]

ROM[DP]

HH

H

,DP+1,DP+1

,DP+1

DP is a 12-bit data register which can store the program ROM address to be the pointer for the ROM code data. First, user load ROM address into DP by instruction "STADPL, STADPM, STADPH", then user can get the lower nibble of ROM code data by instruction "LDAX" and higher nibble by instruction "LDAXI".

PROGRAM EXAMPLE: Read out the ROM code of address 777h by table-look-up instruction.

LDIA #07h; STADPL ; [DP]L ← 07h STADPM ; [DP]M ← 07h STADPH ; [DP]H ← 07h, Load DP=777h : LDL #00h; LDH #03h; LDAX ; ACC ← 6h STAMI ; RAM[30] ← 6h LDAXI ; ACC ← 5h STAM ; RAM[31] ← 5h ; ORG 777h DATA 56h; :

Table-look-up instruction is depended on the Data Pointer ( DP ) to indicate to ROM address, then to get the ROM code data.

User's program and fixed data are stored in the program ROM. User's program is according the PC value to send next executed instruction code. Fixed data can be read out by table-look-up instruction.

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* This specification are subject to be changed without notice.

12.17.2001

EM73P361AEM73P361A

EM73P361A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

When user using any instruction of CALL or subroutine, before entry the subroutine, the previous PC address will be saved into stack until return from those subroutines, the PC value will be restored by the data saved in stack.

DATA AREA:

Except the special area used by user, the whole RAM can be used as data area for storing and loading general data.

ADDRESSING MODE

(1) Indirect addressing mode:

Indirect addressing mode indicates the RAM address by specified HL register. For example:

LDAM ; Acc ← RAM[HL] STAM ; RAM[HL] ← Acc

(2) Direct addressing mode:

Direct addressing mode indicates the RAM address by immediate data. For example: LDA x ; Acc← RAM[x]

STA x ; RAM[x] ← Acc

(3) Zero-page addressing mode

For zero-page region, user can using direct addressing to write or do any arithematic, comparsion or bit manupulated operation directly. For example: STD #k,y ; RAM[y] ← #k

ADD #k,y; RAM[y] ← RAM[y] + #k

PROGRAM COUNTER (3K ROM)PROGRAM COUNTER (3K ROM)

PROGRAM COUNTER (3K ROM)

Program counter ( PC ) is composed by a 12-bit counter, which indicates the next executed address for the instruction of program ROM. For a 3K - byte size ROM, PC can indicate address form 000h - BFFh, for BRANCH and CALL instrcutions,

PC is changed by instruction indicating.

(1) Branch instruction:(1) Branch instruction:

(1) Branch instruction:

SBR aSBR a

SBR a

Object code: 00aa aaaa Condition: SF=1; PC ← PC

11-6.a

( branch condition satisified )

PC Hold original PC value+1 aaaaaa

SF=0; PC← PC +1( branch condition not satisified)

PC Original PC value + 1

LBR aLBR a

LBR a

Object code: 1100 aaaa aaaa aaaa Condition: SF=1; PC ← a ( branch condition satisified)

PCaaaaaaaaaaaa

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* This specification are subject to be changed without notice.

12.17.2001

EM73P361AEM73P361A

EM73P361A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

SF=0 ; PC ← PC + 2 ( branch condition not satisified )

PC Original PC value + 2

(2) Subroutine instruction:(2) Subroutine instruction:

(2) Subroutine instruction:

SCALL aSCALL a

SCALL a

Object code: 1110 nnnn Condition : PC ← a ; a=8n+6 ; n=1..15 ; a=86h, n=0

LCALL aLCALL a

LCALL a

Object code: 0100 0aaa aaaa aaaa Condition: PC ← a

PC0aaaaaaaaaaa

RETRET

RET

Object code: 0100 1111 Condition: PC ← STACK[SP]; SP + 1

PC The return address stored in stack

RT IRT I

RT I

Object code: 0100 1101 Condition : FLAG. PC ← STACK[SP]; EI ← 1; SP + 1

PC The return address stored in stack

(3) Interrupt acceptance operation:(3) Interrupt acceptance operation:

(3) Interrupt acceptance operation:

When an interrupt is accepted, the original PC is pushed into stack and interrupt vector will be loaded into PC,The interrupt vectors are as following:

INT0 INT0

INT0 (External interrupt from P0.2)

PC000000000010

TRGATRGA

TRGA (Timer A overflow interrupt)

PC000000000110

TRGBTRGB

TRGB (Time B overflow interrupt)

PC000000001000

TBITBI

TBI (Time base interrupt)

PC000000001010

PC 0 0 0 0 a a a a a a a a

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* This specification are subject to be changed without notice.

12.17.2001

EM73P361AEM73P361A

EM73P361A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

INT1 INT1

INT1 (External interrupt from P0.0)

PC000000001100

(4) Reset operation:(4) Reset operation:

(4) Reset operation:

PC000000000000

(5) Other operations:(5) Other operations:

(5) Other operations:

For 1-byte instruction execution: PC + 1 For 2-byte instruction execution: PC + 2

There are four kinds of flag, CF ( Carry flag ), ZF ( Zero flag ), SF ( Status flag ) and GF ( General flag ),

these 4 1-bit flags are affected by the arithematic, logic and comparative .... operation .

All flags will be put into stack when an interrupt subroutine is served, and the flags will be restored after RTI instruction executed .

(1) Carry Flag ( CF )

The carry flag is affected by following operation: a. Addition : CF as a carry out indicator, when the addition operation has a carry-out, CF will be "1",

in another word, if the operation has no carry-out, CF will be "0".

b. Subtraction : CF as a borrow-in indicator, when the subtraction operation must has a borrow, in the CF

will be "0", in another word, if no borrow-in, CF will be "1".

c. Comparision: CF is as a borrow-in indicator for Comparision operation as the same as subtraction

operation.

d. Rotation: CF shifts into the empty bit of accumulator for the rotation and holds the shift out data after

rotation.

e. CF test instruction : For TFCFC instruction, the content of CF sends into SF then clear itself "0".

For TTSFC instruction, the content of CF sends into SF then set itself "1".

(2) Zero Flag ( ZF )

ZF is affected by the result of ALU, if the ALU operation generate a "0" result, the ZF will be "1", otherwise, the ZF will be "0".

(3) Status Flag ( SF )

The SF is affected by instruction operation and system status .

ACCUMULATORACCUMULATOR

ACCUMULATOR

Accumulator is a 4-bit data register for temporary data . For the arithematic, logic and comparative opertion .., ACC plays a role which holds the source data and result .

FLAGSFLAGS

FLAGS

10

* This specification are subject to be changed without notice.

12.17.2001

EM73P361AEM73P361A

EM73P361A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

ALUALU

ALU

The arithematic operation of 4 - bit data is performed in ALU unit . There are 2 flags can be affected by the result of ALU operation, ZF and SF . The operation of ALU can be affected by CF only .

ALU STRUCTUREALU STRUCTURE

ALU STRUCTURE

ALU supported user arithematic operation function, including : addition, subtraction and rotaion.

ALU FUNCTIONALU FUNCTION

ALU FUNCTION

(1) Addition:

For instruction ADDAM, ADCAM, ADDM #k, ADD #k,y .... ALU supports addition function.

The addition operation can affect CF and ZF. For addition operation, if the result is "0", ZF will be "1", otherwise, not equal "0", ZF will be "0", When the addition operation has a carry-out. CF will be "1", otherwise, CF will be "0".

EXAMPLE:

Operation Carry Zero 3+4=7 0 0 7+F=6 1 0 0+0=0 0 1 8+8=0 1 1

(2) Subtraction:

For instruction SUBM #k, SUBA #k, SBCAM, DECM... ALU supports user subtraction function . The subtraction operation can affect CF and ZF, For subtraction operation, if the result is negative, CF will

GF is a one bit general purpose register which can be set, clear, test by instruction SGF, CGF and TGS.

PROGRAM EXAMPLE:

Check following arithematic operation for CF, ZF, SF

CF ZF SF LDIA #00h; - 1 1 LDIA #03h; - 0 1 ADDA #05h; - 0 1 ADDA #0Dh; - 0 0 ADDA #0Eh; - 0 0

a. SF is initiated to "1" for reset condition .

b. Branch instruction is decided by SF, when SF=1, branch condition will be satisified, otherwise, branch condition will not be satisified by SF = 0 .

(4) General Flag ( GF )

ZF CF SF GF

ALU

DATA BUS

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* This specification are subject to be changed without notice.

12.17.2001

EM73P361AEM73P361A

EM73P361A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

ACC

CF

MSB LSB

3 2 1 0

H REGISTER

3 2 1 0

L REGISTER

ACC

CF

MSB LSB

(3) Rotation:

There are two kinds of rotation operation, one is rotation left, the other is rotation right. RLCA instruction rotates Acc value to left, shift the CF value into the LSB bit of Acc and the shift out data will be hold in CF.

RRCA instruction operation rotates Acc value to right, shift the CF value into the MSB bit of Acc and the shift out data will be hold in CF.

PROGRAM EXAMPLE: To rotate Acc right and shift a "1" into the MSB bit of Acc .

TTCFS; CF ← 1 RRCA; rotate Acc right and shift CF=1 into MSB.

HL REGISTERHL REGISTER

HL REGISTER

HL register are two 4-bit registers, they are used as a pair of pointer for the address of RAM memory and also 2 independent temporary 4-bit data registers. For some instruction, L register can be a pointer to indicate the pin number ( Port4, Port6, Port7 ) .

HL REGISTER STRUCTUREHL REGISTER STRUCTURE

HL REGISTER STRUCTURE

HL REGISTER FUNCTIONHL REGISTER FUNCTION

HL REGISTER FUNCTION

(1)For instruction : LDL #k, LDH #k, THA, THL, INCL, DECL, EXAL, EXAH, HL register used as a

temporary register .

PROGRAM EXAMPLE: Load immediate data "5h" into L register, "Dh" into H register.

LDL #05h; LDH #0Dh;

(2) For instruction LDAM, STAM, STAMI .., HL register used as a pointer for the address of RAM memory.

EXAMPLE:

Operation Carry Zero 8-4=4 1 0 7-F= -8(1000) 0 0 9-9=0 1 1

be "0", it means a borrow out, otherwise, if the result is positive, CF will be "1". For ZF, if the result of subtraction operation is "0", the ZF will be "1", otherwise, ZF will be "1".

ELAN EM73P361AH, EM73P361AAQ Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual