ELAN EM73A89B Datasheet
GENERAL DESCRIPTION
EM73A89B is an advanced single chip CMOS 4-bit micro-controller. It contains 16K-byte ROM, 1012-nibble
RAM, 4-bit ALU, 13-level subroutine nesting, 22-stage time base, two 12-bit timer/counters for the kernel
function, and one high speed conter. EM73A89B also equipped with 6 interrupt sources, 3~7 I/O ports (including
1 input port and 2~7 bidirection ports), LCD display (64x16 or 64x32), built-in watch-dog-timer and speech
synthesizer.
It's low power consumption and high speed feature are further strengten with DUAL, SLOW, IDLE and STOP
operation mode for optimized power saving.
FEATURES
Operation voltage : 2.2V to 3.6V.
Clock source : Dual clock system. Low-frequency oscillator is 32KHz. Crystal oscillator or RC
Instruction set : 107 powerful instructions.
Instruction cycle time : 0.85µs for 9.2M or 1.7µs for 4.6M Hz selected by mask option(high speed clock).
ROM capacity : 16K x 8 bits.
RAM capacity : 1012 x 4 bits.
Input port : 1 port (P0.0-P0.3), IDLE/STOP releasing function is available by mask option.
Bidirection port : 2~7 ports (P1, P2, P4, P5, P6, P7, P8). IDLE/STOP release function for P8(0..
Built-in watch-dog-timer counter : It is available by mask option.
12-bit timer/counter : Two 12-bit timer/counters are programmable for timer, event counter and pulse
Built-in time base counter : 22 stages.
Subroutine nesting : Up to 13 levels.
Interrupt : External interrupt . . . . . . 2 input interrupt sources.
High speed counter : The high speed counter includes one 8-bit high speed counter and a resistor to
LCD driver : 64x32 or 64x16 dots, 1/32 or 1/16 duty, 1/5 bias by mask option.
Speech synthesizer : 992K speech data ROM (use as 992K nibbles data ROM).
PWM or current D/A : Output selection by mask option.
Power saving function : SLOW, IDLE, STOP operation modes.
Package type : Chip form 126 pins.
EM73A89B
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Preliminary
oscillator by mask option and high-frequency oscillator is a built-in internal
oscillator.
122µs for 32768 Hz (low speed clock, frequency double).
(each input pin has a pull-up and pull-down resistor available by mask option).
3) is available by mask option. P1, P2, P5, P6, P7 are shared with LCD pins.
width measurement mode.
Internal interrupt . . . . . . 2 timer overflow interrupts, 1 time base interrupt.
1 speech/HTC interrupt.
frequency oscillator. It has resistor to frequrncy oscillation mode, melody mode
and auto load timer mode.
* This specification are subject to be changed without notice.
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FUNCTION BLOCK DIAGRAM
RESET CLK
Reset
Control
BZ1/VO
BZ2
P4.0(RX)
P4.1
P4.2(RY)
P4.3(RZ)
VC1~VC4,
VA,VB
VR1~VR4
Speech
synthesizer
HTC
LCD Driver
SEG0~43
COM0~15
Interrupt
Control
Timer/Counter
(TA,TB)
or SEG44~59
P2,5,6,7/COM16~31
P1/SESG60~63
Preliminary
LXIN
LXOUT
Clock
Generator
System Control
Instruction Decoder
Instruction Register
Time
Base
ROM
PC
Data Bus
I/O Control
Timing
Generator
Data pointer
ACC
ALU
Flag
ZCS
Clock Mode
Control
Stack pointer
Stack
RAM
HR
LR
P8.2(INT0)/WAKEUPC
P8.0(INT1)/WAKEUPA
P8.1(TRGB)/WAKEUPB
P8.3(TRGA)/WAKEUPD
P0.0/WAKEUP0
P0.1/WAKEUP1
P0.2/WAKEUP2
P0.3/WAKEUP3
PIN DESCRIPTIONS
Symbol Pin-type Function
V
DD,VDD2
V
SS
RESET RESET-A System reset input signal, low active
CLK OSC-G Capacitor connecting pin for internal high frequency oscillator.
LXIN OSC-B/OSC-H Crystal/Resistor connecting pin for low speed clock source.
LXOUT OSC-B Crystal connecting pin for low speed clock source.
P0(0..3)/WAKEUP0..3 INPUT-B 4-bit input port with IDLE/STOP releasing function
P4.0(RX),P4.2(RY), I/O-X1 3-bit bidirection I/O pins or RF oscillation input pins.
P4.3(RZ) mask option : open-drain (apply to RF oscillation)
P4.1 I/O-Q1 1-bit bidirection I/O pin.
Power supply (+)
Power supply (-)
mask option : none
pull-up
mask option : wakeup enable, pull-up
wakeup enable, none
wakeup disable, pull-up
wakeup disable, pull-down
wakeup disable, none
high current push-pull
normal current push-pull
low current push-pull
mask option : open-drain
high current push-pull
normal current push-pull
low current push-pull
* This specification are subject to be changed without notice.
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Preliminary
Symbol Pin-type Function
P8.0(INT1)/WAKEUPA I/O-X1 2-bit bidirection I/O port with external interrupt sources input and IDLE
P8.2(INT0)/WAKEUPC /STOP releasing function
mask option : wakeup enable, normal current push-pull
wakeup ensable, low current push-pull
wakeup disable, high current push-pull
wakeup disable, normal current push-pull
wakeup disable, low current push-pull
wakeup disable, open drain
P8.1(TRGB)/WAKEUPB I/O-X1 2-bit bidirection I/O port with time/counter A,B external input and IDLE
P8.3(TRGA)/WAKEUPD /STOP releasing function
mask option : wakeup enable, normal current push-pull
wakeup ensable, low current push-pull
wakeup disable, high current push-pull
wakeup disable, normal current push-pull
wakeup disable, low current push-pull
wakeup disable, open drain
VCA, VCB, V1~V6 LCD bias voltage pins
BZ1/VO PWM or current D/A output pin for speech synthesizer by mask option
BZ2 PWM output pin for speech synthesizer
TEST Tie Vss as package type, no connecting as COB type.
*16 COMMONS :
COM0~COM15 LCD common output pins
SEG0~SEG59 LCD segment output pins
P1(0..3)/SEG63..60 I/O-P 4-bit bidirection I/O pins with LCD segment pins
mask option : LCD segment pin
push-pull
open-drain
P2(0..3),P5(0..3), I/O-P 16-bit bidirection I/O pins
P6(0..3),P7(0..3) mask option : push-pull
open-drain
*32 COMMONS :
COM0~COM31 LCD common output pins
SEG0~SEG43 LCD segment output pins
P1(0..3)/SEG63..60, I/O-P 16-bit bidirection I/O pins with LCD segment pins
P2(0..3)/SEG59..56, mask option : LCD segment pin
P5(0..3)/SEG55..52, push-pull
P6(0..3)/SEG51..48, open-drain
P7(0..3)/SEG47..44
* This specification are subject to be changed without notice.
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Preliminary
FUNCTION DESCRIPTIONS
PROGRAM ROM ( 16K X 8 bits )
16 K x 8 bits program ROM contains user's program and some fixed data.
The basic structure of the program ROM may be categorized into 5 partitions.
1. Address 0000h : Reset start address.
2. Address 0002h - 000Ch : 6 kinds of interrupt service routine entry addresses.
3. Address 000Eh - 0086h : SCALL subroutine entry address, only available at 000Eh, 0016h, 001Eh, 0026h, 002Eh,
0036h, 003Eh, 0046h, 004Eh, 0056h, 005Eh, 0066h, 006Eh, 0076h, 007Eh, 0086h.
4. Address 0000h - 07FFh : LCALL subroutine entry address.
5. Address 0000h - 1FFFh : Except used as above function, the other region can be used as user's program and
data region.
address Bank 0 :
EM73A89B
0000h
0002h
0004h
0006h
0008h
000Ah
000Ch
000Eh
0086h
.
.
.
07FFh
0800h
0FFFh
1000h
1FFFh
Reset start address
INT0 ; interrupt service routine entry address
SPI or HTCI
TRGA
TRGB
TBI
INT1
SCALL, subroutine call entry address
Bank 1
Bank 2
Bank 3
Subroutine call entry address
designated by [LCALL a]
instruction
Data table for
[LDAX],[LDAXI]
instruction
* This specification are subject to be changed without notice.
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User's program and fixed data are stored in the program ROM. User's program is executed using the PC value
Preliminary
to fetch an instruction code.
The 16Kx8 bits program ROM can be divided into 4 banks. There are 4Kx8 bits per bank.
The program ROM bank is selected by P3(1..0). The program counter is a 13-bit binary counter. The PC and
P3 are initialized to "0" during reset.
When P3(1..0)=00B or 11B, the bank0 and bank1 of program ROM will be selected. P3(1..0)=01B, the bank0
and bank2 will be selected. P3(1..0)=10B, the bank0 and bank3 will be selected.
P3=xx00B
Address P3=xx11B P3=xx01B P3=xx10B
0000h
:
: Bank0 Bank0 Bank0
0FFFh
1000h
:
: Bank1 Bank2 Bank3
1FFFh
PROGRAM EXAMPLE:
BANK 0
START: :
:
:
LDIA #00H ; set program ROM to bank1
OUTA P3
B XA1
:
XA : :
:
LDIA #01H ; set program ROM to bank2
OUTA P3
B XB1
:
XB : :
:
LDIA #02H ; set program ROM to bank3
OUTA P3
B XC1
:
XC : :
:
BXD
XD : :
:
:
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BANK 1
XA1 : :
:
BXA
:
XA2 : :
* This specification are subject to be changed without notice.
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B XA2
Preliminary
:
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BANK 2
XB1 : :
:
BXB
:
XB2 : :
B XB2
:
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BANK 3
XC1 : :
:
BXC
:
XC2 : :
B XC2
Fixed data can be read out by table-look-up instruction. Table-look-up instruction is requires the Data point
(DP) to indicate the ROM address in obtaining the ROM code data (Except bank 0) :
LDAX Acc
LDAXI Acc
←←
← ROM[DP]
←←
←←
← ROM[DP]
←←
L
,DP+1
H
DP is a 12-bit data register that stores the program ROM address as pointer for the ROM code data.
User has to initially load ROM address into DP with instructions "STADPL", and "STADPM, STADPH",
then to obtain the lower nibble of ROM code data by instruction "LDAX" and higher nibble by instruction
"LDAXI".
PROGRAM EXAMPLE: Read out the ROM code of address 1777h by table-look-up instruction.
LDIA #07h;
STADPL ; [DP]
STADPM ; [DP]
STADPH ; [DP]
:
LDL #00h;
LDH #03h;
LDAX ; ACC ← 6h
STAMI ; RAM[30] ← 6h
LDAXI ; ACC ← 5h
STAM ; RAM[31] ← 5h
;
ORG 1777h
DATA 56h;
← 07h
L
← 07h
M
← 07h, Load DP=777h
H
DATA RAM ( 1012-nibble )
A total 1012 - nibble data RAM is available from address 000 to 3FFh
Data RAM includes the zero page region, stacks and data areas.
* This specification are subject to be changed without notice.
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Preliminary
EM73A89B
Bank 0
Address
P9=xx00B 000-00Fh
010-01Fh
020-02Fh
030-03Fh
040-04Fh
050-05Fh
060-06Fh
070-07Fh
080-08Fh
090-09Fh
0A0-0AFh
0B0-0BFh
0C0-0CFh
0D0-0DFh
0E0-0EFh
0F0-0FFh
Bank 1
P9=xx01B 100-10Fh
110-11Fh
:
:
1E0-1EFh
1F0-1FFh
Bank 2
P9=xx10B 200-20Fh
210-21Fh
220-22Fh
230-23Fh
240-24Fh
250-25Fh
260-26Fh
270-27Fh
280-28Fh
290-29Fh
2A0-2AFh
2B0-2BFh
2C0-2CFh
2D0-2DFh
2E0-2EFh
2F0-2FFh
Bank 3
P9=xx11B 300-30Fh
310-31Fh
320-32Fh
330-33Fh
340-34Fh
350-35Fh
360-36Fh
370-37Fh
380-38Fh
390-39Fh
3A0-3AFh
3B0-3BFh
3C0-3CFh
3D0-3DFh
3E0-3EFh
3F0-3FFh
0123456789ABCDEF
ZERO PAGE
Level 0 Level 1 Level 2 Level 3
Level 4 Level 5 Level 6 Level 7
Level 8
Level 8 Level 10 Level 11
Level 12
:
:
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
* This specification are subject to be changed without notice.
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
8.16.2001
SEG62
SEG63
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EM73A89B
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Preliminary
ZERO- PAGE:
From 000h to 00Fh is the zero-page location. It is used as the zero-page address mode pointer for the
instruction of "STD #k,y; ADD #k,y; CLR y,b; CMP k,y".
PROGRAM EXAMPLE: To write immediate data "07h" to RAM [03] and to clear bit 2 of RAM [0Eh].
STD #07h, 03h ; RAM[03] ← 07h
CLR 0Eh,2 ; RAM[0Eh]
STACK:
There are 13 - level (maximum) stack levels that user can use for subroutine (including interrupt and CALL).
User can assign any level be the starting stack by providing the level number to stack pointer (SP).
When an instruction (CALL or interrupt) is invoked, before enter the subroutine, the previous PC address
is saved into the stack until returned from those subroutines, the PC value is restored by the data saved in stack.
DATA AREA:
← 0
2
Except the area used by user's application, the whole RAM can be used as data area for storing and loading
general data.
ADDRESSING MODE
The 1012 nibble data memory consists of four banks (bank 0 ~ bank 3). There are 244x4 bits (address
000h~0F3h) in bank 0 and 768x4 bits (address 100h ~ 3FFh) in bank 1 ~ bank 3.
The bank is selected by P9.
P9 Initial value : * * 0 0
* * RBK
RBK RAM bank
0 0 Bank0
0 1 Bank1
1 0 Bank2
1 1 Bank3
The Data Memory consists of three Address mode, namely -
(1) Indirect addressing mode:
The address in the bank is specified by the HL registers.
P9(1,0)
HR LR
RAM address
* This specification are subject to be changed without notice.
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Preliminary
PROGRAM EXAMPLE: Load the data of RAM address "143h" to RAM address "032h".
OUT #0001B,P9 ; RAM bank1
LDL #3h ; LR← 3
LDH # 4h ; HR← 4
LDAM ; Acc← RAM[134h]
OUT #0000B,P9 ; RAM bank0
LDL #2h ; LR← 2
LDH # 3h ; HR← 3
STAM ; RAM[023h]← Acc
(2) Direct addressing mode:
The address in the bank is directly specified by 8 bits code of the second byte in the instruction field.
instruction field
xxxxxxxx
P9(1,0)
EM73A89B
RAM address
PROGRAM EXAMPLE: Load the data of RAM address "143h" to RAM address "023h".
OUT #0001B,P9
LDA 43h ; Acc← RAM[143h]
OUT #0000B,P9
STA 23h ; RAM[023h]← Acc
(3) Zero-page addressing mode:
The zero-page is in the bank 0 (address 000h~00Fh). The address is the lower 4 bits code of the second byte
in the instruction field.
xxxxxxxx
instruction field
yyyy
0000
yyyy
RAM address
PROGRAM EXAMPLE: Write immediate "0Fh" to RAM address "005h".
STD #0Fh, 05h ; RAM[05h]← 0Fh
00
* This specification are subject to be changed without notice.
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PROGRAM COUNTER (16K ROM)
Preliminary
Program counter ( PC ) is composed by a 13-bit counter, which indicates the next executed address for the
instruction of program ROM instruction.
For BRANCH and CALL instructions, PC is changed by instruction indicating. PC only can indicate the address
from 0000h-1FFFh. The bank number is decided by P3.
(1) Branch instruction:
SBR a
Object code: 00aa aaaa
Condition: SF=1; PC ← PC
( branch condition satisified )
12-6.a
PC Hold original PC value+1 aaaaaa
SF=0; PC← PC +1( branch condition not satisified )
PC Original PC value + 1
LBR a
Object code: 1100 aaaa aaaa aaaa
Condition: SF=1; PC ← PC
( branch condition satisified )
12.a
Hold
PC
a a a a a a aaaaaa
+2
SF=0; PC← PC +2( branch condition not satisified )
PC Original PC value + 2
SLBR a
Object code: 0101 0101 1100 aaaa aaaa aaaa (a:1000h~1FFFh)
0101 0111 1100 aaaa aaaa aaaa (a:0000h~0FFFh)
Condition: SF=1; PC ← a ( branch condition satisified )
PCaaaaaaaaaaaa a
SF=0 ; PC ← PC + 3 ( branch condition not satisified )
PC Original PC value + 3
(2) Subroutine instruction:
SCALL a
Object code: 1110 nnnn
Condition : PC ← a ; a=8n+6 ; n=1..Fh ; a=86h, n=0
PC00000aaaaa aaa
LCALL a
Object code: 0100 0aaa aaaa aaaa
Condition: PC ← a
* This specification are subject to be changed without notice.
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Preliminary
PC00aaaaaaaaaa a
RET
Object code: 0100 1111
Condition: PC ← STACK[SP]; SP + 1
PC The return address stored in stack
RT I
Object code: 0100 1101
Condition : FLAG. PC ← STACK[SP]; EI ← 1; SP + 1
PC The return address stored in stack
(3) Interrupt acceptance operation:
When an interrupt is accepted, the original PC is pushed into stack and interrupt vector will be loaded into
PC. The interrupt vectors are as follows :
INT0 (External interrupt from P8.2)
PC00000000000 1 0
SPI (speech end interrupt)
PC000000000010 0
TRGA (Timer A overflow interrupt)
PC0000000000 1 1 0
TRGB (Time B overflow interrupt)
PC00000000 0 1 0 0 0
TBI (Time base interrupt)
PC00000000 0 1 0 1 0
INT1 (External interrupt from P8.0)
PC00000000 0 1 1 0 0
(4) Reset operation:
PC00000000000 0 0
* This specification are subject to be changed without notice.
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Preliminary
(5) Other operations:
For 1-byte instruction execution: PC + 1
For 2-byte instruction execution: PC + 2
For 3-byte instruction execution: PC + 3
ACCUMULATOR
Accumulator(ACC) is a 4-bit data register for temporary data storage. For the arithematic, logic and
comparative opertion.., ACC plays a role which holds the source data and result.
FLAGS
There are three kinds of flag, CF ( Carry flag ), ZF ( Zero flag ) and SF ( Status flag ), these three 1-bit flags
are included by the arithematic, logic and comparative .... operation.
All flags will be put into stack when an interrupt subroutine is served, and the flags will be restored after
RTI instruction is executed.
(1) Carry Flag ( CF )
The carry flag is affected by the following operations:
a. Addition : CF as a carry out indicator, under addition operation, when a carry-out occures, the CF is "1",
likewise, if the operation has no carry-out, CF is "0".
b. Subtraction : CF as a borrow-in indicator, under subtraction operation, when a borrow occures, the CF
is "0", likewise, if there is no borrow-in, the CF is "1".
c. Comparision : CF as a borrow-in indicator for Comparision operation as in the subtraction operation.
d. Rotation : CF shifts into the empty bit of accumulator for the rotation and holds the shift out data after
rotation.
e. CF test instruction : Under TFCFC instruction, the CF content is sent into SF then clear itself as "0".
Under TTSFC instruction, the CF content is sent into SF then set itself as "1".
(2) Zero Flag ( ZF )
ZF is affected by the result of ALU, if the ALU operation generates a "0" result, the ZF is "1", likewise, the
ZF is "0".
(3) Status Flag ( SF )
The SF is affected by instruction operation and system status.
a. SF is initiated to "1" for reset condition.
b. Branch instruction is decided by SF, when SF=1, branch condition is satisified, likewise, when SF = 0,
branch condition is unsatisified.
* This specification are subject to be changed without notice.
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PROGRAM EXAMPLE:
Preliminary
Check following arithematic operation for CF, ZF, SF
CF ZF SF
LDIA #00h; - 1 1
LDIA #03h; - 0 1
ADDA #05h; - 0 1
ADDA #0Dh; - 0 0
ADDA #0Eh; - 0 0
ALU
The arithematic operation of 4-bit data is performed in ALU unit. There are 2 flags that can be affected by
the result of ALU operation, ZF and SF. The operation of ALU is affected by CF only.
ALU STRUCTURE
ALU supported user arithematic operation functions, including Addition, Subtraction and Rotaion.
DATA BUS
ALU
ZF CF SF
ALU FUNCTION
(1) Addition:
ALU supports addition function with instructions ADDAM, ADCAM, ADDM #k, ADD #k,y .... .
The addition operation affects CF and ZF. Under addition operation, if the result is "0", ZF will be "1",
otherwise, ZF will be "0". When the addition operation has a carry-out, CF will be "1", otherwise, CF will
be "0".
EXAMPLE:
Operation Carry Zero
3+4=7 0 0
7+F=6 1 0
0+0=0 0 1
8+8=0 1 1
(2) Subtraction:
ALU supports subtraction function with instructions SUBM #k, SUBA #k, SBCAM, DECM... . The
subtraction operation affects CF and ZF. Under subtraction operation, if the result is negative, CF will
be "0", and a borrow out, otherwise, if the result is positive, CF will be "1". For ZF, if the result of subtraction
operation is "0", the ZF is "1", likewise, ZF is "1".
* This specification are subject to be changed without notice.
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EXAMPLE:
Preliminary
Operation Carry Zero
8-4=4 1 0
7-F= -8(1000) 0 0
9-9=0 1 1
(3) Rotation:
Two types of rotation operation are available, one is rotation left, the other is rotation right.
RLCA instruction rotates Acc value counter-clockwise, shift the CF value into the LSB bit of Acc and hold
the shift out data in CF.
MSB LSB
ACC
CF
RRCA instruction operation rotates Acc value clockwise, shift the CF value into the MSB bit of Acc and
hold the shift out data in CF.
MSB LSB
ACC
CF
PROGRAM EXAMPLE: To rotate Acc clockwise (right) and shift a "1" into the MSB bit of Acc.
TTCFS; CF ← 1
RRCA; rotate Acc right and shift CF=1 into MSB.
HL REGISTER
HL register are two 4-bit registers, they are used as a pair of pointer for the RAM memoryaddress. They are
used as also 2 independent temporary 4-bit data registers. For certain instructions, L register can be a pointer
to indicate the pin number (Port4 only).
HL REGISTER STRUCTURE
3 2 1 0
H REGISTER
3 2 1 0
L REGISTER
HL REGISTER FUNCTION
(1) HL register is used as a temporary register for instructions : LDL #k, LDH #k, THA, THL, INCL, DECL,
EXAL, EXAH.
PROGRAM EXAMPLE:
LDL #05h;
LDH #0Dh;
Load immediate data "5h" into L register, "0Dh" into H register.
(2) HL register is used as a pointer for the address of RAM memory for instructions : LDAM, STAM, STAMI ..
PROGRAM EXAMPLE: Store immediate data "#0Ah" into RAM of address 35h.
* This specification are subject to be changed without notice.
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EM73A89B
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Preliminary
LDL #5h;
LDH #3h;
STDMI #0Ah; RAM[35] ← Ah
(3) L register is used as a pointer to indicate the bit of I/O port for instructions : SELP, CLPL, TFPL,
(When LR = 0 indicate P4.0)
PROGRAM EXAMPLE: To set bit 0 of Port4 to "1"
LDL #00h;
SEPL ; P4.0 ← 1
STACK POINTER (SP)
Stack pointer is a 4-bit register that stores the present stack level number.
Before using stack, user must set the SP value first, CPU will not initiate the SP value after reset condition.
When a new subroutine is received, the SP is decreased by one automatically, likewise, if returning from a
subroutine, the SP is increased by one.
The data transfer between ACC and SP is done with instructions "LDASP" and "STASP".
DATA POINTER (DP)
Data pointer is a 12-bit register that stores the ROM address can indicating the ROM code data specified
by user (refer to data ROM).
CLOCK AND TIMING GENERATOR
The clock generator is supported by a dual clock system. The high-frequency oscillator is internal oscillator.
The low-frequency oscillator may be sourced from crystal, the working frequency is 32 KHz.
CLOCK GENERATOR STRUCTURE
There are two clock generator for system clock control unit, P14 is the status register that hold the CPU
status. P16, P19 and P22 are the command register for system clock mode control.
CLK
LXIN
LXOUT
High-frequency
generator
Low-frequency
generator
fc
System clock
fs
mode control
P14
P16
P19
P22
LXIN
LXOUT
Crystal connection
VDD
* This specification are subject to be changed without notice.
System control
R
LXIN
open
RC oscillator connection
R=2.2MΩ
LXOUT
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
SYSTEM CLOCK MODE CONTROL
Preliminary
The system clock mode controller can start or stop the high-frequency and low-frequency clock oscillator
and switch between the basic clocks. EM73A89B has four operation modes (DUAL, SLOW, IDLE and
STOP operation modes).
RESET
operation
Reset
Reset
I/O wakeup
Reset
Reset release
STOP
operation
mode
NORMAL
operation
mode
Command
(P16)
Reset
Command
High osc : stopped
Low osc : stopped
High osc : oscillating
Low osc : oscillating
Command
(P22)
(P22)
Command
(P19)
Command
(P16)
SLOW
operation
mode
High osc : stopped
Low osc : oscillating
I/O or internal timer wakeup
IDLE
(CPU
stops)
High osc : stopped
Low osc : oscillating
Operation Mode Oscillator System Clock Available function One instruction cycle
NORMAL High, Low frequency High frequency clock LCD, speech, HTC. 8 / fc
SLOW Low frequency Low frequency clock LCD, HTC 4 / fs
IDLE Low frequency CPU stops LCD STOP None CPU stops All disable -
DUAL OPERATION MODE
The 4-bit µc is in the DUAL operation mode when the CPU is reseted. This mode is dual clock system
(high-frequency and low-frequency clocks oscillating). It can be changed to SLOW or STOP operation
mode with the command register (P22 or P16).
LCD display, speech synthesizer and sound generator are available for the DUAL operation mode.
SLOW OPERATION MODE
The SLOW operation mode is single clock system (low-frequency clock oscillating). It can be changed to
the DUAL operation mode with the command register (P22), STOP operation mode with P16 and IDEL
operation mode with P19.
LCD display is available for the SLOW operation mode. Speech synthesizer and sound generator are
disabled in this mode.
* This specification are subject to be changed without notice.
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
P22 3210 Initial value : ***0
Preliminary
* * * SOM
SOM Select operation mode
0 DUAL operation mode
1 SLOW operation mode
P14 32 10 Initial value : 0000
ACT WKS SINT CPUS
CPUS CPU status WKS Wakeup status
0 DUAL operation mode 0 Wakeup not by internal timer
1 SLOW operation mode 1 Wakeup by internal timer
Port14 is the status register for CPU. P14.0 (CPU status) is a read-only bit. P14.2 (wakeup status) will be
set as "1" when CPU is waked by internal timer. P14.2 will be cleared as "0" when user out data to P14.
P14.1 is the interrupt source selector (refer to interrupt). P14.3 is the speech acknowledge signal (refer to
speech synthesizer control).
IDLE OPERATION MODE
The IDLE operation mode suspends all CPU functions except the low-frequency clock oscillation and the
LCD driver. It keeps the internal status with low power consumption without stopping the slow clock
oscillator and LCD display.
LCD display is available for the IDLE operation mode. The high speed counter and speech synthesizer are
disabled in this mode. The IDLE operation mode will be wakeup and return to the SLOW operation mode by
the internal timing generator or I/O pins (P0(0..3)/WAKEUP 0..3 and P8(0..3)/WAKEUPA..D).
P19 32 10 Initial value : 0000
IDME SIDR
IDME Enable IDLE mode SIDR Select IDLE releasing condition
0 1 Enable IDLE mode 0 0 P0(0..3), P8(0..3) pin input
* * no function 0 1 P0(0..3), P8(0..3) pin input and 1 sec signal
1 0 P0(0..3), P8(0..3) pin input and 0.5 sec signal
1 1 P0(0..3), P8(0..3) pin input and 15.625 ms signal
STOP OPERATION MODE
The STOP operation mode suspends system operation and holds the internal status immediately before the
suspension with low power consumption. This mode will be released by reset or I/O pins (P0(0..3)/
WAKEUP 0..3 or P8(0..3)/WAKEUP A..D).
LCD display, high speed counter and speech synthesizer are disabled in this mode.
* This specification are subject to be changed without notice.
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EM73A89B
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Preliminary
P16 3210 Initial value : *000
* SWWT
SWWT Enable STOP mode
1 0 1 Enable STOP mode
* * * no function
GENERAL PURPOSE REGISTER (P10)
P10 is a 4-bit general purpose register which can be read, written and rested by all I/O instructions.
(including : INA, INM, OUT, OUTA, OUTM, SEP, CLP, TTP, TFP)
PROGRAM EXAMPLE:
CHIP ROM16K
;--------RAM define area-----------------
DSEG
ORG 10H
HLBUF: RES 2 ; HL buffer for interrupt
P9BUF: RES 1 ; P9 (RAM bank) buffer for interrupt
:
;----------Interrupt subroutine--------------------
CSEG
ORG 004H
LBR S PI
:
SPI: OUTA P10 ; save Acc to general purpose register P10
INA P9
OUT #0000B,P9 10 instruction bytes
STA P9BUF ; save RAM bank to P9BUF
EXHL HLBUF ; save HL to HLBUF
:
:
EXHL HLBUF ; restore HLBUF to HL
LDA P9BUF ; resotre P9BUF to RAM bank 10 instruction bytes
OUTA P9
INA P10 ; restore register P10 to Acc
RTI
* This specification are subject to be changed without notice.
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