ELAN EM73963A Datasheet
GENERAL DESCRIPTION
EM73963A is an advanced single chip CMOS 4-bit micro-controller. It contains 16K-byte ROM, 372-nibble
RAM, 4-bit ALU, 13-level subroutine nesting, 22-stage time base, two 12-bit timer/counters for the kernel
function. EM73963A also equipped with 5 interrupt sources, 3 I/O ports (including 1 input port and 2 bidirection
ports), LCD display (40x8), built-in sound generator.
It's low power consumption and high speedfeature are further strengten with DUAL, SLOW, IDLE and STOP
operation mode for optimized power saving.
FEATURES
Operation voltage : 2.4V to 5.5V.
Clock source : Dual clock system. Low-frequency oscillator is Crystal or RC oscillator (32KHz,
Oscillation frequency : 480K, 1M, 2M and 4M Hz are both available for high frequency clock by mask option.
Instruction set : 107 powerful instructions.
Instruction cycle time : Up to 2 µs for 4 MHz (high speed clock).
ROM capacity : 16K X 8 bits.
RAM capacity : 372 X 4 bits.
Input port : 1 port (P0.0-P0.3), IDLE/STOP releasing function is available by mask option.(each
Bidirection port : 2 ports (P4, P8). P4.0 and SOUND are available by mask option. IDLE/STOP release
12-bit timer/counter : Two 12-bit timer/counters are programmable for timer, event counter and pulse width
Built-in time base counter : 22 stages.
Subroutine nesting : Up to 13 levels.
Interrupt : External . . . . . 2 input interrupt sources.
LCD driver : 40 X 8 dots, 1/8 duty, 1/5 bias.
Sound effect : Tone generator, random generator and volume control.
Power saving function :SLOW, IDLE, STOP operation modes.
Package type : Chip form 69 pins.
EM73963A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
connect a external resistor) by mask option and high-frequency oscillator is RC
oscillator (connect a external resistor and a capacitor).
External clock and internal clock is available by mask option.
244 µs for 32768 Hz (low speed clock).
input pin has a pull-up and pull-down resistor available by mask option).
function for P8(0..3) is available by mask option.
measurement mode.
Internal . . . . . . 2 Timer overflow interrupts.
1 Time base interrupt.
* This specification are subject to be changed without notice.
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FUNCTION BLOCK DIAGRAM
RESET
CLK
LXIN
EM73963A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
LXOUT
V1~V4
Reset
Control
Interrupt
Control
Time
Base
LCD Driver
COM0~COM7
Timer/Counter
(TA,TB)
SEG0~SEG39
Clock
Generator
Instruction Decoder
Instruction Register
ROM
PC
SOUND GEN.
SOUND
System Control
Data Bus
Timing
Generator
Data pointer
ACC
ALU
Flag
ZCS
I/O Control
Clock Mode
Control
Stack pointer
Stack
RAM
HR
LR
P4.0/SOUND
P8.2(INT0)/WAKEUPC
P8.0(INT1)/WAKEUPA
P8.1(TRGB)/WAKEUPB
P8.3(TRGA)/WAKEUPD
P0.0/WAKEUP0
P0.1/WAKEUP1
P0.2/WAKEUP2
P0.3/WAKEUP3
PIN DESCRIPTIONS
Symbol Pin-type Function
V
DD
V
SS
RESET RESET-A System reset input signal, low active
CLK OSC-C RC or external clock source connecting pin for high speed clock source.
LXIN OSC-B/OSC-F Crystal/RC connecting pin for low speed clock source.
LXOUT OSC-B/OSC-F Crystal/RC connecting pin for low speed clock source.
P0(0..3)/WAKEUP0..3 INPUT-B 4-bit input port with IDLE/STOP releasing function
P4.0/SOUND I/O-O 1-bit bidirection I/O port or inverse sound effect output
P8.0(INT1)/WAKEUPA I/O-L 2-bit bidirection I/O port with external interrupt sources input and IDLE
P8.2(INT0)/WAKEUPC /STOP releasing function
Power supply (+)
Power supply (-)
mask option : none
pull-up
mask option : wakeup enable, pull-up
wakeup enable, none
wakeup disable, pull-up
wakeup disable, pull-down
wakeup disable, none
mask option : SOUND enable, push-pull, high current PMOS
SOUND disable, open-drain
SOUND disable, push-pull, high current PMOS
SOUND disable, push-pull, low current PMOS
mask option : wakeup enable, push-pull
wakeup disable, push-pull
wakeup disable, open-drain
* This specification are subject to be changed without notice.
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EM73963A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Symbol Pin-type Function
P8.1(TRGB)/WAKEUPB I/O-L 2-bit bidirection I/O port with time/counter A,B external input and IDLE
P8.3(TRGA)/WAKEUPD /STOP releasing function
mask option : wakeup enable, push-pull
wakeup disable, push-pull
wakeup disable, open-drain
SOUND Built-in sound effect output
V1, V2, V3, V4 LCD bias voltage input
COM0~COM7 LCD common output pins
SEG0~SEG39 LCD segment output pins
TEST Tie VSS as package type, no connecting as COB type
FUNCTION DESCRIPTIONS
PROGRAM ROM ( 16K X 8 bits )
16 K x 8 bits program ROM contains user's program and some fixed data.
The basic structure of the program ROM may be categorized into 5 partitions.
1. Address 0000h: Reset start address.
2. Address 0002h - 000Ch : 5 kinds of interrupt service routine entry addresses.
3. Address 000Eh-0086h : SCALL subroutine entry address, only available at 000Eh,0016h,001Eh,0026h, 002Eh,
0036h, 003Eh, 0046h, 004Eh, 0056h, 005Eh, 0066h, 006Eh, 0076h, 007Eh,0086h.
4. Address 0000h - 07FFh : LCALL subroutine entry address.
5. Address 0000h - 1FFFh : Except used as above function, the other region can be used as user's program and
data region.
address Bank 0 :
0000h Reset start address
0002h INT0; interrupt service routine entry address
0004h Reserved
0006h TRGA
0008h TRGB
000Ah TBI
000Ch INT1
000Eh
0086h
.
.
.
.
.
.
SCALL, subroutine call entry address
07FFh
0800h
Subroutine call entry address
designated by [LCALL a]
instruction
0FFFh
1000h
Bank 1
1FFFh
Bank 2
Bank 3
* This specification are subject to be changed without notice.
Data table for
[LDAX],[LDAXI]
instruction
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EM73963A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
User's program and fixed data are stored in the program ROM. User's program is executed using the PC value
to fetch an instruction code.
The 16Kx8 bits program ROM can be divided into 4 banks. There are 4Kx8 bits per bank.
The program ROM bank is selected by P3(1..0). The program counter is a 13-bit binary counter. The PC
and P3 are initialized to "0" during reset.
When P3(1..0)=00B, the bank0 and bank1 of program ROM will be selected. P3(1..0)=01B, the bank0 and
bank2 will be selected.
Address P3=xx00B P3=xx01B P3=xx10B
0000h
:
: Bank0 Bank0 Bank0
0FFFh
1000h
:
: Bank1 Bank2 Bank3
1FFFh
PROGRAM EXAMPLE:
BANK 0
START: :
:
:
LDIA #00H ; set program ROM to bank1
OUTA P3
B XA1
:
XA : :
:
LDIA #01H ; set program ROM to bank2
OUTA P3
B XB1
:
XB : :
:
LDIA #02H ; set program ROM to bank3
OUTA P3
B XC1
:
XC : :
:
BXD
XD : :
:
:
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BANK 1
XA1 : :
:
BXA
:
XA2 : :
* This specification are subject to be changed without notice.
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EM73963A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
B XA2
:
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BANK 2
XB1 : :
:
BXB
:
XB2 : :
B XB2
:
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BANK 3
XC1 : :
:
BXC
:
XC2 : :
B XC2
Fixed data can be read out by table-look-up instruction. Table-look-up instruction requires the Data point
(DP) to indicate the ROM address in obtaining the ROM code data (Except bank 0) :
LDAX Acc
LDAXI Acc
←←
← ROM[DP]
←←
←←
← ROM[DP]
←←
L
,DP+1
H
DP is a 12-bit data register that stores the program ROM address as pointer for the ROM code data.
User has to initially load ROM address into DP with instructions "STADPL", and "STADPM, STADPH",
then to obtain the lower nibble of ROM code data by instruction "LDAX" and higher nibble by instruction
"LDAXI"
PROGRAM EXAMPLE: Read out the ROM code of address 1777h by table-look-up instruction.
LDIA #07h;
STADPL ; [DP]
STADPM ; [DP]
STADPH ; [DP]
:
OUT #00H , P3 ; Set in bank 1
LDL #00h;
LDH #03h;
LDAX ; ACC ← 6h
STAMI ; RAM[30] ← 6h
LDAXI ; ACC ← 5h
STAM ; RAM[31] ← 5h
;
ORG 1777h
DATA 56h;
← 07h
L
← 07h
M
← 07h, Load DP=777h
H
DATA RAM (372-nibble )
A total 372 - nibble data RAM is available from address 000 to 17Fh
Data RAM includes the zero page region, stacks and data area.
* This specification are subject to be changed without notice.
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Bank 0
Bank 1
Address
000h - 00Fh
010h - 01Fh
020h - 02Fh
:
:
:
0C0h - 0CFh
0D0h - 0DFh
0E0h - 0EFh
0F0h - 0F3h
100h - 10Fh
110h - 11Fh
:
:
:
160h - 16Fh
Increment
Level 0
Level 4
Level 8
Level 12
Zero-page
Level 1
Level 5
Level 9
Level 2
Level 6
Level 10
Increment
Level 3
Level 7
Level 11
170h - 17Fh
ZERO- PAGE:
From 000h to 00Fh is the zero-page location. It is used as the zero-page address mode pointer for the
instruction of "STD #k,y; ADD #k,y; CLR y,b; CMP k,y".
PROGRAM EXAMPLE: To wirte immediate data "07h" to RAM [03] and to clear bit 2 of RAM [0Eh].
STD #07h, 03h ; RAM[03] ← 07h
CLR 0Eh,2 ; RAM[0Eh]
← 0
2
STACK:
There are 13 - level (maximum) stack levels that user can use for subroutine (including interrupt and CALL).
User can assign any level be the starting stack by providing the level number to stack pointer (SP).
When an instruction (CALL or interrupt) is invoked, before enter the subroutine, the previous PC address is
saved into the stack. Until returned from those subroutines, the PC value is restored by the data saved in stack.
DATA AREA:
Except the area used by user's application, the whole RAM can be used as data area for storing and loading
general data.
ADDRESSING MODE
The 372 nibble data memory consists of two banks (bank 0 and bank 1). There are 244x4 bits (address
000h~0F3h) in bank 0 and 128x4 bits (address 100h~17Fh) in bank 1.
* This specification are subject to be changed without notice.
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EM73963A
R
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
The bank is selected by P9.3. When P9.3 is cleared to "0", the bank 0 is selected, when P9.3 is set to "1", the bank
1 is selected.
The data Memory consists of three Address mode, namely -
(1) Indirect addressing mode:
The address in the bank is specified by the HL registers.
P9.3 HR LR
AM address
PROGRAM EXAMPLE: Load the data of RAM address "143h" to RAM address "023h".
SEP P9,3 ; P9.3← 1
LDL #3h ; LR← 3
LDH #4h ; HR← 4
LDAM ; Acc← RAM[134h]
CLP P9,3 ; P9.3← 0
LDL #2h ; LR← 2
LDH #3h ; HR← 3
STAM ; RAM[023h]← Acc
(2) Direct addressing mode:
The address in the bank is directly specified by 8 bits of the second byte in the instruction field.
instruction field
xxxxxxxx
P9.3
RAM address
PROGRAM EXAMPLE: Load the data of RAM address "143h" to RAM address "023h".
SEP P9,3 ; P9.3← 1
LDA 43h ; Acc← RAM[143h]
CLP P9,3 ; P9.3← 0
STA 23h ; RAM[023h]← Acc
(3) Zero-page addressing mode:
The zero-page is in the bank 0 (address 000h~00Fh). The address is the lower 4 bits of the second byte in the
instruction field.
xxxxxxxx
instruction field
yyyy
RAM address
0
0000
yyyy
PROGRAM EXAMPLE: Write immediate "0Fh" to RAM address "005h".
STD #0Fh, 05h ; RAM[05h]← 0Fh
* This specification are subject to be changed without notice.
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
PROGRAM COUNTER (16K ROM)
Program counter ( PC ) is composed by a 13-bit counter, which indicates the next executed address for the
program ROM instruction.
For BRANCH and CALL instructions, PC is changed by instruction indicating. PC only can indicate the address
from 0000h-1FFFh. The bank number is decided by P3.
(1) Branch instruction:
SBR a
Object code: 00aa aaaa
Condition: SF=1; PC ← PC
PC Hold original PC value+1 aaaaaa
SF=0; PC← PC +1( branch condition not satisified)
PC Original PC value + 1
( branch condition satisified )
12-6.a
LBR a
Object code: 1100 aaaa aaaa aaaa
Condition: SF=1; PC ← PC
Hold
PC
a a a a a a aaaaaa
+2
( branch condition satisified )
12.a
SF=0; PC← PC +2( branch condition not satisified)
PC Original PC value + 2
SLBR a
Object code: 0101 0101 1100 aaaa aaaa aaaa (a:1000h~1FFFh)
0101 0111 1100 aaaa aaaa aaaa (a:0000h~0FFFh)
Condition: SF=1; PC ← a ( branch condition satisified)
PCaaaaaaaaaaaa a
SF=0 ; PC ← PC + 3 ( branch condition not satisified )
PC Original PC value + 3
(2) Subroutine instruction:
SCALL a
Object code: 1110 nnnn
Condition : PC ← a ; a=8n+6 ; n=1..Fh ; a=86h, n=0
PC00000aaaaa aaa
LCALL a
Object code: 0100 0aaa aaaa aaaa
Condition: PC ← a
* This specification are subject to be changed without notice.
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
PC00aaaaaaaaaa a
RET
Object code: 0100 1111
Condition: PC ← STACK[SP]; SP + 1
PC The return address stored in stack
RT I
Object code: 0100 1101
Condition : FLAG. PC ← STACK[SP]; EI ← 1; SP + 1
PC The return address stored in stack
(3) Interrupt acceptance operation:
When an interrupt is accepted, the original PC is pushed into stack and interrupt vector will be loaded into
PC,The interrupt vectors are as follows :
INT0 (External interrupt from P8.2)
PC00000000000 1 0
TRGA (Timer A overflow interrupt)
PC0000000000 1 1 0
TRGB (Time B overflow interrupt)
PC00000000 0 1 0 0 0
TBI (Time base interrupt)
PC00000000 0 1 0 1 0
INT1 (External interrupt from P8.0)
PC00000000 0 1 1 0 0
(4) Reset operation:
PC00000000000 0 0
(5) Other operations:
For 1-byte instruction execution: PC + 1
For 2-byte instruction execution: PC + 2
For 3-byte instruction execution: PC + 3
* This specification are subject to be changed without notice.
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ACCUMULATOR
Accumulator is a 4-bit data register for temporary data storage. For the arithematic, logic and comparative
opertion .., ACC plays a role which holds the source data and result.
FLAGS
There are three kinds of flag, CF ( Carry flag ), ZF ( Zero flag ), and SF ( Status flag ), these three 1-bit flags
are included by the arithematic, logic and comparative .... operation.
All flags will be put into stack when an interrupt subroutine is served, and the flags will be restored after
RTI instruction is executed.
(1) Carry Flag ( CF )
The carry flag is affected by the following operations :
a. Addition : CF as a carry out indicator, under addition operation, when a carry-out occures, the CF is "1",
likewise, if the operation has no carry-out, the CF is "0".
b. Subtraction : CF as a borrow-in indicator, under subtraction operation, when a borrow occures, the CF
is "0", likewise, if there is no borrow-in, the CF is "1".
c. Comparision: CF as a borrow-in indicator for Comparision operation as the same as subtraction
operation.
d. Rotation: CF shifts into the empty bit of accumulator for the rotation and holds the shift out data after
rotation.
e. CF test instruction : Under TFCFC instruction, the CF content is sent into SF then clear itself as "0".
Under TTSFC instruction, the CF content is sent into SF then set itself as "1".
(2) Zero Flag ( ZF )
ZF is affected by the result of ALU, if the ALU operation generates a "0" result, the ZF is "1",
likewise, the ZF is "0".
(3) Status Flag ( SF )
The SF is affected by instruction operation and system status.
a. SF is initiated to "1" for reset condition.
b. Branch instruction is decided by SF, when SF=1, branch condition is satisified, likewise,
when SF=0, branch condition is unsatisified.
PROGRAM EXAMPLE:
Check following arithematic operation for CF, ZF, SF
CF ZF SF
LDIA #00h; - 1 1
LDIA #03h; - 0 1
ADDA #05h; - 0 1
ADDA #0Dh; - 0 0
ADDA #0Eh; - 0 0
* This specification are subject to be changed without notice.
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
ALU
The arithematic operation of 4 - bit data is performed in ALU unit . There are 2 flags that can be affected by
the result of ALU operation, ZF and SF. The operation of ALU is affected by CF only.
ALU STRUCTURE
ALU supported user arithematic operation functions, including Addition, Subtraction and Rotaion.
DATA BUS
ALU
ZF CF SF
ALU FUNCTION
(1) Addition:
ALU supports addition function with instructions ADDAM, ADCAM, ADDM #k, ADD #k,y .... .
The addition operation affects CF and ZF. Under addition operation, if the result is "0", ZF will be "1",
otherwise, ZF will be "0", When the addition operation has a carry-out, CF will be "1", otherwise, CF will
be "0".
EXAMPLE:
Operation Carry Zero
3+4=7 0 0
7+F=6 1 0
0+0=0 0 1
8+8=0 1 1
(2) Subtraction:
ALU supports subtration function with instructions SUBM #k, SUBA #k, SBCAM, DECM.... The
subtraction operation affects CF and ZF, Under subtraction operation, if the result is negative, CF will be "0",
and a borrow out, otherwise, if the result is positive, CF will be "1". For ZF, if the result of subtraction
operation is "0", the ZF is "1", otherwise, ZF is "1".
EXAMPLE:
Operation Carry Zero
8-4=4 1 0
7-F= -8(1000) 0 0
9-9=0 1 1
* This specification are subject to be changed without notice.
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(3) Rotation:
There are two kinds of rotation operation, one is rotation left, the other is rotation right.
RLCA instruction rotates Acc value to left, shift the CF value into the LSB bit of Acc and the shift out data
will be hold in CF.
MSB LSB
ACC
CF
RRCA instruction operation rotates Acc value to right, shift the CF value into the MSB bit of Acc and the
shift out data will be hold in CF.
MSB LSB
ACC
CF
PROGRAM EXAMPLE: To rotate Acc clockwise(right) and shift a "1" into the MSB bit of Acc.
TTCFS; CF ← 1
RRCA; rotate Acc right and shift CF=1 into MSB.
HL REGISTER
HL register are two 4-bit registers, they are used as a pair of pointer for the of RAM memory address. They
are used as also 2 independent temporary 4-bit data registers. For certain instructions, L register can be a pointer
to indicate the pin number (Port4 only).
HL REGISTER STRUCTURE
3 2 1 0
H REGISTER
HL REGISTER FUNCTION
(1) HL register is used as a temporary register for instructions : LDL #k, LDH #k, THA, THL, INCL, DECL,
EXAL, EXAH.
3 2 1 0
L REGISTER
PROGRAM EXAMPLE:
LDL #05h;
LDH #0Dh;
(2) HL register is used as a poiner for the address of RAM memory for instructions : LDAM, STAM, STAMI... .
PROGRAM EXAMPLE: Store immediate data "#0Ah" into RAM of address 35h.
LDL #5h;
LDH #3h;
STDMI #0Ah; RAM[35] ← Ah
* This specification are subject to be changed without notice.
Load immediate data "5h" into L register, "0Dh" into H register.
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