ELAN EM73962AH Datasheet

1

* This specification are subject to be changed without notice.

EM73962AEM73962A

EM73962A

4-BIT MICROCONTROLLER4-BIT MICROCONTROLLER

4-BIT MICROCONTROLLER

10.8.2001

GENERAL DESCRIPTIONGENERAL DESCRIPTION

GENERAL DESCRIPTION

EM73962A is an advanced single chip CMOS 4-bit micro-controller. It contains 16K-byte ROM, 372-nibble RAM, 4-bit ALU, 13-level subroutine nesting, 22-stage time base, two 12-bit timer/counters for the kernal function. EM73962A also contains 5 interrupt sources, 3 I/O ports (including 1 input port and 2 bidirection ports), LCD display (40x8), built-in sound generator. Except low-power consumption and high speed, EM73962A also have a sleep mode for power saving function. EM73962A is suitable for appliaction in many fields, for example : family appliance, consumer products, hand held games and the toy controller ... etc.

FEATURESFEATURES

FEATURES

• Operation voltage : 2.4V to 5.0V.

• Clock source : Single clock system using RC. oscillator. External clock and internal clock is available by mask option.

• Oscillation frequency : 480K, 1M, 2M and 4M Hz is available by mask option.

• Instruction set : 107 powerful instructions.

• Instruction cycle time : Up to 2us for 4 MHz.

• ROM capacity : 16384 X 8 bits.

• RAM capacity : 372 X 4 bits.

• Input port : 1 port (P0.0-P0.3) and sleep/hold releasing function are available by mask option. (each input pin is pull-up and pull-down resistor available by mask option).

• Bidirection port : 1 port (P8). P8(0..3) and sleep/hold releasing function are available by mask option.

• 12-bit timer/counter : Two 12-bit timer/counters are programmable for timer, event counter and pulse width measurement.

• Built-in time base counter : 22 stages.

• Subroutine nesting : Up to 13 levels.

• Interrupt : External . . . . . 2 input interrupt sources.

Internal . . . . . . 2 Timer overflow interrupts.

1 Time base interrupt.

• LCD driver : 40 X 8 dots, 1/8 duty, LCD bias is 1/4 and 1/5 available by mask option, LCD bias resistor is 20K X 5 and 10K X 5 available by mask option.

• Sound effect : Tone generator, random generator and volume control.

• Power saving function: Sleep mode and Hold mode.

• Package type : EM73962AH Chip form 62 pins.

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* This specification are subject to be changed without notice.

EM73962AEM73962A

EM73962A

4-BIT MICROCONTROLLER4-BIT MICROCONTROLLER

4-BIT MICROCONTROLLER

10.8.2001

SymbolSymbol

Symbol

Pin-type Pin-type

Pin-type

FunctionFunction

Function

V

DD

Power supply (+)

Vs s Power supply (-) RESET RESET-A System reset input signal, low active

mask option : none

pull-up

CLK OSC-C RC or external clock source connecting pin P0.(0..3)/WAKEUP0..3 INPUT-B 4-bit input port with Sleep/Hold releasing function

mask option : wakeup enable, pull-up

wakeup enable, none wakeup disable, pull-up wakeup disable, pull-down

wakeup disable, none P8.0(INT1)/WAKEUPA I/O-L 2-bit bidirection I/O port with external interrupt sources input and Sleep P8.2(INT0)/WAKEUPC /Hold releasing function

mask option : wakeup enable, push-pull

wakeup disable, push-pull

wakeup disable, open-drain P8.1(TRGB)/WAKEUPB I/O-L 2-bit bidirection I/O port with time/counter A,B external input and Sleep P8.3(TRGA)/WAKEUPD /Hold releasing function

mask option : wakeup enable, push-pull

wakeup disable, push-pull

wakeup disable, open-drain SOUND Built-in sound effect output COM0~COM7 LCD common output pins SEG0~SEG39 LCD segment output pins TEST No connecting for COB

FUNCTION BLOCK DIAGRAMFUNCTION BLOCK DIAGRAM

FUNCTION BLOCK DIAGRAM

PIN DESCRIPTIONSPIN DESCRIPTIONS

PIN DESCRIPTIONS

Interrupt

Control

Time Base

Timer/Counter

(TA,TB)

System Control

Instruction Decoder Instruction Register

ROM

PC

Data Bus

Reset

Control

Clock

Generator

Timing

Generator

Sleep Mode

Control

Data pointer

ACC

ALU

Flag

ZCS

Stack pointer

Stack ROM

HR

LR

I/O Control

P0.0/WAKEUP0 P0.1/WAKEUP1 P0.2/WAKEUP2 P0.3/WAKEUP3

P8.0(INT1)/WAKEUPA

P8.1(TRGB)/WAKEUPB

P8.2(INT0)/WAKEUPC

P8.3(TRGA)/WAKEUPD

RESET

CLK

SOUND GEN.

LCD Driver

COM0~COM7

SOUND

SEG0~SEG39

3

* This specification are subject to be changed without notice.

EM73962AEM73962A

EM73962A

4-BIT MICROCONTROLLER4-BIT MICROCONTROLLER

4-BIT MICROCONTROLLER

10.8.2001

SCALL, subroutine call entry address

Data table for [LDAX],[LDAXI] instruction

Subroutine call entry address designated by [LCALL a] instruction

FUNCTION DESCRIPTIONSFUNCTION DESCRIPTIONS

FUNCTION DESCRIPTIONS

PROGRAM ROM ( 16K X 8 bits ) for EM73962APROGRAM ROM ( 16K X 8 bits ) for EM73962A

PROGRAM ROM ( 16K X 8 bits ) for EM73962A

16 K x 8 bits program ROM contains user's program and some fixed data. The basic structure of program ROM can be divided into 4 parts.

1. Address 0000h: Reset start address.

2. Address 0002h - 000Ch : 5 kinds of interrupt service routine entry addresses.

3. Address 000Eh - 0086h : SCALL subroutine entry address, only available at 000Eh, 0016h, 001Eh, 0026h, 002Eh, 0036h, 003Eh, 0046h, 004Eh, 0056h, 005Eh, 0066h, 006Eh, 0076h, 007Eh, 0086h.

4. Address 0000h - 07FFh : LCALL subroutine entry address.

5. Address 0000h - 1FFFh : Except used as above function, the other region can be used as user's program region.

address Bank 0 :

0000h Reset start address 0002h INT0; interrupt service routine entry address 0004h 0006h TRGA 0008h TRGB 000Ah TBI 000Ch INT1 000Eh 0086h

: :

07FFh 0800h

0FFFh

1000h

Bank 1

1FFFh

Bank 2

Bank 3

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* This specification are subject to be changed without notice.

EM73962AEM73962A

EM73962A

4-BIT MICROCONTROLLER4-BIT MICROCONTROLLER

4-BIT MICROCONTROLLER

10.8.2001

User's program and fixed data are stored in the program ROM. User's program is according the PC value to send next executed instruction code. The 16Kx8 bits program ROM can be divided into 4 banks. There are 4Kx8 bits in each bank. The bank of the program ROM is selected by P3(1..0). The program counter is a 13-bit binary counter. The PC and P3 are initialized to "0" during reset. When P3(1..0)=00B, the bank0 and bank1 of program ROM will be selected. P3(1..0)=01B, the the bank0 and bank2 will be selected. P3(1..0)=01B, the bank0 and bank3 will be selected.

Address P3=xx00B P3=xx01B P3=xx10b

0000h

: : Bank0 Bank0 Bank0

0FFFh

1000h

: : Bank1 Bank2 Bank3

1FFFh

PROGRAM EXAMPLE:

BANK 0

START: :

: : LDIA #00H ; set program ROM to bank1 OUTA P3 B XA1 :

XA : :

: LDIA #01H ; set program ROM to bank2 OUTA P3 B XB1 :

XB : :

: LDIA #02H ; set program ROM to bank3 OUTA P3 B XC1 :

XC : :

: BXD

XD : :

: :

; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

BANK 1

XA1 : :

: BXA :

XA2 : :

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* This specification are subject to be changed without notice.

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EM73962A

4-BIT MICROCONTROLLER4-BIT MICROCONTROLLER

4-BIT MICROCONTROLLER

10.8.2001

B XA2 :

; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

BANK 2

XB1 : :

: BXB :

XB2 : :

B XB2 :

; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

BANK 3

XC1 : :

: BXC :

XC2 : :

B XC2

Fixed data can be read out by table-look-up instruction. Table-look-up instruction is depended on the Data Pointer (DP) to ROM address, then to get the ROM code data :

LDAXLDAX

LDAX

Acc Acc

Acc

←←

←

ROM[DP] ROM[DP]

ROM[DP]

LL

L

LDAXILDAXI

LDAXI

Acc Acc

Acc

←←

←

ROM[DP] ROM[DP]

ROM[DP]

HH

H

,DP+1,DP+1

,DP+1

DP is a 12-bit data register which can store the program ROM address to be the pointer for the ROM code data. First, user load ROM address into DP by instruction "STADPL, STADPM, STADPH", then user can get the lower nibble of ROM code data by instruction "LDAX" and higher nibble by instruction "LDAXI" PROGRAM EXAMPLE: Read out the ROM code of address 1777h by table-look-up instruction.

LDIA #07h; STADPL ; [DP]L ← 07h STADPM ; [DP]M ← 07h STADPH ; [DP]H ← 07h, Load DP=777h : LDL #00h; LDH #03h; LDAX ; ACC ← 6h STAMI ; RAM[30] ← 6h LDAXI ; ACC ← 5h STAM ; RAM[31] ← 5h ; ORG 1777h DATA 56h;

DATA RAM ( 372-nibble ) DATA RAM ( 372-nibble )

DATA RAM ( 372-nibble )

There is total 372 - nibble data RAM from address 000 to 17Fh Data RAM includes 3 parts: zero page region, stacks and data area.

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* This specification are subject to be changed without notice.

EM73962AEM73962A

EM73962A

4-BIT MICROCONTROLLER4-BIT MICROCONTROLLER

4-BIT MICROCONTROLLER

10.8.2001

ZERO- PAGE:

From 000h to 00Fh is the location of zero-page. It is used as the pointer in zero -page addressing mode for the instruction of "STD #k,y; ADD #k,y; CLR y,b; CMP k,y".

PROGRAM EXAMPLE: To wirte immediate data "07h" to address "003h" of RAM and to clear bit 2 of RAM.

STD #07h, 03h ; RAM[03] ← 07h CLR 0Eh,2 ; RAM[0Eh]2 ← 0

STACK:

There are 13 - level (maximum) stack for user using for subroutine (including interrupt and CALL). User can assign any level be the starting stack by giving the level number to stack pointer(SP). When user using any instruction of CALL or subroutine, before entry the subroutine, the previous PC address will be saved into stack until return from those subroutines, the PC value will be restored by the data saved in stack.

DATA AREA:

Except the special area used by user, the whole RAM can be used as data area for storing and loading general data.

ADDRESSING MODE

The 372 nibble data memory consists of two banks (bank 0 and bank 1). There are 244x4 bits (address 000h~0F3h) on bank 0 and 128x4 bits (address 100h~17Fh) on bank 1.

Increment

Address

020h - 02Fh

0C0h - 0CFh

0D0h - 0DFh

0E0h - 0EFh

Level 0 Level 4 Level 8

Level 12

Level 1 Level 5 Level 9

Level 2 Level 6

Level 10

Level 3 Level 7

Level 11

Increment

Zero-page

000h - 00Fh 010h - 01Fh

0F0h - 0F3h

: : :

110h - 11Fh

160h - 16Fh

170h - 17Fh

100h - 10Fh

: : :

Bank 0

Bank 1

7

* This specification are subject to be changed without notice.

EM73962AEM73962A

EM73962A

4-BIT MICROCONTROLLER4-BIT MICROCONTROLLER

4-BIT MICROCONTROLLER

10.8.2001

P9.3

instruction field

RAM address

xxxxxxxx

0

instruction field

R

AM address

yyyy

0000

yyyy

There are three addressing modes in the data memory :

(1) Indirect addressing mode:

The bank is selected by P9.3. When P9.3 is cleared to "0", the bank 0 is selected. When P9.3 is set to "1", the bank 1 is selected. The address in the bank are specified by the HL registers.

PROGRAM EXAMPLE: Load the data of RAM address "143h" to RAM address "023h".

SEP P9,3 ; P9.3← 1 LDL #3h ; LR← 3 LDH #4h ; HR← 4 LDAM ; Acc← RAM[134h] CLP P9,3 ; P9.3← 0 LDL #2h ; LR← 2 LDH #3h ; HR← 3 STAM ; RAM[023h]← Acc

(2) Direct addressing mode:

The bank is selected by P9.3. When P9.3 is cleared to "0", the bank 0 is selected. When P9.3 is set to "1", the bank 1 is selected. The address in the bank are directly specified by 8 bits of the second byte in the instruction field.

PROGRAM EXAMPLE: Load the data of RAM address "143h" to RAM address "023h".

SEP P9,3 ; P9.3← 1 LDA 43h ; Acc← RAM[134h] CLP P9,3 ; P9.3← 0 STA 23h ; RAM[023h]← Acc

(3) Zero-page addressing mode:

The zero-page is the bank 0 (address 000h~00Fh). The address are the lower 4 bits of the second byte in the instruction field.

PROGRAM EXAMPLE: Write immediate "0Fh" to RAM address "005h".

STD #0Fh, 05h ; RAM[05h]← 0Fh

P9.3 HR LR

R

AM address

8

* This specification are subject to be changed without notice.

EM73962AEM73962A

EM73962A

4-BIT MICROCONTROLLER4-BIT MICROCONTROLLER

4-BIT MICROCONTROLLER

10.8.2001

+2

PROGRAM COUNTER (16K ROM) for EM73962APROGRAM COUNTER (16K ROM) for EM73962A

PROGRAM COUNTER (16K ROM) for EM73962A

Program counter ( PC ) is composed by a 13-bit counter, which indicates the next executed address for the instruction of program ROM. For a 8K - byte size ROM, PC can indicate address form 0000h - 1FFFh, for BRANCH and CALL instrcutions, PC is changed by instruction indicating.

(1) Branch instruction:(1) Branch instruction:

(1) Branch instruction:

SBR aSBR a

SBR a

Object code: 00aa aaaa Condition: SF=1; PC ← PC

12-6.a

( branch condition satisified )

PC Hold original PC value+1 aaaaaa

SF=0; PC← PC +1( branch condition not satisified )

PC Original PC value + 1

LBR aLBR a

LBR a

Object code: 1100 aaaa aaaa aaaa Condition: SF=1; PC ← PC

12.a

( branch condition satisified )

PC

Hold

a a a a a aaaaaaa

SF=0; PC← PC +2( branch condition not satisified )

PC Original PC value + 2

SLBR aSLBR a

SLBR a

Object code: 0101 0101 1100 aaaa aaaa aaaa (a:1000h~1FFFh)

0101 0111 1100 aaaa aaaa aaaa (a:0000h~0FFFh)

Condition: SF=1; PC ← a ( branch condition satisified)

PCaaaaaaaaaaaa a

SF=0 ; PC ← PC + 3 ( branch condition not satisified )

PC Original PC value + 3

(2) Subroutine instruction:(2) Subroutine instruction:

(2) Subroutine instruction:

SCALL aSCALL a

SCALL a

Object code: 1110 nnnn Condition : PC ← a ; a=8n+6 ; n=1..Fh ; a=86h, n=0

PC00000aaaaa11 0

LCALL aLCALL a

LCALL a

Object code: 0100 0aaa aaaa aaaa Condition: PC ← a

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* This specification are subject to be changed without notice.

EM73962AEM73962A

EM73962A

4-BIT MICROCONTROLLER4-BIT MICROCONTROLLER

4-BIT MICROCONTROLLER

10.8.2001

PC00aaaaaaaaaa a

RETRET

RET

Object code: 0100 1111 Condition: PC ← STACK[SP]; SP + 1

PC The return address stored in stack

RT IRT I

RT I

Object code: 0100 1101 Condition : FLAG. PC ← STACK[SP]; EI ← 1; SP + 1

PC The return address stored in stack

(3) Interrupt acceptance operation:(3) Interrupt acceptance operation:

(3) Interrupt acceptance operation:

When an interrupt is accepted, the original PC is pushed into stack and interrupt vector will be loaded into PC,The interrupt vectors are as following:

INT0INT0

INT0 (External interrupt from P8.2)

PC00000000000 1 0

TRGATRGA

TRGA (Timer A overflow interrupt)

PC0000000000 1 1 0

TRGBTRGB

TRGB (Time B overflow interrupt)

PC00000000 0 1 0 0 0

TBI TBI

TBI (Time base interrupt)

PC00000000 0 1 0 1 0

INT1INT1

INT1 (External interrupt from P8.0)

PC00000000 0 1 1 0 0

(4) Reset operation:(4) Reset operation:

(4) Reset operation:

PC00000000000 0 0

(5) Other operations:(5) Other operations:

(5) Other operations:

For 1-byte instruction execution: PC + 1 For 2-byte instruction execution: PC + 2 For 3-byte instruction execution: PC + 3

10

* This specification are subject to be changed without notice.

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EM73962A

4-BIT MICROCONTROLLER4-BIT MICROCONTROLLER

4-BIT MICROCONTROLLER

10.8.2001

ACCUMULATORACCUMULATOR

ACCUMULATOR

Accumulator is a 4-bit data register for temporary data. For the arithematic, logic and comparative opertion .., ACC plays a role which holds the source data and result.

FLAGSFLAGS

FLAGS

There are three kinds of flag, CF ( Carry flag ), ZF ( Zero flag ), SF ( Status flag ), these 3 1-bit flags are affected

by the arithematic, logic and comparative .... operation.

All flags will be put into stack when an interrupt subroutine is served, and the flags will be restored after RTI instruction executed.

(1) Carry Flag ( CF )

The carry flag is affected by following operation: a. Addition : CF as a carry out indicator, when the addition operation has a carry-out, CF will be "1",

in another word, if the operation has no carry-out, CF will be "0".

b. Subtraction : CF as a borrow-in indicator, when the subtraction operation must has a borrow, in the CF

will be "0", in another word, if no borrow-in, CF will be "1".

c. Comparision: CF is as a borrow-in indicator for Comparision operation as the same as subtraction

operation.

d. Rotation: CF shifts into the empty bit of accumulator for the rotation and holds the shift out data after

rotation.

e. CF test instruction : For TFCFC instruction, the content of CF sends into SF then clear itself "0".

For TTSFC instruction, the content of CF sends into SF then set itself "1".

(2) Zero Flag ( ZF )

ZF is affected by the result of ALU, if the ALU operation generate a "0" result, the ZF will be "1", otherwise, the ZF will be "0".

(3) Status Flag ( SF )

The SF is affected by instruction operation and system status.

a. SF is initiated to "1" for reset condition.

b. Branch instruction is decided by SF, when SF=1, branch condition will be satisified, otherwise,

branch condition will not be satisified by SF = 0.

PROGRAM EXAMPLE:

Check following arithematic operation for CF, ZF, SF

CF ZF SF

LDIA #00h; - 1 1 LDIA #03h; - 0 1 ADDA #05h; - 0 1 ADDA #0Dh; - 0 0 ADDA #0Eh; - 0 0

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* This specification are subject to be changed without notice.

EM73962AEM73962A

EM73962A

4-BIT MICROCONTROLLER4-BIT MICROCONTROLLER

4-BIT MICROCONTROLLER

10.8.2001

ALUALU

ALU

The arithematic operation of 4 - bit data is performed in ALU unit. There are 2 flags can be affected by the result of ALU operation, ZF and SF. The operation of ALU can be affected by CF only.

ALU STRUCTUREALU STRUCTURE

ALU STRUCTURE

ALU supported user arithematic operation function, including : addition, subtraction and rotaion.

ALU FUNCTIONALU FUNCTION

ALU FUNCTION

(1) Addition:

For instruction ADDAM, ADCAM, ADDM #k, ADD #k,y .... ALU supports addition function.

The addition operation can affect CF and ZF. For addition operation, if the result is "0", ZF will be "1", otherwise, not equal "0", ZF will be "0", When the addition operation has a carry-out. CF will be "1", otherwise, CF will be "0".

EXAMPLE:

Operation C arry Zero 3+4=7 0 0 7+F=6 1 0 0+0=0 0 1 8+8=0 1 1

(2) Subtraction:

For instruction SUBM #k, SUBA #k, SBCAM, DECM... ALU supports user subtraction function. The subtraction operation can affect CF and ZF, For subtraction operation, if the result is negative, CF will be "0", it means a borrow out, otherwise, if the result is positive, CF will be "1". For ZF, if the result of subtraction operation is "0", the ZF will be "1", otherwise, ZF will be "1".

EXAMPLE:

Operation Carry Zero 8-4=4 1 0 7-F= -8(1000) 0 0 9-9=0 1 1

ZF CF SF

ALU

DATA BUS

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