ELAN EM73461A Datasheet
GENERAL DESCRIPTION
EM73461A is an advanced single chip CMOS 4-bit micro-controller. It contains 4K-byte ROM, 244-nibble RAM,
4-bit ALU, 13-level subroutine nesting, 22-stage time base, two 12-bit timer/counters for the kernel function.
EM73461A also contains 6 interrupt sources, 1 input port, 2 bidirection ports, LCD display (32x4), and one high
speed timer/counter with melody output.
EM73461A has plentiful operating modes (SLOW, IDLE, STOP) intended to reduce the power consumption.
FEATURES
• Operation voltage : 2.4V to 3.6V.
• Clock source : Dual clock system. Low-frequency oscillator is Crystal or RC oscillator (32K Hz,
• Instruction set : 109 powerful instructions.
• Instruction cycle time : Up to 2us for 4 MHz (high speed clock).
• ROM capacity : 4096 X 8 bits.
• RAM capacity : 244 X 4 bits.
• Input port : 1 port (P0). P0(0..3) and IDLE releasing function are available by mask option.
• Bidirection port : 2 ports (P4, P8). P4.0 and SOUND is available by mask option. P4.1 is shared with
• 12-bit timer/counter : Two 12-bit timer/counters are programmable for timer, event counter and pulse width
• High speed timer/counter : One 8-bit high speed timer/counters is programmable for auto load timer, melody
• Built-in time base counter : 22 stages.
• Subroutine nesting : Up to 13 levels.
• Interrupt : External . . . . . 2 input interrupt sources.
• LCD driver : 32 X 4 dots, 1/4,1/3,1/2 static six kinds of duty selectable, 1/2 bias, 1/3 bias.
• Power saving function : SLOW, IDLE, STOP operation mode.
• Package type : Chip form 61 pins.
EM73461A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Preliminary
connect an external resistor) by mask option and high-frequency oscillator is RC
oscillator (connect an external resistor).
122 µs or 244µs by frequency double mask option for 32768 Hz (low speed clock).
HTC external input. P8(0..3) and IDLE releasing function are available by mask
option.
measurement.
output and pulse width measurement.
Internal . . . . . . 2 Timer overflow interrupts, 1 time base interrupt.
1 high speed timer overflow interrupt.
APPLICATIONS
EM73461A is suitable for application in family applicance, consumer products, hand held games and the toy
controller.
* This specification are subject to be changed without notice.
1.5.2001
1
FUNCTION BLOCK DIAGRAM
EM73461A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Preliminary
VA
VB
V1
V2
V3
RESET
Reset
Control
Interrupt
Control
Time
Base
LCD
COM0~COM3
Generator
Instruction Decoder
Instruction Register
Timer/Counter
(TA,TB)
SEG0~SEG31
CLK
Clock
LXOUT
Generator
ROM
PC
DP
SP
HTC
SOUND
LXIN
Clock
(slow)
System Control
Data Bus
ZCS G
Timing
Generator
Data pointer
ACC
ALU
Flag
P4.0/SOUND
I/O Control
P4.2
P4.3
P4.1TRGH
Sleep Mode
Control
Stack pointer
Stack
ROM
HR
LR
P0.0/WAKEUP0
P0.1/WAKEUP1
P0.2/WAKEUP2
P0.3/WAKEUP3
P8.2(INT0)/WAKEUPC
P8.0(INT1)/WAKEUPA
P8.1(TRGB)/WAKEUPB
P8.3(TRGA)/WAKEUPD
PIN DESCRIPTIONS
Symbol Pin-type Function
V
DD
V
SS
RESET RESET-A System reset input signal, low active
CLK OSC-I RC clock source connecting pin
LXIN OSC-B/OSC-H1Crystal/RC connecting pin for low speed clock source
LXOUT OSC-B Crystal connecting pin for low speed clock source
P0(0..3)/WAKEUP0..3 INPUT-K 4-bit input port with IDLE releasing function
P4.0/SOUND I/O-R 1-bit bidirection I/O port or inverse sound effect output
Power supply (+)
Power supply (-)
mask option : none
pull-up
mask option : wakeup enable, negative edge release, pull-up
wakeup enable, negative edge release, none
wakeup enable, positive edge release, pull-down
wakeup enable, positive edge release, none
wakeup disable, pull-up
wakeup disable, pull-down
wakeup disable, none
mask option : SOUND enable, high current push-pull
SOUND disable, open-drain
* This specification are subject to be changed without notice.
1.5.2001
2
EM73461A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Preliminary
PIN DESCRIPTIONS
Symbol Pin-type Function
SOUND disable, low current push-pull
SOUND disable, normal current push-pull
SOUND disable, high current push-pull
P4.1/TRGH I/O-Q 1-bit bidirection I/O port with HTC external input
mask option : NMOS open-drain
PMOS open-drain
low current push-pull
normal current push-pull
high current push-pull
P4(2,3) I/O-Q 2-bit bidirection I/O port with high current source
mask option : NMOS open-drain
PMOS open-drain
low current push-pull
normal current push-pull
high current push-pull
P8.0(INT1)/WAKEUPA, I/O-S 2-bit bidirection I/O port with external interrupt source input and IDLE
P8.2(INT0)/WAKEUPC releasing function
mask option : wakeup enable, low current push-pull
wakeup enable, normal current push-pull
wakeup disable, open-drain
wakeup disable, low current push-pull
wakeup disable, normal current push-pull
P8.1(TRGB)/WAKEUPB I/O-S 2-bit bidirection I/O port with time/counter A,B external input and IDLE
P8.3(TRGA)/WAKEUPD releasing function
mask option : wakeup enable, low current push-pull
wakeup enable, normal current push-pull
wakeup disable, open-drain
wakeup disable, low current push-pull
wakeup disable, normal current push-pull
SOUND Melody output
VA,VB, V1, V2, V3 Connect the capacitors for LCD bias voltage
COM0~COM3 LCD common output pins
SEG0~SEG31 LCD segment output pins
TEST Tie Vss as package type, no connecting as COB type.
FUNCTION DESCRIPTIONS
PROGRAM ROM (4K X 8 bits)
4 K x 8 bits program ROM contains user's program and some fixed data.
The basic structure of program ROM can be divided into 5 parts.
1. Address 000h: Reset start address.
2. Address 002h - 00Ch : 6 kinds of interrupt service routine entry addresses.
3. Address 00Eh-086h : SCALL subroutine entry address, only available at 00Eh,016h,01Eh,026h, 02Eh,
036h, 03Eh, 046h, 04Eh, 056h, 05Eh, 066h, 06Eh, 076h, 07Eh, 086h.
4. Address 000h - 7FFh : LCALL subroutine entry address.
5. Address 000h - FFFh : Except used as above function, the other region can be used as user's program region.
* This specification are subject to be changed without notice.
1.5.2001
3
EM73461A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
address 4096 x 8 bits
Preliminary
000h Reset start address
002h INT0; External interrupt service routine entry address
004h HTCI; High speed timer interrupt service entry address
006h TRGA; Timer/counterA interrupt service routine entry address
008h TRGB; Timer/counter B interrupt service routine entry address
00Ah TBI; Time base interrupt service routine entry address
00Ch INT1; External interrupt service routine entry address
00Eh
086h
.
.
.
FFFh
User's program and fixed data are stored in the program ROM. User's program is according the PC value
to send next executed instruction code. Fixed data can be read out by two ways.
(1) Table-look-up instruction :
Table -look-up instruction is depended on the Data Pointer (DP) to indicate to ROM address, then to get the
ROM code data.
LDAX Acc
LDAXI Acc
SCALL, subroutine call entry address
.
.
.
←←
← ROM[DP]
←←
←←
← ROM[DP]H,DP+1
←←
L
DP is a 12-bit data register which can store the program ROM address to be the pointer for the ROM code
data. First, user load ROM address into DP by instruction "STADPL, STADPM, STADPH", then user can
get the lower nibble of ROM code data by instruction "LDAX" and higher nibble by instruction "LDAXI".
PROGRAM EXAMPLE: Read out the ROM code of address 777h by table-look-up instruction.
LDIA #07h;
STADPL ; DP3-0 ← 07h
STADPM ; DP5-4 ← 07h
STADPH ; DP8-6 ← 07h, Load DP=777h
:
LDL #00h;
LDH #03h;
LDAX ; ACC ← 6h
STAMI ; RAM[30] ← 6h
LDAXI ; ACC ← 5h
STAM ; RAM[31] ← 5h
;
ORG 777h
DATA 56h;
:
DATA RAM ( 244-nibble )
There is total 244 - nibble data RAM from address 00 to F3h
Data RAM includes 3 parts: zero page region, stacks and data area.
* This specification are subject to be changed without notice.
1.5.2001
4
EM73461A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Preliminary
Increment
Address
00h~0Fh
10h~1Fh
20h~2Fh
30h~3Fh
40h~4Fh
:
B0h ~ BFh
C0h ~ CFh
D0h ~ DFh
E0h ~ EFh
F0h ~ F3h
level 0
level 4
level 8
level C
LCD display RAM:
RAM address from 20h ~ 3Fh are the LCD display RAM area, the RAM data of this region can't be operated
by instruction LDHL xx and EXHL.
zero page
LCD display RAM
level 1
level 5
level 9
level 2
level 6
level A
level 3
level17
level B
ZERO-PAGE:
From 00h to 0Fh is the location of zero-page. It is used as the pointer in zero-page addressing mode for the
instruction of "STD #k,y; ADD #k,y; CLR y,b; CMP k,y".
PROGRAM EXAMPLE: To wirte immediate data "07h" to address "03h" of RAM and to clear bit 2 of RAM.
STD #07h, 03h ; RAM[03] ← 07h
CLR 0Eh,2 ; RAM[0Eh]2 ← 0
STACK:
There are 13-level (maximum) stack for user using for subroutine (including interrupt and CALL). User can
assign any level be the starting stack by giving the level number to stack pointer (SP).
When user using any instruction of CALL or subroutine, before entry the subroutine, the previous PC address
will be saved into stack until return from those subroutines, the PC value will be restored by the data saved
in stack.
DATA AREA:
Except the special area used by user, the whole RAM can be used as data area for storing and loading general
data.
ADDRESSING MODE
(1) Indirect addressing mode:
Indirect addressing mode indicates the RAM address by specified HL register.
For example: LDAM ; Acc ← RAM[HL]
STAM ; RAM[HL] ← Acc
(2) Direct addressing mode:
Direct addressing mode indicates the RAM address by immediate data.
* This specification are subject to be changed without notice.
1.5.2001
5
EM73461A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Preliminary
For example:
(3) Zero-page addressing mode
For zero-page region, user can using direct addressing to write or do any arithematic, comparsion or bit
manupulated operation directly.
For example:
PROGRAM COUNTER (4K ROM)
Program counter ( PC ) is composed by a 12-bit counter, which indicates the next executed address for the
instruction of program ROM.
For a 4K - byte size ROM, PC can indicate address form 000h - FFFh, for BRANCH and CALL instrcutions,
PC is changed by instruction indicating.
(1) Branch instruction:
LDA x ; Acc← RAM[x]
STA x ; RAM[x] ← Acc
STD #k,y ; RAM[y] ← #k
ADD #k,y; RAM[y] ← RAM[y] + #k
SBR a
Object code: 00aa aaaa
Condition: SF=1; PC ← PC
( branch condition satisified )
11-6.a
PC Hold original PC value+1 aaaaaa
SF=0; PC← PC +1( branch condition not satisified )
PC Original PC value + 1
LBR a
Object code: 1100 aaaa aaaa aaaa
Condition: SF=1; PC ← a ( branch condition satisified )
PCaaaaaaaaaaaa
SF=0 ; PC ← PC + 2 ( branch condition not satisified )
PC Original PC value + 2
(2) Subroutine instruction:
SCALL a
Object code: 1110 nnnn
Condition : PC ← a ; a=8n+6 ; n=1..15 ; a=86h, n=0
PC0000aaaaaaaa
LCALL a
Object code: 0100 0 aaa aaaa aaaa
Condition: PC ← a
PC0aaaaaaaaaaa
* This specification are subject to be changed without notice.
1.5.2001
6
EM73461A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Preliminary
RET
Object code: 0100 1111
Condition: PC ← STACK[SP]; SP + 1
PC The return address stored in stack
RT I
Object code: 0100 1101
Condition : FLAG. PC ← STACK[SP]; EI ← 1; SP + 1
PC The return address stored in stack
(3) Interrupt acceptance operation:
When an interrupt is accepted, the original PC is pushed into stack and interrupt vector will be loaded into
PC,The interrupt vectors are as following:
INT0 (External interrupt from P8.2)
PC000000000010
TRGA (Timer A overflow interrupt)
PC000000000110
TRGB (Time B overflow interrupt)
PC000000001000
TBI (Time base interrupt)
PC000000001010
INT1 (External interrupt from P8.0)
PC000000001100
(4) Reset operation:
PC000000000000
(5) Other operations:
For 1-byte instruction execution: PC + 1
For 2-byte instruction execution: PC + 2
ACCUMULATOR
* This specification are subject to be changed without notice.
1.5.2001
7
EM73461A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Preliminary
Accumulator is a 4-bit data register for temporary data. For the arithematic, logic and comparative opertion
.., ACC plays a role which holds the source data and result.
FLAGS
There are four kinds of flag, CF ( Carry flag ), ZF ( Zero flag ), SF ( Status flag ) and GF ( General flag ),
these 4 1-bit flags are affected by the arithematic, logic and comparative .... operation.
All flags will be put into stack when an interrupt subroutine is served, and the flags will be restored after
RTI instruction executed.
(1) Carry Flag ( CF )
The carry flag is affected by following operation:
a. Addition : CF as a carry out indicator, when the addition operation has a carry-out, CF will be "1",
in another word, if the operation has no carry-out, CF will be "0".
b. Subtraction : CF as a borrow-in indicator, when the subtraction operation must has a borrow, in the CF
will be "0", in another word, if no borrow-in, CF will be "1".
c. Comparision: CF is as a borrow-in indicator for Comparision operation as the same as subtraction
operation.
d. Rotation: CF shifts into the empty bit of accumulator for the rotation and holds the shift out data after
rotation.
e. CF test instruction : For TFCFC instruction, the content of CF sends into SF then clear itself "0".
For TTSFC instruction, the content of CF sends into SF then set itself "1".
(2) Zero Flag ( ZF )
ZF is affected by the result of ALU, if the ALU operation generate a "0" result, the ZF will be "1",
otherwise, the ZF will be "0".
(3) Status Flag ( SF )
The SF is affected by instruction operation and system status.
a. SF is initiated to "1" for reset condition.
b. Branch instruction is decided by SF, when SF=1, branch condition will be satisified, otherwise,
branch condition will not be satisified by SF = 0.
(4) General Flag ( GF )
GF is a one bit general purpose register which can be set, clear, test by instruction SGF, CGF and TGS.
PROGRAM EXAMPLE:
Check following arithematic operation for CF, ZF, SF
* This specification are subject to be changed without notice.
1.5.2001
8
EM73461A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Preliminary
CF ZF SF
LDIA #00h; - 1 1
LDIA #03h; - 0 1
ADDA #05h; - 0 1
ADDA #0Dh; - 0 0
ADDA #0Eh; - 0 0
ALU
The arithematic operation of 4 - bit data is performed in ALU unit. There are 2 flags can be affected by the
result of ALU operation, ZF and SF. The operation of ALU can be affected by CF only.
ALU STRUCTURE
ALU supported user arithematic operation function, including : addition, subtraction and rotaion.
DATA BUS
ALU
ZF CF SF GF
ALU FUNCTION
(1) Addition:
For instruction ADDAM, ADCAM, ADDM #k, ADD #k,y .... ALU supports addition function.
The addition operation can affect CF and ZF. For addition operation, if the result is "0", ZF will be "1",
otherwise, not equal "0", ZF will be "0". When the addition operation has a carry-out, CF will be "1",
otherwise, CF will be "0".
EXAMPLE:
Operation Carry Zero
3+4=7 0 0
7+F=6 1 0
0+0=0 0 1
8+8=0 1 1
(2) Subtraction:
For instruction SUBM #k, SUBA #k, SBCAM, DECM... ALU supports user subtraction function. The
subtraction operation can affect CF and ZF, For subtraction operation, if the result is negative, CF will
be "0", it means a borrow out, otherwise, if the result is positive, CF will be "1". For ZF, if the result of
subtraction operation is "0", the ZF will be "1", otherwise, ZF will be "1".
* This specification are subject to be changed without notice.
1.5.2001
9
EM73461A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Preliminary
EXAMPLE:
Operation Carry Zero
8-4=4 1 0
7-F= -8(1000) 0 0
9-9=0 1 1
(3) Rotation:
There are two kinds of rotation operation, one is rotation left, the other is rotation right.
RLCA instruction rotates Acc value to left, shift the CF value into the LSB bit of Acc and the shift out data
will be hold in CF.
MSB LSB
ACC
CF
RRCA instruction operation rotates Acc value to right, shift the CF value into the MSB bit of Acc and the
shift out data will be hold in CF.
MSB LSB
ACC
CF
PROGRAM EXAMPLE: To rotate Acc right and shift a "1" into the MSB bit of Acc.
TTCFS; CF ← 1
RRCA; rotate Acc right and shift CF=1 into MSB.
HL REGISTER
HL register are two 4-bit registers, they are used as a pair of pointer for the address of RAM memory and also
2 independent temporary 4-bit data registers. For some instruction, L register can be a pointer to indicate the
pin number ( Port4 ).
HL REGISTER STRUCTURE
3 2 1 0
3 2 1 0
H REGISTER
HL REGISTER FUNCTION
* This specification are subject to be changed without notice.
L REGISTER
1.5.2001
10
Loading...