ELAN EM73361AAQ Datasheet

EM73361AEM73361A

EM73361A

EM73361AEM73361A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

GENERAL DESCRIPTIONGENERAL DESCRIPTION

GENERAL DESCRIPTION

GENERAL DESCRIPTIONGENERAL DESCRIPTION

EM73361A is an advanced single chip CMOS 4-bit micro-controller. It contains 3K-byte ROM, 52-nibble RAM,

4-bit ALU, 13-level subroutine nesting, 22-stage time base, two 12-bit timer/counters for the kernel function.
EM73361A also contains 3 interrupt sources, 1 input port, 4 bidirection I/O ports, built-in watch-dog-timer
counter, tone generator and LCD driver (27x3 to 13x3).

Except low-power consumption and high speed, EM73361A also have a sleep mode operation for power saving.

FEATURESFEATURES

FEATURES

FEATURESFEATURES

• Operation voltage : 2.2V to 3.6V(clock frequency : 32K Hz).

• Clock source : Single clock system for crystal, connect a external resistor or external clock
source available by mask option.

• Instruction set : 109 powerful instructions.

• Instruction cycle time : 122µs for 32K Hz.

• ROM capacity : 3072 X 8 bits.

• RAM capacity : 52 X 4 bits.

• Input port : 1 port (P0)(Pull-up and pull-down resistor with wakeup function available by
mask option).

• Bidirection port : 4 ports (P4, P5, P6, P7) are available by mask option. (each I/O pin is push-pull
and open-drain available by mask option) P4.0 is high current pin (P4.0 and
TONE available by mask option). P4.2~P4.3, P5, P6 and P7 are shared with
SEG26-SEG13 by mask option.

• 12-bit timer/counter : Two 12-bit timer/counters are programmable for timer mode.

• Low voltage reset (LVR) : Reset at 1.5V, and reset release at 1.8V.

• Tone generator : There is a built-in tone generator.

• Built-in time base counter : 22 stages.

• Subroutine nesting : Up to 13 levels.

• Interrupt : External . . . . . 2 External interrupt (INT0, INT1).

Internal . . . . . . 2 Timer overflow interrupts.

1 Time base interrupt.

• LCD driver : 27 X 3 to 13 X 3 dots available by mask option. Capacitor divider and resistor
divider are available by mask option.1/3, 1/2 and static three kinds of duty (1/2
bias) selectable. The programming method of LCD driver is I/O mapping.

• Built-in watch-dog-timer : The WDT is enabled or disabled by mask option.

• Power saving function : Sleep mode and Hold mode.

• Package type : EM73361AAH Chip form 46 pins.
EM73361AAQ QFP 100 pins.

APPLICATIONSAPPLICATIONS

APPLICATIONS

APPLICATIONSAPPLICATIONS

EM73361A is suitable for application in family appliance, consumer products, hand held games and the toy
controller.

* This specification are subject to be changed without notice.

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PIN CONFIGURATIONSPIN CONFIGURATIONS

PIN CONFIGURATIONS

PIN CONFIGURATIONSPIN CONFIGURATIONS

EM73361AEM73361A

EM73361A

EM73361AEM73361A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

NC
NC
NC

NC
P7.1/SEG15
P7.2/SEG14
P7.3/SEG13

SEG12
SEG11
SEG10

SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3

NC

NC

NC

NCNCNCNCNC

8079787776757473727170696867666564636261605958575655545352

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

100

123456789

NCNCNCNCNCNCNC

NC

NC

P6.2/SEG18

P6.1/SEG19

P7.0/SEG16

P6.3/SEG17

P5.2/SEG22

P5.1/SEG23

P6.0/SEG20

P5.3/SEG21

EM73361AAQ

QFP 100

101112131415161718192021222324252627282930

NC

NC

NC

SEG2

SEG1

SEG0

COM1

COM0

P4.3/SEG25

P4.2/SEG26

COM2

P5.0/SEG24

VB

VA

XIN

VEE

TESTNCNCNCNCNCNCNCNCNCNC

NCNCNCNCNCNCNCNCNC

XOUT

51

NC

50

NC

49

NC

48

NC

47

NC

46

NC

45

P4.1/WDT

44

P4.0/TONE

43

TONE

42

P0.3/WAKEUP3

41

P0.2(INT0)/WAKEUP2

40

P0.1/WAKEUP1

39

P0.0(INT1)/WAKEUP0

38

RESET

37

VDD

36

VSS

35

NC
NC

34
33

NC

32

NC

31

NC

* This specification are subject to be changed without notice.

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FUNCTION BLOCK DIAGRAMFUNCTION BLOCK DIAGRAM

FUNCTION BLOCK DIAGRAM

FUNCTION BLOCK DIAGRAMFUNCTION BLOCK DIAGRAM

EM73361AEM73361A

EM73361A

EM73361AEM73361A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

RESET

Reset

Control

Interrupt

Control

Time
Base

PIN DESCRIPTIONSPIN DESCRIPTIONS

PIN DESCRIPTIONS

PIN DESCRIPTIONSPIN DESCRIPTIONS

12-bit

timer

counter

(TA,TB)

XIN

Clock

Generator

Instruction Decoder
Instruction Register

XOUT

Frequency

doubler

System Control

ROM

PC

Data Bus

ZCS G

Timing

Generator

Data pointer

ACC

ALU

Flag

Sleep Mode

Stack pointer

HR

I/O Control

Control

Stack

RAM

LR

LCD

driver

Tone generator

WDT

P0.0(INT1)/WAKEUP0
P0.1/WAKEUP1
P0.2(INT0)/WAKEUP2
P0.3/WAKEUP3

VA
VB
VEE
COM0~COM2
SEG0~SEG12

P4,P5,P6,P7/SEG(26..13)

TONE

P4.0/TONE
P4.1/WDT

V

DD

V

SS

SymbolSymbol

Symbol

SymbolSymbol

Pin-typePin-type

Pin-type

Pin-typePin-type

Power supply (+)
Power supply (-)

FunctionFunction

Function

FunctionFunction

RESET RESET-A System reset input signal, low active

mask option : none

pull-up
XIN OSC-A/OSC-F Crystal/external resistor or external clock source connecting pin
XOUT OSC-A/OSC-F Crystal/external resistor connecting pin

P0.0(INT1)/WAKEUP0, INPUT-J 2-bit input port with external interrupt sources input and Sleep/Hold

P0.2(INT0)/WAKEUP2 releasing function

mask option : wakeup enable, pull-up

wakeup enable, none

wakeup disable, pull-up

wakeup disable, none

wakeup disable, pull-down
P0.1/WAKEUP1, INPUT-H 2-bit input port with Sleep/Hold releasing function
P0.3/WAKEUP3 mask option : wakeup enable, pull-up

wakeup enable, none

* This specification are subject to be changed without notice.

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EM73361AEM73361A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

SymbolSymbol

Symbol

SymbolSymbol

P4.0/TONE I/O-O 1-bit bidirection I/O pin or inverse tone generator output

P4.1/WDT I/O-D 1-bit bidirection I/O pin with watch-dog-timer output

P4(2..3)/SEG(26..25) I/O-P 4-bit bidirection I/O ports are shared with LCD segment pins
P5(0..3)/SEG(24..21) mask option : segment enable, open-drain
P6(0..3)/SEG(20..17) segment disable, push-pull
P7(0..3)/SEG(16..13) segment disable, open-drain

TONE Built-in tone generator output
VA, VB, VEE Connect the capacitors for LCD bias voltage
COM0~COM2 LCD common output pins
SEG0~SEG12 LCD segment output pins
TEST Tie Vss as package type, no connecting as COB type

FUNCTION DESCRIPTIONSFUNCTION DESCRIPTIONS

FUNCTION DESCRIPTIONS

FUNCTION DESCRIPTIONSFUNCTION DESCRIPTIONS

Pin-typePin-type

Pin-type

Pin-typePin-type

FunctionFunction

Function

FunctionFunction

wakeup disable, pull-up

wakeup disable, pull-down

wakeup disable, none

mask option : TONE enable, push-pull, high current PMOS

TONE disable, open-drain

TONE disable, push-pull, high current PMOS

TONE disable, push-pull, low current PMOS

mask option : open-drain

push-pull

PROGRAM ROM ( 3K X 8 bits )PROGRAM ROM ( 3K X 8 bits )

PROGRAM ROM ( 3K X 8 bits )

PROGRAM ROM ( 3K X 8 bits )PROGRAM ROM ( 3K X 8 bits )

3 K x 8 bits program ROM contains user's program and some fixed data .
The basic structure of program ROM can be divided into 4 parts.

1. Address 000h: Reset start address.

2. Address 002h - 00Ch: 4 kinds of interrupt service routine entry addresses .

3. Address 00Eh-086h : SCALL subroutine entry address, only available at 00Eh,016h,01Eh,026h, 02Eh,
036h, 03Eh, 046h, 04Eh, 056h, 05Eh, 066h, 06Eh, 076h ,07Eh, 086h .

4. Address 000h - 7FFh : LCALL subroutine entry address

5. Address 000h - BFFh : Except used as above function, the other region can be used as user's program region.

address 3072 x 8 bits
000h Reset start address
002h INT0 ; External interrupt service toutine entry address
004h
006h TRGA; Timer/counter A interrupt service routine entry address
008h TRGB; Timer/counter B interrupt service routine entry address
00Ah TBI; Time base interrupt service routine entry address
00Ch INT1; External interrupt service routine entry address
00Eh
086h

.

.

.

BFFh

SCALL, subroutine call entry address

* This specification are subject to be changed without notice.

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EM73361AEM73361A

EM73361A

EM73361AEM73361A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

User's program and fixed data are stored in the program ROM. User's program is according the PC value
to send next executed instruction code. Fixed data can be read out by table-look-up instruction.

Table-look-up instruction is depended on the Data Pointer ( DP ) to indicate to ROM address, then to get the
ROM code data.

LDAXLDAX

LDAX

LDAXLDAX
LDAXILDAXI

LDAXI

LDAXILDAXI

Acc Acc

Acc

Acc Acc
Acc Acc

Acc

Acc Acc

←←

ROM[DP] ROM[DP]

←

ROM[DP]

←←

ROM[DP] ROM[DP]

←←

ROM[DP] ROM[DP]

←

ROM[DP]

←←

ROM[DP] ROM[DP]

LL

L

LL

,DP+1,DP+1

,DP+1

,DP+1,DP+1

HH

H

HH

DP is a 12-bit data register which can store the program ROM address to be the pointer for the ROM code data.
First, user load ROM address into DP by instruction "STADPL, STADPM, STADPH", then user can get the
lower nibble of ROM code data by instruction "LDAX" and higher nibble by instruction "LDAXI".

PROGRAM EXAMPLE: Read out the ROM code of address 777h by table-look-up instruction.

LDIA #07h;
STADPL ; [DP]L ← 07h
STADPM ; [DP]M ← 07h
STADPH ; [DP]H ← 07h, Load DP=777h
:
LDL #00h;
LDH #03h;
LDAX ; ACC ← 6h
STAMI ; RAM[30] ← 6h
LDAXI ; ACC ← 5h
STAM ; RAM[31] ← 5h
;
ORG 777h
DATA 56h;
:

DATA RAM ( 52-nibble ) DATA RAM ( 52-nibble )

DATA RAM ( 52-nibble )

DATA RAM ( 52-nibble ) DATA RAM ( 52-nibble )

There is total 52 - nibble data RAM from address 00 to 33h
Data RAM includes 3 parts: zero page region, stacks and data area.

Increment

Address
00h - 0Fh
10h - 1Fh
20h - 2Fh
30h - 33h

Level 0
Level 4
Level 8
Level 12

Level 1

Level 2

Level 5

Level 6

Level 9

Level 10

Stack Zero-page

Level 3
Level 7
Level 11

ZERO- PAGE:

From 00h to 0Fh is the location of zero-page. It is used as the pointer in zero -page addressing mode for the
instruction of "STD #k,y; ADD #k,y; CLR y,b; CMP k,y".

PROGRAM EXAMPLE: To wirte immediate data "07h" to address "03h" of RAM and to clear bit 2 of RAM.

STD #07h, 03h ; RAM[03] ← 07h
CLR 0Eh,2 ; RAM[0Eh]2 ← 0

STACK:

There are 13 - level (maximum) stack for user using for subroutine (including interrupt and CALL). User
can assign any level be the starting stack by giving the level number to stack pointer (SP).

* This specification are subject to be changed without notice.

Increment

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EM73361AEM73361A

EM73361A

EM73361AEM73361A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

When user using any instruction of CALL or subroutine, before entry the subroutine, the previous PC address
will be saved into stack until return from those subroutines, the PC value will be restored by the data saved
in stack.

DATA AREA:

Except the special area used by user, the whole RAM can be used as data area for storing and loading general
data.

ADDRESSING MODE

(1) Indirect addressing mode:

Indirect addressing mode indicates the RAM address by specified HL register.
For example:

LDAM ; Acc ← RAM[HL]
STAM ; RAM[HL] ← Acc

(2) Direct addressing mode:

Direct addressing mode indicates the RAM address by immediate data.
For example: LDA x ; Acc← RAM[x]

STA x ; RAM[x] ← Acc

(3) Zero-page addressing mode

For zero-page region, user can using direct addressing to write or do any arithematic, comparsion or bit
manupulated operation directly.
For example: STD #k,y ; RAM[y] ← #k

ADD #k,y; RAM[y] ← RAM[y] + #k

PROGRAM COUNTER (3K ROM)PROGRAM COUNTER (3K ROM)

PROGRAM COUNTER (3K ROM)

PROGRAM COUNTER (3K ROM)PROGRAM COUNTER (3K ROM)

Program counter ( PC ) is composed by a 12-bit counter, which indicates the next executed address for the
instruction of program ROM.
For a 3K - byte size ROM, PC can indicate address form 000h - BFFh, for BRANCH and CALL instrcutions,

PC is changed by instruction indicating.

(1) Branch instruction:(1) Branch instruction:

(1) Branch instruction:

(1) Branch instruction:(1) Branch instruction:

SBR aSBR a

SBR a

SBR aSBR a

Object code: 00aa aaaa
Condition: SF=1; PC ← PC

( branch condition satisified )

11-6.a

PC Hold original PC value+1 aaaaaa

SF=0; PC← PC +1( branch condition not satisified)

PC Original PC value + 1

LBR aLBR a

LBR a

LBR aLBR a

Object code: 1100 aaaa aaaa aaaa
Condition: SF=1; PC ← a ( branch condition satisified)

PCaaaaaaaaaaaa

* This specification are subject to be changed without notice.

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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

SF=0 ; PC ← PC + 2 ( branch condition not satisified )

PC Original PC value + 2

(2) Subroutine instruction:(2) Subroutine instruction:

(2) Subroutine instruction:

(2) Subroutine instruction:(2) Subroutine instruction:

SCALL aSCALL a

SCALL a

SCALL aSCALL a

Object code: 1110 nnnn
Condition : PC ← a ; a=8n+6 ; n=1..15 ; a=86h, n=0

PC 0 0 0 0 a a a a a a a a

LCALL aLCALL a

LCALL a

LCALL aLCALL a

Object code: 0100 0aaa aaaa aaaa
Condition: PC ← a

PC0aaaaaaaaaaa

EM73361AEM73361A

EM73361A

EM73361AEM73361A

RETRET

RET

RETRET

Object code: 0100 1111
Condition: PC ← STACK[SP]; SP + 1

PC The return address stored in stack

RT IRT I

RT I

RT IRT I

Object code: 0100 1101
Condition : FLAG. PC ← STACK[SP]; EI ← 1; SP + 1

PC The return address stored in stack

(3) Interrupt acceptance operation:(3) Interrupt acceptance operation:

(3) Interrupt acceptance operation:

(3) Interrupt acceptance operation:(3) Interrupt acceptance operation:

When an interrupt is accepted, the original PC is pushed into stack and interrupt vector will be loaded into
PC,The interrupt vectors are as following:

INT0 INT0

INT0 (External interrupt from P0.2)

INT0 INT0

PC000000000010

TRGATRGA

TRGA (Timer A overflow interrupt)

TRGATRGA

PC000000000110

TRGBTRGB

TRGB (Time B overflow interrupt)

TRGBTRGB

PC000000001000

TBITBI

TBI (Time base interrupt)

TBITBI

PC000000001010

* This specification are subject to be changed without notice.

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EM73361AEM73361A

EM73361A

EM73361AEM73361A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

INT1 INT1

INT1 (External interrupt from P0.0)

INT1 INT1

PC000000001100

(4) Reset operation:(4) Reset operation:

(4) Reset operation:

(4) Reset operation:(4) Reset operation:

PC000000000000

(5) Other operations:(5) Other operations:

(5) Other operations:

(5) Other operations:(5) Other operations:

For 1-byte instruction execution: PC + 1
For 2-byte instruction execution: PC + 2

ACCUMULATORACCUMULATOR

ACCUMULATOR

ACCUMULATORACCUMULATOR

Accumulator is a 4-bit data register for temporary data . For the arithematic, logic and comparative opertion
.., ACC plays a role which holds the source data and result .

FLAGSFLAGS

FLAGS

FLAGSFLAGS

There are four kinds of flag, CF ( Carry flag ), ZF ( Zero flag ), SF ( Status flag ) and GF ( General flag ),

these 4 1-bit flags are affected by the arithematic, logic and comparative .... operation .

All flags will be put into stack when an interrupt subroutine is served, and the flags will be restored after
RTI instruction executed .

(1) Carry Flag ( CF )

The carry flag is affected by following operation:
a. Addition : CF as a carry out indicator, when the addition operation has a carry-out, CF will be "1",

in another word, if the operation has no carry-out, CF will be "0".

b. Subtraction : CF as a borrow-in indicator, when the subtraction operation must has a borrow, in the CF

will be "0", in another word, if no borrow-in, CF will be "1".

c. Comparision: CF is as a borrow-in indicator for Comparision operation as the same as subtraction

operation.

d. Rotation: CF shifts into the empty bit of accumulator for the rotation and holds the shift out data after

rotation.

e. CF test instruction : For TFCFC instruction, the content of CF sends into SF then clear itself "0".

For TTSFC instruction, the content of CF sends into SF then set itself "1".

(2) Zero Flag ( ZF )

ZF is affected by the result of ALU, if the ALU operation generate a "0" result, the ZF will be "1",
otherwise, the ZF will be "0".

(3) Status Flag ( SF )

The SF is affected by instruction operation and system status .

* This specification are subject to be changed without notice.

10.8.2001

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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

a. SF is initiated to "1" for reset condition .

b. Branch instruction is decided by SF, when SF=1, branch condition will be satisified, otherwise,
branch condition will not be satisified by SF = 0 .

(4) General Flag ( GF )

GF is a one bit general purpose register which can be set, clear, test by instruction SGF, CGF and TGS.

PROGRAM EXAMPLE:

Check following arithematic operation for CF, ZF, SF

CF ZF SF
LDIA #00h; - 1 1
LDIA #03h; - 0 1
ADDA #05h; - 0 1
ADDA #0Dh; - 0 0
ADDA #0Eh; - 0 0

ALUALU

ALU

ALUALU

EM73361AEM73361A

EM73361A

EM73361AEM73361A

The arithematic operation of 4 - bit data is performed in ALU unit . There are 2 flags can be affected by
the result of ALU operation, ZF and SF . The operation of ALU can be affected by CF only .

ALU STRUCTUREALU STRUCTURE

ALU STRUCTURE

ALU STRUCTUREALU STRUCTURE

ALU supported user arithematic operation function, including : addition, subtraction and rotaion.

DATA BUS

ALU

ZF CF SF GF

ALU FUNCTIONALU FUNCTION

ALU FUNCTION

ALU FUNCTIONALU FUNCTION

(1) Addition:

For instruction ADDAM, ADCAM, ADDM #k, ADD #k,y .... ALU supports addition function.

The addition operation can affect CF and ZF. For addition operation, if the result is "0", ZF will be "1",
otherwise, not equal "0", ZF will be "0", When the addition operation has a carry-out. CF will be "1",
otherwise, CF will be "0".

EXAMPLE:

Operation Carry Zero
3+4=7 0 0
7+F=6 1 0
0+0=0 0 1
8+8=0 1 1

(2) Subtraction:

For instruction SUBM #k, SUBA #k, SBCAM, DECM... ALU supports user subtraction function . The
subtraction operation can affect CF and ZF, For subtraction operation, if the result is negative, CF will

* This specification are subject to be changed without notice.

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EM73361AEM73361A

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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

be "0", it means a borrow out, otherwise, if the result is positive, CF will be "1". For ZF, if the result
of subtraction operation is "0", the ZF will be "1", otherwise, ZF will be "1".
EXAMPLE:

Operation Carry Zero
8-4=4 1 0
7-F= -8(1000) 0 0
9-9=0 1 1

(3) Rotation:

There are two kinds of rotation operation, one is rotation left, the other is rotation right.
RLCA instruction rotates Acc value to left, shift the CF value into the LSB bit of Acc and the shift out data
will be hold in CF.

MSB LSB

ACC

CF

RRCA instruction operation rotates Acc value to right, shift the CF value into the MSB bit of Acc and the
shift out data will be hold in CF.

MSB LSB

ACC

CF

PROGRAM EXAMPLE: To rotate Acc right and shift a "1" into the MSB bit of Acc .

TTCFS; CF ← 1
RRCA; rotate Acc right and shift CF=1 into MSB.

HL REGISTERHL REGISTER

HL REGISTER

HL REGISTERHL REGISTER

HL register are two 4-bit registers, they are used as a pair of pointer for the address of RAM memory and also
2 independent temporary 4-bit data registers. For some instruction, L register can be a pointer to indicate the
pin number ( Port4, Port6, Port7 ) .

HL REGISTER STRUCTUREHL REGISTER STRUCTURE

HL REGISTER STRUCTURE

HL REGISTER STRUCTUREHL REGISTER STRUCTURE

HL REGISTER FUNCTIONHL REGISTER FUNCTION

HL REGISTER FUNCTION

HL REGISTER FUNCTIONHL REGISTER FUNCTION

3 2 1 0

H REGISTER

3 2 1 0

L REGISTER

(1)For instruction : LDL #k, LDH #k, THA, THL, INCL, DECL, EXAL, EXAH, HL register used as a

temporary register .

PROGRAM EXAMPLE: Load immediate data "5h" into L register, "Dh" into H register.

LDL #05h;
LDH #0Dh;

(2) For instruction LDAM, STAM, STAMI .., HL register used as a pointer for the address of RAM memory.

* This specification are subject to be changed without notice.

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