ELAN EM73201CP, EM73201BK, EM73201AP Datasheet
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
GENERAL DESCRIPTION
EM73201 is an advanced single chip CMOS 4-bit micro-controller. It contains 2K-byte ROM, 52-nibble RAM,
4-bit ALU, 13-level subroutine nesting, 22-stage time base, one 12-bit timer/counter for the kernel function.
EM73201 also contains 5 interrupt sources, 4 I/O ports (including 1 input port, 1 output port for LED driving,
2 bidirection I/O ports) built-in watch-dog-time counter and one high frequency clock output for modulating
infrared signal.
Except low-power consumption and high speed, EM73201 also have a sleep and hold mode operation for the
power saving function.
EM73201 is suitable for application in family appliance, consumer products and toy controller.
FEATURES
Operation voltage : 2.4V to 6.0V (clock frequency: 32 KHz to 5 MHz)
Clock source : Single clock system for RC , Crystal and external clock source, available by
Instruction set : 109 powerful instructions.
Instruction cycle time : Up to 2µs for 4.19MHz .
ROM capacity : 2048 x 8 bits.
RAM capacity : 52 x 4 bits.
Input port : 1 port (P0).
Output port : 1 port (P1).
Bidirection I/O port : 2 ports (P7,P8).
12-bit timer/counter : One 12-bit timer/counter is programmable for timer, even counter and pulse
Built-in time base counter : 22 stages.
Subroutine nesting : Up to 13 levels.
Interrupt : External interrupt . . . . . . 2 input interrupt sources.
The built-in watch-dog-timer counter is available by mask option.
Low voltage reset is available by mask option.
High frequency clockout: Programmable high frequency clock output for modulating infrared signal.
Power saving function : Sleep mode and Hold mode.
Package type : EM73201H Chip form 22 pins.
EM73201
Preliminary
mask option.
width measurement mode.
Internal interrupt . . . . . . 1 timer overflow interrupt,
1 time base interrupt.
EM73201AP DIP 18 pins.
EM73201BK SKINNY 22 pins.
EM73201CP DIP 16 pins.
APPLICATIONS
EM73201 is suitable for application in family appliance, consumer products and the toy controller.
7.20.1999
1* This specification are subject to be changed without notice.
EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
PIN CONFIGURATIONS
EM73201AP
P8.3
P7.0
P7.1
P7.2
P7.3
P1.0
P1.1
P1.2
V
EM73201AP must enable low voltage reset
1
2
3
4
5
6
7
8
SS
9
18
17
16
15
14
13
12
11
10
V
DD
P8.2
XOUT
XIN
TEST
P0.3
P0.2
P0.1
P0.0
FUNCTIONAL BLOCK DIAGRAM
Preliminary
EM73201BK
P8.0
P8.3
P7.0
P7.1
P7.2
P7.3
P1.0
P1.1
P1.2
P1.3
V
1
2
3
4
5
6
7
8
9
10
SS
11
22
21
20
19
18
17
16
15
14
13
12
V
DD
P8.2
RESET
P8.1
XOUT
XIN
TEST
P0.3
P0.2
P0.1
P0.0
EM73201CP
V
DD
P7.0
P7.2
P7.3
P1.0
P1.1
P1.2
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
RESET
XOUT
XIN
TEST
P0.3
P0.2
P0.1
P0.0
9
RESET
Reset
Control
Interrupt
Control
Time
Base
Infrared Control
WDT
12 bits
timer
counter
XIN/CLK
Instruction Decoder
Instruction Register
XOUT/NC
Clock
Generator
ROM
PC
System Control
Data Bus
Timing
Generator
Data pointer
ACC
ALU
Flag
ZCS G
I/O Control
P1.1
P1.2
P1.3
P1.0/CLKOUT
Stack pointer
HR
P7.0
P7.1
Sleep Mode
Control
Stack
ROM
LR
P7.2
P7.3
P8.0/INT1
P8.1
P8.2/INT0
P0.0/WAKEUP0
P0.1/WAKEUP1
P0.2/WAKEUP2
P0.3/WAKEUP3
P8.3/TRGA
* This specification are subject to be changed without notice.
7.20.1999
2
EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
PIN DESCRIPTIONS
Symbol Pin- Type Function
V
DD Power supply (+)
Vss Power supply (-)
RESET RESET-A System reset input signal, low active
XIN/CLK OSC-A/OSC-C Crystal/RC or external clock source connecting pin
XOUT/NC OSC-A Crystal connecting pin or NC for RC osc. type
P(0..3)/WAKEUP0..3 INPUT-C 4-bit input port with Sleep/Hold releaseing func tion
P1.0/CLKOUT
P1(1..3)
P7(0..3) I/O-U 4-bit bidirection I/O port
P8.0/INT1,P8.2/INT0 I/O-W 2-bit bidirection I/O pins with external interrupt sources input
P8.3/TRGA I/O-V 1-bit bidirection I/O pin with timer/counter A external input
P8.1 I/O-W 1-bit bidirection I/O pin
OUTPUT-B 1-bit high current output pin for LED driving or clock output for
OUTPUT-A 3-bit high current output pin for LED driving
Preliminary
mask option: none
pull-up
mask option : none
pull-up
pull-down
infrared signal
mask option : open-drain, normal sink
open-drain, high sink
normal source, normal sink
normal source, high sink
mask option : open-drain, normal sink
open-drain, high sink
normal source, normal sink
normal source, high sink
mask option : open-drain, normal sink
low source, normal sink
normal source, normal sink
normal source, high sink
high source, high sink
mask option : open-drain, normal sink
low source, normal sink
normal source, normal sink
normal source, high sink
high source, high sink
mask option : open-drain, normal sink
low source, normal sink
normal source, normal sink
normal source, high sink
high source, high sink
mask option : open-drain, normal sink
low source, normal sink
normal source, normal sink
normal source, high sink
high source, high sink
7.20.1999
3* This specification are subject to be changed without notice.
EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
FUNCTION DESCRIPTIONS
Preliminary
PROGRAM ROM ( 2K X 8 bits )
2 K x 8 bits program ROM contains user's program and some fixed data .
The basic structure of program ROM can be divided into 5 parts.
1. Address 000h: Reset start address.
2. Address 002h - 00Ch: 4 kinds of interrupt service rountine entry addresses .
3. Address 00Eh-086h : SCALL subroutine entry address, only available at 00Eh,016h,01Eh,026h, 02Eh,
036h, 03Eh, 046h, 04Eh, 056h, 05Eh, 066h, 06Eh, 076h ,07Eh, 086h .
4. Address 000h - 7FFh : LCALL subroutine entry address
5. Address 7E0h - 7FFh : The data region for 5-to-8 bits data conversion table .
6. Address 000h - 7FFh : Except used as above function, the other region can be used as user's program region.
address 2048 x 8 bits
000h Reset start address
002h INT0; External interrupt service routine entry address
004h
006h TRGA, Timer/counterA interrupt service routine entry address
008h
00Ah TBI; Time base interrupt service routine entry address
00Ch INT1; External interrupt service routine entry address
00Eh
086h
.
.
.
7FFh
User's program and fixed data are stored in the program ROM. User's program is according the PC value
to send next executed instruction code. Fixed data can be read out by two ways.
SCALL, subroutine call entry address
.
.
.
(1) Table-look-up instruction:
Table-look-up instruction is depended on the Data Pointer ( DP ) to indicate to ROM address, then to get
the ROM code data.
LDAX Acc
LDAXI Acc
←←
← ROM[DP]
←←
←←
← ROM[DP]
←←
L
,DP+1
H
DP is a 12-bit data register which can store the program ROM address to be the pointer for the ROM
code data. First, user load ROM address into DP by instruction "STADPL, STADPM, STADPH",
then user can get the lower nibble of ROM code data by instruction "LDAX" and higher nibble by
instruction "LDAXI".
PROGRAM EXAMPLE: Read out the ROM code of address 777h by table-look-up instruction.
LDIA #07h;
STADPL ; [DP]
STADPM ; [DP]
STADPH ; [DP]
:
LDL #00h;
LDH #03h;
LDAX ; ACC ← 6h
← 07h
L
← 07h
M
← 07h, Load DP=777h
H
* This specification are subject to be changed without notice.
7.20.1999
4
EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
STAMI ; RAM[30] ← 6h
Preliminary
LDAXI ; ACC ← 5h
STAM ; RAM[31] ← 5h
:
ORG 777h
DATA 56h;
:
DATA RAM ( 52-nibble )
There is total 52 - nibble data RAM from address 00 to 33h
Data RAM includes 3 parts: zero page region, stacks and data area.
Increment
Address
00h - 0Fh
10h - 1Fh
20h - 2Fh
30h - 33h
Level 0
Level 4
Level 8
Level 12
Level 1
Level 5
Level 9
Stack Zero-page
Level 2
Level 6
Level 10
Level 3
Increment
Level 7
Level 11
ZERO- PAGE:
From 00h to 0Fh is the location of zero-page. It is used as the pointer in zero-page addressing mode for the
instruction of "STD #k,y; ADD #k,y; CLR y,b; CMP k,y".
PROGRAM EXAMPLE:
To wirte immediate data "07h" to address "03h" of RAM and to clear bit 2 of RAM.
STD #07h, 03h ; RAM[03] ← 07h
CLR 0Eh,2 ; RAM[0Eh]
← 0
2
STACK:
There are 13 - level (maximum) stack for user using for subroutine (including interrupt and CALL). User
can assign any level be the starting stack by giving the level number to stack pointer (SP).
When user using any instruction of CALL or subroutine, before entry the subroutine, the previous PC address
will be saved into stack until return from those subroutines, the PC value will be restored by the data saved
in stack.
DATA AREA:
Except the special area used by user, the whole RAM can be used as data area for storing and loading general
data.
ADDRESSING MODE
(1) Indirect addressing mode:
Indirect addressing mode indicates the RAM address by specified HL register.
For example:
LDAM ; Acc ← RAM[HL]
STAM ; RAM[HL] ← Acc
(2) Direct addressing mode:
Direct addressing mode indicates the RAM address by immediate data.
7.20.1999
5* This specification are subject to be changed without notice.
EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
Preliminary
For example: LDA x ; Acc← RAM[x]
STA x ; RAM[x] ← Acc
(3) Zero-page addressing mode
For zero-page region, user can using direct addressing to write or do any arithematic, comparsion
or bit manupulated operation directly.
For example:
PROGRAM COUNTER (2K ROM)
Program counter ( PC ) is composed by a 12-bit counter, which indicates the next executed address for the
instruction of program ROM.
For a 2 K - byte size ROM, PC can indicate address form 000h - 7FFh, for BRANCH and CALL instrcutions,
PC is changed by instruction indicating.
(1) Branch instruction:
STD #k,y ; RAM[y] ← #k
ADD #k,y; RAM[y] ← RAM[y] + #k
SBR a
Object code: 00aa aaaa
Condition: SF=1; PC ← PC
PC Hold original PC value+1 a aaaa a
SF=0; PC← PC +1( branch condition not satisified)
PC Original PC value + 1
LBR a
Object code: 1100 aaaa aaaa aaaa
Condition: SF=1; PC ← a ( branch condition satisified)
PC 0 a a a a a a a a a a a
SF=0 ; PC ← PC + 2 ( branch condition not satisified )
PC Original PC value + 2
(2) Subroutine instruction:
( branch condition satisified )
11-6.a
SCALL a
Object code: 1110 nnnn
Condition : PC ← a ; a=8n+6 ; n=1..15 ; a=86h, n=0
PC 0 0 0 0 a a a a a a a a
LCALL a
Object code: 0100 0 aaa aaaa aaaa
Condition: PC ← a
* This specification are subject to be changed without notice.
7.20.1999
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EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
Preliminary
PC0aaaaaaaaaaa
RET
Object code: 01 00 1 1 1 1
Condition: PC ← STACK[SP]; SP + 1
PC The return address stored in stack
RT I
Object code: 0100 1101
Condition : FLAG. PC ← STACK[SP]; EI ← 1; SP + 1
PC The return address stored in stack
(3) Interrupt acceptance operation:
When an interrupt is accepted, the original PC is pushed into stack and interrupt vector will be loaded into
PC,The interrupt vectors are as following:
INT0 (External interrupt from P8.2)
PC000000000010
TRGA (Timer A overflow interrupt)
PC000000000110
TBI (Time base interrupt)
PC000000001010
INT1 (External interrupt from P8.0)
PC000000001100
(4) Reset operation:
PC000000000000
(5) Other operations:
For 1-byte instruction execution: PC + 1
For 2-byte instruction execution: PC + 2
ACCUMULATOR
Accumulator is a 4-bit data register for temporary data . For the arithematic, logic and comparative opertion
.., ACC plays a role which holds the source data and result .
FLAGS
7.20.1999
7* This specification are subject to be changed without notice.
EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
Preliminary
There are four kinds of flag, CF ( Carry flag ), ZF ( Zero flag ), SF ( Status flag ) and GF ( General flag ),
these 4 1-bit flags are affected by the arithematic, logic and comparative .... operation .
All flags will be put into stack when an interrupt subroutine is served, and the flags will be restored after
RTI instruction executed .
(1) Carry Flag ( CF )
The carry flag is affected by following operation:
a. Addition : CF as a carry out indicator, when the addition operation has a carry-out, CF will be "1",
in another word, if the operation has no carry-out, CF will be "0".
b. Subtraction : CF as a borrow-in indicator, when the subtraction operation must has a borrow, in the CF
will be "0", in another word, if no borrow-in, CF will be "1".
c. Comparision: CF is as a borrow-in indicator for Comparision operation as the same as subtraction
operation.
d. Rotation: CF shifts into the empty bit of accumulator for the rotation and holds the shift out data after
rotation.
e. CF test instruction : For TFCFC instruction, the content of CF sends into SF then clear itself "0".
For TTSFC instruction, the content of CF sends into SF then set itself "1".
(2) Zero Flag ( ZF )
ZF is affected by the result of ALU, if the ALU operation generate a "0" result, the ZF will be "1",
otherwise, the ZF will be "0".
(3) Status Flag ( SF )
The SF is affected by instruction operation and system status .
a. SF is initiated to "1" for reset condition .
b. Branch instruction is decided by SF, when SF=1, branch condition will be satisified, otherwise,
branch condition will not be satisified by SF = 0 .
(4) General Flag ( GF )
GF is a one bit general purpose register which can be set, clear, test by instruction SGF, CGF and TGS.
PROGRAM EXAMPLE:
Check following arithematic operation for CF, ZF, SF
CF ZF SF
LDIA #00h; - 1 1
LDIA #03h; - 0 1
ADDA #05h; - 0 1
ADDA #0Dh; - 0 0
ADDA #0Eh; - 0 0
* This specification are subject to be changed without notice.
7.20.1999
8
EM73201
4-BIT MICRO-CONTROLLER FOR GENERAL PURPOSE PRODUCT
ALU
Preliminary
The arithematic operation of 4 - bit data is performed in ALU unit . There are 2 flags can be affected by
the result of ALU operation, ZF and SF . The operation of ALU can be affected by GF only .
ALU STRUCTURE
ALU supported user arithematic operation function, including : addition, subtraction and rotaion.
DATA BUS
ALU
ZF CF SF GF
ALU FUNCTION
(1) Addition:
For instruction ADDAM, ADCAM, ADDM #k, ADD #k,y .... ALU supports addition function.
The addition operation can affect CF and ZF. For addition operation, if the result is "0", ZF will be "1",
otherwise, not equal "0", ZF will be "0", When the addition operation has a carry-out. CF will be "1",
otherwise, CF will be "0".
EXAMPLE:
Operation Carry Zero
3+4=7 0 0
7+F=6 1 0
0+0=0 0 1
8+8=0 1 1
(2) Subtraction:
For instruction SUBM #k, SUBA #k, SBCAM, DECM... ALU supports user subtraction function . The
subtraction operation can affect CF and ZF, For subtraction operation, if the result is negative, CF will
be "0", it means a borrow out, otherwise, if the result is positive, CF will be "1". For ZF, if the result
of subtraction operation is "0", the ZF will be "1", otherwise, ZF will be "0".
EXAMPLE:
Operation Carry Zero
8-4=4 1 0
7-F= -8(1000) 0 0
9-9=0 1 1
7.20.1999
9* This specification are subject to be changed without notice.
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