P6FXI-A
MA
AddUlona) Walt State - One additional wait state
is
inserted before the
assertion
of
the first Maxx and CAS#jRAS# assertion during DRAM read
or
write
leadoff cycles. The available options are:
• Disabled (default)
• Enabled
RAS# To CAS# Delay - Allows 1 clock delay
or
none between assertion
of
RASH
and CASH. The available options are:
• Disabled (default)
• Enabled
DRAM
Read
Burst
Timing
<B/E/F> - Controls DRAM Read Burst Timings. If
users set
the
optio~
to
x2/2/3,
the
Burst Read Timings
of
REDO,
EDO
and
.EPM
DRAM respectively are x222, x222, and x333. The available options are:
•
x2J2J3
(default) •
x2J3/4
• x3/4/4 •
x1/2J3
DRAM
' Write
Burst
Timing
<B/E/F> - Controls DRAM Write Burst Timings. The
available options are:
•
x2J2J3(
default)
• x3/3/3
• . x3/3/4
•
x4/414
ISA Bus Clock - ISA clock divide by 4
or
3 depending on PCI bus clock. Users
can refer
to
the formula for clear figure. ( ISA Clock =
PCI
Clock / 3
or
ISA
Clock
=
PCI
Clock /
4).
The available options are:
• PCICLKl4 (default) • PCICLKl3
DRAM
Refresh Queue - If DRAM
is
set
to
((Enabled", the internal 4 deep refresh
queue
is
enable for adjusting
the
DRAM refresh rate. The available options are:
• Enabled (default) • Disabled
DRAM
RAS
Only Refresh - If you choose ((Enabled",
the
DRAM refresh type is
RAS only; otherwise, the DRAM refresh type
is
CAS-before-RAS. The available
options are:
• Disab!ed (default) • Enabled
ECC
Checklng,tGeneration - Enables the option for detecting memory error. The .
available options are:
• Disabled (default) • Enabled
Memory
Parity
Ch~ck
- Enables
or
disables
the
memory parity error check
of
every DRAM module on board . It
is
recommended
to
set this option
to
"Disabled"
(default) when using non-parity bit DRAM modules.
Fast Dram Refresh - The fast refresh mode implements a refresh cycle every 32
host clocks. The available options are:
• Disabled (default) • Enabled
User's Manual 4-8
P6FXI-A
Read-Around-WrHe -When
the
option is disabled,
all
posed writes in the DBX are
retired before a CPU
or
PCI read access
is
reserviced. The available options are:
• Enabled (default) • Disabled
PCI
Burst
Write Combine -
If
this option
is
set as enabled, DBX is allowed
to
combine back-to-back sequential CPU
to
PCI Writes into a single PCI Write
Burst
The available options are: '
• Enabled (default) • Disabled
PCI·T&-DRAM Pipeline - Restricts pipelining
of
PCI
to
DRAM Write cycles when
this option is set as disabled. The available options are:
• Enabled (default) • Disabled
CPlJ-T&-PCI
Write Post - Enables the PCU
to
PCI posting. T
he
availab
le
options
are:
• Enabled (default)
• Disabled
CPU·T&-PCIIDE
Postlng-
When this option
is
set as disabled, the cycles are
treated as normal I/O write transactions. The available options are:
• Enabled (default)
• Disabled
System BIOS Cacheable - Allows shadowing
of
the system BIOS and improves
the system performance. The available options are:
• Disabled (default) • Enabled
Video
RAM
cacheable - Sets the mode
of
the system's video BIOS shadowing
mode. The available options are:
• Disabled (default) • Enabled
Memory Hole
at
15M-16M ' - Enables this option
to
reserve the certain space in
memory for ISA cards. The available options are:
• Disabled (default) • Enabled
8
BIt
I/O
Recovery Time - Defines
the
8-bit I/O recovery time with one
of
the
following system clock options
'.
The available options are:
• 1 (default)
• 2J3/41S/6f7/8/NA
16
Bit
I/O
Recovery Time - Defines the 16-bit I/O recovery time with one
of
the
following system clock options. The available options are:
• 1 (default) • 2J3/4/NA
User's Manual 4-9
/