ECS A960M-MV Schematics REV 1.0A
5
4
3
2
1
A960M-MV
D D
SCHEMATICS TABLE:
Page Index
------- ------------------------
1
COVER PAGE
BLOCK DIADRAM2
AM3 CPU HT & OVERCLOCK
3
4
AM3 CPU MEMORY
AM3 CPU CONTROL & MISC
5
C C
B B
10
11
12
13
14
15
16
6
AM3 CPU PWR & GND
DDR3 DIMM CHANNEL
7
DDR3 DIMM POWER
8
9
CLK GEN
Power 1(CPU Vcore RT8855)
Power 2(DC-DC)
Power 3(DC-DC,Power Sequence)
Front Panel,Fan
NB RS780 HT LINK I/F
NB RS780 PCI-E LINK I/F Clock Distribution
NB RS780 SYSTEM I/F
Page Index
------- ------------------------
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NB RS780 POWER & GND
VGA,HDMI
PCI-E Slot(X16,X1)
SB1(PCIE,PCI,CPU)
SB2(ACPI,USB,GPIO,Audio)
SB3(SATA,IDE,HWM,SPI)
SB4(Power,Decoupling)
SB5(Straps)
IDE, USB, PSKBM, COM
SIO(F71808AU)
Audio1(Chip 1705&662)
Audio2(Panel)
PCIE LAN RTL8111E/8105E
Power Delivery Chart (consumption)
Power Sequence Distribution
REVISION HISTORY:
Rev Date Notes
------ -------------- ---------------------------------------------------------------------------------
1.0
1.0A 2012-10-05 1. Swap HDMI signal
Rev:1.0A
2012-08-23
INITIAL RELEASE
1. Change SIO from F71869E to F71808A
2. Change DVI to HDMI
IMPORTANT NOTES ABOUT
THIS SCHEMATIC
DESIGN NOTE: Example
text for the design note to
show the note inside the
colored box.
DESIGN NOTE: Example
text for the design note to
A A
show the note inside the
colored box.
DESIGN NOTE: Example
text for the design note to
show the note inside the
colored box.
5
1) DESIGN NOTES in
grey are information
notes.
2) DESIGN NOTES in
yellow are notes of
caution.
3) DESIGN NOTES in
red are critical, and
must be understood and
followed.
PCB
PCB
L1:TOPPCB STACK:
L2:PWR
15-ES8-011000
15-ES8-011000
4
3
L3:GND
L4:BOTTOM
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Elitegroup Computer Systems
Elitegroup Computer Systems
Elitegroup Computer Systems
Cover Page
Cover Page
Cover Page
A960M-MV
A960M-MV
A960M-MV
1
1
1
of
32Thursday, October 11, 2012
of
32Thursday, October 11, 2012
of
1
32Thursday, October 11, 2012
1.0A
1.0A
1.0A
5
4
3
2
1
PWM
RT8855(DCR sense)
D D
SVID
Clock Generator
ICS 9LPRS471C
PCIE X 16
HyperTransport
PCIE 16X
LINK
AMD
AM3+
AM3 SOCKET
OUT
NB:RS780L
IN
16x16
DDR3 A CHANNEL
Dual Channel
DDR3 B CHANNEL
Unbuffered DDR3
DIMM1
Unbuffered DDR3
DIMM2
VGA
HT LINK0 CPU I/F
PCIE X 1
LAN
(RTL8105EL)
PCIE 1X
PCIE 1X
Integrated Graphics
1 16X PCIE VIDEO I/F
1 2X PCIE I/F with SB
4 1X PCIE I/F
OPTION
TMDS
HDMI CON
4X ALINK
C C
8 ports
USB 2.0
SB:ATI SB710
USB2.0*10
Serial ATA
SATA*4
SATA*4
AUDIO CODEC
ALC662
HD AUDIO I/F
AC97 2.3 & Azalia
ATA 66/100/133
SPI
BIOS
32M
ACPI 2.0
LPC 1.1
MII
PCI/PCI Bridge
LPC I/F
B B
SIO F71808AU
COM
A A
Elitegroup Computer Systems
Elitegroup Computer Systems
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
Elitegroup Computer Systems
Block Diagram
Block Diagram
Block Diagram
A960M-MV
A960M-MV
A960M-MV
2
2
2
of
32Thursday, October 11, 2012
of
32Thursday, October 11, 2012
of
1
32Thursday, October 11, 2012
1.0A
1.0A
1.0A
A
B
C
D
E
V_DIMM
VCC1.8
4 4
HT_CLKIN_H[0..1]14
HT_CLKIN_L[0..1]14
HT_CLKOUT_H[0..1]14
HT_CLKOUT_L[0..1]14
HT_CADIN_H[0..15]14
HT_CADIN_L[0..15]14
HT_CADOUT_H[0..15]14
HT_CADOUT_L[0..15]14
HT_CTLIN_H[0..1]14
3 3
HT_CTLIN_L[0..1]14
HT_CTLOUT_H[0..1]14
HT_CTLOUT_L[0..1]14
1.5V
V_DIMM
VCC1.8
VCC3VCC3
HT_CLKIN_H[0..1]
HT_CLKIN_L[0..1]
HT_CLKOUT_H[0..1]
HT_CLKOUT_L[0..1]
HT_CADIN_H[0..15]
HT_CADIN_L[0..15]
HT_CADOUT_H[0..15]
HT_CADOUT_L[0..15]
HT_CTLIN_H[0..1]
HT_CTLIN_L[0..1]
HT_CTLOUT_H[0..1]
HT_CTLOUT_L[0..1]
CPU_VDDHT
SR13 51-04-XSR13 51-04-X
12
12
SR14 51-04-XSR14 51-04-X
HT_CLKIN_H1
HT_CLKIN_L1
HT_CLKIN_H0
HT_CLKIN_L0
HT_CTLIN_H1
HT_CTLIN_L1
HT_CTLIN_H0
HT_CTLIN_L0
HT_CADIN_H15
HT_CADIN_L15
HT_CADIN_H14
HT_CADIN_L14
HT_CADIN_H13
HT_CADIN_L13
HT_CADIN_H12
HT_CADIN_L12
HT_CADIN_H11
HT_CADIN_L11
HT_CADIN_H10
HT_CADIN_L10
HT_CADIN_H9
HT_CADIN_L9
HT_CADIN_H8
HT_CADIN_L8
HT_CADIN_H7
HT_CADIN_L7
HT_CADIN_H6
HT_CADIN_L6
HT_CADIN_H5
HT_CADIN_L5
HT_CADIN_H4
HT_CADIN_L4
HT_CADIN_H3
HT_CADIN_L3
HT_CADIN_H2
HT_CADIN_L2
HT_CADIN_H1
HT_CADIN_L1
HT_CADIN_H0
HT_CADIN_L0
HyperTransport
CPUA
CPUA
N6
L0_CLKIN_H1
P6
L0_CLKIN_L1
N3
L0_CLKIN_H0
N2
L0_CLKIN_L0
V4
L0_CTLIN_H1
V5
L0_CTLIN_L1
U1
L0_CTLIN_H0
V1
L0_CTLIN_L0
U6
L0_CADIN_H15
V6
L0_CADIN_L15
T4
L0_CADIN_H14
T5
L0_CADIN_L14
R6
L0_CADIN_H13
T6
L0_CADIN_L13
P4
L0_CADIN_H12
P5
L0_CADIN_L12
M4
L0_CADIN_H11
M5
L0_CADIN_L11
L6
L0_CADIN_H10
M6
L0_CADIN_L10
K4
L0_CADIN_H9
K5
L0_CADIN_L9
J6
L0_CADIN_H8
K6
L0_CADIN_L8
U3
L0_CADIN_H7
U2
L0_CADIN_L7
R1
L0_CADIN_H6
T1
L0_CADIN_L6
R3
L0_CADIN_H5
R2
L0_CADIN_L5
N1
L0_CADIN_H4
P1
L0_CADIN_L4
L1
L0_CADIN_H3
M1
L0_CADIN_L3
L3
L0_CADIN_H2
L2
L0_CADIN_L2
J1
L0_CADIN_H1
K1
L0_CADIN_L1
J3
L0_CADIN_H0
J2
L0_CADIN_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
HT LINK
HT LINK
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
ZIF-941P-S
ZIF-941P-S
AD5
AD4
AD1
AC1
Y6
W6
W2
W3
Y5
Y4
AB6
AA6
AB5
AB4
AD6
AC6
AF6
AE6
AF5
AF4
AH6
AG6
AH5
AH4
Y1
W1
AA2
AA3
AB1
AA1
AC2
AC3
AE2
AE3
AF1
AE1
AG2
AG3
AH1
AG1
HT_CLKOUT_H1
HT_CLKOUT_L1
HT_CLKOUT_H0
HT_CLKOUT_L0
HT_CTLOUT_H1
HT_CTLOUT_L1
HT_CTLOUT_H0
HT_CTLOUT_L0
HT_CADOUT_H15
HT_CADOUT_L15
HT_CADOUT_H14
HT_CADOUT_L14
HT_CADOUT_H13
HT_CADOUT_L13
HT_CADOUT_H12
HT_CADOUT_L12
HT_CADOUT_H11
HT_CADOUT_L11
HT_CADOUT_H10
HT_CADOUT_L10
HT_CADOUT_H9
HT_CADOUT_L9
HT_CADOUT_H8
HT_CADOUT_L8
HT_CADOUT_H7
HT_CADOUT_L7
HT_CADOUT_H6
HT_CADOUT_L6
HT_CADOUT_H5
HT_CADOUT_L5
HT_CADOUT_H4
HT_CADOUT_L4
HT_CADOUT_H3
HT_CADOUT_L3
HT_CADOUT_H2
HT_CADOUT_L2
HT_CADOUT_H1
HT_CADOUT_L1
HT_CADOUT_H0
HT_CADOUT_L0
Please use 1mm pad size,
place all ELT test pads
on bottom side only.
A1
A31
AM3
Top View
AL1
CPU(104)
CPU(104)
30-431-020111
30-431-020111
AL31
2 2
1 1
Elitegroup Computer Systems
Elitegroup Computer Systems
Elitegroup Computer Systems
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
A
B
C
D
Date: Sheet of
CPU HT & DEBUG
CPU HT & DEBUG
CPU HT & DEBUG
A960M-MV
A960M-MV
A960M-MV
E
1.0A
1.0A
3
3
3
1.0A
32Thursday, October 11, 2012
32Thursday, October 11, 2012
32Thursday, October 11, 2012
A
B
C
D
E
DDR3 Memory Interface A DDR3 Memory Interface B
CPUC
AJ19
AK19
AL19
AL18
U31
U30
W29
W28
Y31
Y30
V31
W31
A18
A19
C19
D19
AE30
AC31
AF31
AD29
AE29
AB31
AG31
AD31
B19
AC29
AC30
AB29
N31
AA31
AA28
M31
M29
N28
N29
AE31
N30
P29
AA29
P31
R29
R28
R31
R30
T31
T29
U29
U28
AA30
AK13
AJ13
AK17
AJ17
AK23
AL23
AL28
AL29
D31
C31
C24
C23
D17
C17
C14
C13
AJ14
AH17
AJ23
AK29
C30
A23
B17
B13
CPUC
MB_CLK_H7
MB_CLK_L7
MB_CLK_H6
MB_CLK_L6
MB_CLK_H5
MB_CLK_L5
MB_CLK_H4
MB_CLK_L4
MB_CLK_H3
MB_CLK_L3
MB_CLK_H2
MB_CLK_L2
MB_CLK_H1
MB_CLK_L1
MB_CLK_H0
MB_CLK_L0
MB0_CS_L1
MB0_CS_L0
MB0_ODT1
MB0_ODT0
MB1_CS_L1
MB1_CS_L0
MB1_ODT1
MB1_ODT0
MB_RESET_L
MB_CAS_L
MB_WE_L
MB_RAS_L
MB_BANK2
MB_BANK1
MB_BANK0
MB_CKE1
MB_CKE0
MB_ADD15
MB_ADD14
MB_ADD13
MB_ADD12
MB_ADD11
MB_ADD10
MB_ADD9
MB_ADD8
MB_ADD7
MB_ADD6
MB_ADD5
MB_ADD4
MB_ADD3
MB_ADD2
MB_ADD1
MB_ADD0
MB_DQS_H7
MB_DQS_L7
MB_DQS_H6
MB_DQS_L6
MB_DQS_H5
MB_DQS_L5
MB_DQS_H4
MB_DQS_L4
MB_DQS_H3
MB_DQS_L3
MB_DQS_H2
MB_DQS_L2
MB_DQS_H1
MB_DQS_L1
MB_DQS_H0
MB_DQS_L0
MB_DM7
MB_DM6
MB_DM5
MB_DM4
MB_DM3
MB_DM2
MB_DM1
MB_DM0
MB_DATA63
MB_DATA62
MB_DATA61
MB_DATA60
MB_DATA59
MB_DATA58
MB_DATA57
MB_DATA56
MB_DATA55
MB_DATA54
MB_DATA53
MB_DATA52
MB_DATA51
MB_DATA50
MB_DATA49
MB_DATA48
MB_DATA47
MB_DATA46
MB_DATA45
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
MB_DATA36
MB_DATA35
MB_DATA34
MB_DATA33
MB_DATA32
MB_DATA31
MB_DATA30
MB_DATA29
MB_DATA28
MB_DATA27
MB_DATA26
MB_DATA25
MB_DATA24
MB_DATA23
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
MB_DATA18
MB_DATA17
MB_DATA16
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
MEM CHB
MEM CHB
MB_DATA11
MB_DATA10
MB_DATA9
MB_DATA8
MB_DATA7
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
MB_DATA2
MB_DATA1
MB_DATA0
MB_DQS_H8
MB_DQS_L8
MB_DM8
MB_CHECK7
MB_CHECK6
MB_CHECK5
MB_CHECK4
MB_CHECK3
MB_CHECK2
MB_CHECK1
MB_CHECK0
MB_EVENT_L
ZIF-941P-S
ZIF-941P-S
AH13
MEM_MB_DATA63
AL13
MEM_MB_DATA62
AL15
MEM_MB_DATA61
AJ15
MEM_MB_DATA60
AF13
MEM_MB_DATA59
AG13
MEM_MB_DATA58
AL14
MEM_MB_DATA57
AK15
MEM_MB_DATA56
AL16
MEM_MB_DATA55
AL17
MEM_MB_DATA54
AK21
MEM_MB_DATA53
AL21
MEM_MB_DATA52
AH15
MEM_MB_DATA51
AJ16
MEM_MB_DATA50
AH19
MEM_MB_DATA49
AL20
MEM_MB_DATA48
AJ22
MEM_MB_DATA47
AL22
MEM_MB_DATA46
AL24
MEM_MB_DATA45
AK25
MEM_MB_DATA44
AJ21
MEM_MB_DATA43
AH21
MEM_MB_DATA42
AH23
MEM_MB_DATA41
AJ24
MEM_MB_DATA40
AL27
MEM_MB_DATA39
AK27
MEM_MB_DATA38
AH31
MEM_MB_DATA37
AG30
MEM_MB_DATA36
AL25
MEM_MB_DATA35
AL26
MEM_MB_DATA34
AJ30
MEM_MB_DATA33
AJ31
MEM_MB_DATA32
E31
MEM_MB_DATA31
E30
MEM_MB_DATA30
B27
MEM_MB_DATA29
A27
MEM_MB_DATA28
F29
MEM_MB_DATA27
F31
MEM_MB_DATA26
A29
MEM_MB_DATA25
A28
MEM_MB_DATA24
A25
MEM_MB_DATA23
A24
MEM_MB_DATA22
C22
MEM_MB_DATA21
D21
MEM_MB_DATA20
A26
MEM_MB_DATA19
B25
MEM_MB_DATA18
B23
MEM_MB_DATA17
A22
MEM_MB_DATA16
B21
MEM_MB_DATA15
A20
MEM_MB_DATA14
C16
MEM_MB_DATA13
D15
MEM_MB_DATA12
C21
MEM_MB_DATA11
A21
MEM_MB_DATA10
A17
MEM_MB_DATA9
A16
MEM_MB_DATA8
B15
MEM_MB_DATA7
A14
MEM_MB_DATA6
E13
MEM_MB_DATA5
F13
MEM_MB_DATA4
C15
MEM_MB_DATA3
A15
MEM_MB_DATA2
A13
MEM_MB_DATA1
D13
MEM_MB_DATA0
J31
MEM_MB_DQS_H8
J30
MEM_MB_DQS_L8
J29
K29
MEM_MB_CHECK7
K31
MEM_MB_CHECK6
G30
MEM_MB_CHECK5
G29
MEM_MB_CHECK4
L29
MEM_MB_CHECK3
L28
MEM_MB_CHECK2
H31
MEM_MB_CHECK1
G31
MEM_MB_CHECK0
V29
EVENT pins are for future AM3r2
1 2
R255 300-04R255 300-04
MEM_MB_DM8 7
Layout: Route as 60 ohms
with 5/10 W/S from CPU pins.
MEM_MB_EVENT_L 7
V_DIMMV_DIMM
CPUB
CPUB
STP39STP39
STP44STP44
STP40STP40
STP33STP33
4 4
3 3
2 2
MEM_MA0_CLK0_P7
MEM_MA0_CLK0_N7 MEM_MB0_CLK0_N7
MEM_MA0_CLK1_P7
MEM_MA0_CLK1_N7
STP32STP32
STP43STP43
STP41STP41
STP46STP46
MEM_MA0_CS_L17
MEM_MA0_CS_L07
MEM_MA0_ODT17 MEM_MB0_ODT17
MEM_MA0_ODT07
MEM_MA_RESET-7 MEM_MB_RESET-7
MEM_MA_CAS-7
MEM_MA_WE-7
MEM_MA_RAS-7
MEM_MA_BANK27
MEM_MA_BANK17
MEM_MA_BANK07
MEM_MA_CKE07
MEM_MA_ADD[15..0]7
MEM_MA_DM[7..0]7
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6 MEM_MB_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_L0
MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0
AG21
AG20
AE20
AE19
U27
U26
V27
W27
W26
W25
U24
V24
G19
H19
G20
G21
AC25
AA24
AE28
AC28
AD27
AA25
AE27
AC27
E20
AB25
AB27
AA26
N25
Y27
AA27
M25
M27
N24
AC26
N26
P25
Y25
N27
R24
P27
R25
R26
R27
U25
W24
AD15
AE15
AG18
AG19
AG24
AG25
AG27
AG28
D29
C29
C25
D25
E19
G15
AF15
AF19
AJ25
AH29
B29
E24
E18
H15
L27
T25
T27
F19
F15
MA_CLK_H7
MA_CLK_L7
MA_CLK_H6
MA_CLK_L6
MA_CLK_H5
MA_CLK_L5
MA_CLK_H4
MA_CLK_L4
MA_CLK_H3
MA_CLK_L3
MA_CLK_H2
MA_CLK_L2
MA_CLK_H1
MA_CLK_L1
MA_CLK_H0
MA_CLK_L0
MA0_CS_L1
MA0_CS_L0
MA0_ODT1
MA0_ODT0
MA1_CS_L1
MA1_CS_L0
MA1_ODT1
MA1_ODT0
MA_RESET_L
MA_CAS_L
MA_WE_L
MA_RAS_L
MA_BANK2
MA_BANK1
MA_BANK0
MA_CKE1
MA_CKE0
MA_ADD15
MA_ADD14
MA_ADD13
MA_ADD12
MA_ADD11
MA_ADD10
MA_ADD9
MA_ADD8
MA_ADD7
MA_ADD6
MA_ADD5
MA_ADD4
MA_ADD3
MA_ADD2
MA_ADD1
MA_ADD0
MA_DQS_H7
MA_DQS_L7
MA_DQS_H6
MA_DQS_L6
MA_DQS_H5
MA_DQS_L5
MA_DQS_H4
MA_DQS_L4
MA_DQS_H3
MA_DQS_L3
MA_DQS_H2
MA_DQS_L2
MA_DQS_H1
MA_DQS_L1
MA_DQS_H0
MA_DQS_L0
MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0
MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MEM CHA
MEM CHA
MA_DATA11
MA_DATA10
MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0
MA_DQS_H8
MA_DQS_L8
MA_CHECK7
MA_CHECK6
MA_CHECK5
MA_CHECK4
MA_CHECK3
MA_CHECK2
MA_CHECK1
MA_CHECK0
MA_EVENT_L
MA_DM8
ZIF-941P-S
ZIF-941P-S
AE14
MEM_MA_DATA63
AG14
MEM_MA_DATA62
AG16
MEM_MA_DATA61
AD17
MEM_MA_DATA60
AD13
MEM_MA_DATA59
AE13
MEM_MA_DATA58
AG15
MEM_MA_DATA57
AE16
MEM_MA_DATA56
AG17
MEM_MA_DATA55
AE18
MEM_MA_DATA54
AD21
MEM_MA_DATA53
AG22
MEM_MA_DATA52
AE17
MEM_MA_DATA51
AF17
MEM_MA_DATA50
AF21
MEM_MA_DATA49
AE21
MEM_MA_DATA48
AF23
MEM_MA_DATA47
AE23
MEM_MA_DATA46
AJ26
MEM_MA_DATA45
AG26
MEM_MA_DATA44
AE22
MEM_MA_DATA43
AG23
MEM_MA_DATA42
AH25
MEM_MA_DATA41
AF25
MEM_MA_DATA40
AJ28
MEM_MA_DATA39
AJ29
MEM_MA_DATA38
AF29
MEM_MA_DATA37
AE26
MEM_MA_DATA36
AJ27
MEM_MA_DATA35
AH27
MEM_MA_DATA34
AG29
MEM_MA_DATA33
AF27
MEM_MA_DATA32
E29
MEM_MA_DATA31
E28
MEM_MA_DATA30
D27
MEM_MA_DATA29
C27
MEM_MA_DATA28
G26
MEM_MA_DATA27
F27
MEM_MA_DATA26
C28
MEM_MA_DATA25
E27
MEM_MA_DATA24
F25
MEM_MA_DATA23
E25
MEM_MA_DATA22
E23
MEM_MA_DATA21
D23
MEM_MA_DATA20
E26
MEM_MA_DATA19
C26
MEM_MA_DATA18
G23
MEM_MA_DATA17
F23
MEM_MA_DATA16
E22
MEM_MA_DATA15
E21
MEM_MA_DATA14
F17
MEM_MA_DATA13
G17
MEM_MA_DATA12
G22
MEM_MA_DATA11
F21
MEM_MA_DATA10
G18
MEM_MA_DATA9
E17
MEM_MA_DATA8
G16
MEM_MA_DATA7
E15
MEM_MA_DATA6
G13
MEM_MA_DATA5
H13
MEM_MA_DATA4
H17
MEM_MA_DATA3
E16
MEM_MA_DATA2
E14
MEM_MA_DATA1
G14
MEM_MA_DATA0
J28
MEM_MA_DQS_H8
J27
MEM_MA_DQS_L8
J25
K25
MEM_MA_CHECK7
J26
G28
MEM_MA_CHECK5
G27
MEM_MA_CHECK4
L24
MEM_MA_CHECK3
K27
MEM_MA_CHECK2
H29
MEM_MA_CHECK1MEM_MA_DQS_H0
H27
MEM_MA_CHECK0
W30
EVENT pins are for future AM3r2
1 2
R256 300-04R256 300-04
MEM_MA_DATA[63..0] 7 MEM_MB_DATA[63..0] 7
MEM_MB_ADD[15..0]7
MEM_MA_DM8 7
MEM_MA_CHECK[7..0] 7 MEM_MB_CHECK[7..0] 7
Layout: Route as 60 ohms
with 5/10 W/S from CPU pins.
MEM_MA_EVENT_L 7
MEM_MB_DM[7..0]7
STP36STP36
STP37STP37
STP38STP38
STP31STP31
MEM_MB0_CLK0_P7
MEM_MB0_CLK1_P7
MEM_MB0_CLK1_N7
STP34STP34
STP35STP35
STP42STP42
STP45STP45
MEM_MB0_CS_L17
MEM_MB0_CS_L07
MEM_MB0_ODT07
MEM_MB_CAS-7
MEM_MB_WE-7
MEM_MB_RAS-7
MEM_MB_BANK27
MEM_MB_BANK17
MEM_MB_BANK07
MEM_MB_CKE17MEM_MA_CKE17
MEM_MB_CKE07
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3MEM_MA_CHECK6
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_DM7
MEM_MB_DM6
MEM_MB_DM5
MEM_MB_DM4
MEM_MB_DM3
MEM_MB_DM2
MEM_MB_DM1
MEM_MB_DM0
1 1
MEM_MA_DQS_H[8..0]7
MEM_MA_DQS_L[8..0]7
MEM_MB_DQS_H[8..0]7
MEM_MB_DQS_L[8..0]7
1.5V
V_DIMMV_DIMM
MEM_MA_DQS_H[8..0]
MEM_MA_DQS_L[8..0]
MEM_MB_DQS_H[8..0]
MEM_MB_DQS_L[8..0]
A
CPU Memory
B
Elitegroup Computer Systems
Elitegroup Computer Systems
Elitegroup Computer Systems
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
C
D
Date: Sheet of
AM3 CPU MEMORY
AM3 CPU MEMORY
AM3 CPU MEMORY
A960M-MV
A960M-MV
A960M-MV
E
1.0A
1.0A
4
4
4
1.0A
32Thursday, October 11, 2012
32Thursday, October 11, 2012
32Thursday, October 11, 2012
A
B
C
D
E
VCC25A VCC25A
VCC3 VCC3
V_DIMM V_DIMM
VDDHT
4 4
CPUCLK9
CPUCLK-9
SB_CPUPWRGD10,20
LDT_STOP-16,20
LDT_RST-16,20,5
CPU_PVEN10
CPU_SVD10
CPU_SVC10
1.5V
1.2V
CPU_CLKP
CPU_CLKN
CPU_PWRGD
LDT_STOPLDT_RST-
CPU_PVEN
CPU_SVD
CPU_SVC
CPU_VDDHT
STP22STP22
TP20TP20
TP18TP18
TP11TP11
TP9TP9
TP16TP16
Layout: Place as close as
possible to CPU socket.
a,Rshunt near CPU pin<600mil
b,Cseries as a pair within 25mil
c,Cseries to CPU pin trace length<1250mil
d,12:4:6:4:12(1080 for 93ohm)
VCC25A
support AM3+ TSI.
Vincent 2012/01/31
CPU_THERMDC16,26
CPU_THERMDA26
-CPU_THERMTRIP21
CPU_COREFB+10
CPU_COREFB-10
CPU_VDDNB_FB+10
CPU_VDDNB_FB-10
3 3
LDT_RSTLDT_STOPCPU_PWRGD
CPU_PRESENT_L_15
2 2
1 1
TSI_SIC
TSI_SID
CPU_ALERT_L
CPU_TEST27_SINGLECHAIN
CPU_THERMTRIP_L_15
-PROCHOT
CPU_TEST26_BURNIN_L
CPU_SA0
CPU_PWRGD
LDT_STOP-
LDT_RST-
CPU_THERMDC
CPU_THERMDA
CPU_THERMTRIP_L
CPU_VDD_FB_H
CPU_VDD_FB_L
CPU_VDDNB_FB_H
CPU_VDDNB_FB_L
RN8 300-8P4R-04RN8 300-8P4R-04
1
3
5
7
1 2
R108 10K-04R108 10K-04
1 2
R116 10K-04R116 10K-04
1 2
R111 10K-04R111 10K-04
1 2
R115 10K-04R115 10K-04
RN10 300-8P4R-04RN10 300-8P4R-04
1
3
5
7
C143 180P-50VX7-04C143 180P-50VX7-04
C142 180P-50VX7-04C142 180P-50VX7-04
C139 180P-50VX7-04C139 180P-50VX7-04
21
21
21
IMC_TDI21
IMC_TRST_21
IMC_TDO21
IMC_TMS21
A
TP28TP28
STP28STP28
TP27TP27
STP9STP9
STP8STP8
V_DIMM
12
R134
R134
CPU_M_VREF_SUS V_DIMM
15-1-06
15-1-06
0.25W
12
R133
R133
C147
C147
15-1-06
15-1-06
.1U-16VY-04
.1U-16VY-04
2 1
12mil(width):20mil(spacing)
V_DIMM
2
4
6
8
V_DIMM
2
4
6
8
V_DIMM
1 2
3 4
5 6
7 8
IMC_TDI
IMC_TRST_
IMC_TDO
IMC_TMS
B
E C
E C
RN17
RN17
10K-8P4R-04
10K-8P4R-04
E C
B
QN12
QN12
2N3904-S
2N3904-S
RN16
RN16
4.7K-8P4R-04-O
4.7K-8P4R-04-O
CPU_DBREQ_
CPU_TCK
CPU_DBRDY
CPU_TMS
CPU_TDI
CPU_TRSTCPU_TDO
B
QN11
QN11
2N3904-S
2N3904-S
12
B
QN10
QN10
2N3904-S
2N3904-S
B
R208
R208
10K-04
10K-04
EC
1 2
QN9
QN9
2N3904-S
2N3904-S
3 4
5 6
7 8
1 2
3 4
5 6
7 8
E C
a,20mil(width):20mil(spacing)
b,reference to GND
1 2
FB28 FB120-08FB28 FB120-08
CPU_CLKP
CPU_CLKN CPU_SVD
Layout: Keep trace to resistors
less than 1" from CPU pins.
Layout: Place within 500
mils of the CPU socket.
RN13
RN13
4.7K-8P4R-04
4.7K-8P4R-04
12
R184
R184
10K-04
10K-04
B
C150
C150
4.7U-08
4.7U-08
2 1
C115 3900P-50VX7-04C115 3900P-50VX7-04
21
C114 3900P-50VX7-04C114 3900P-50VX7-04
21
1 2
R140 39.2-1-04R140 39.2-1-04
1 2
R142 39.2-1-04R142 39.2-1-04
1 2
R119 511-1-04R119 511-1-04
1 2
R120 511-1-04R120 511-1-04
Over Clocking
V_DIMM
12
12
R189
R189
R196
R196
10K-04
10K-04
10K-04
10K-04
B
QN5
QN5
2N3904-S
2N3904-S
EC
B
QN7
QN7
2N3904-S
2N3904-S
EC
QN6
QN6
2N3904-S
2N3904-S
2 1
12
TP24TP24
TP23TP23
STP18STP18
STP23STP23
STP25STP25
STP16STP16
STP29STP29
STP17STP17
STP15STP15
STP20STP20
STP19STP19
IMC_DBREQ_
IMC_TCK
IMC_DBRDY
CPU_VDDA_RUN
2.5V@0.25A
C157
C157
3300P-50VX7-04
3300P-50VX7-04
STP62STP62
R102
R102
169-1-04
169-1-04
TSI_SIC21,26
TSI_SID21,26
STP61STP61
TP21TP21
TP13TP13
STP30STP30
IMC_CRST_21 LDT_RST- 16,20,5
C
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
CPU_PWRGD
LDT_STOPLDT_RST-
CPU_PRESENT_L_15
TSI_SIC
TSI_SID
CPU_SA0
CPU_ALERT_L
CPU_TDI
CPU_TRSTCPU_TCK
CPU_TMS
CPU_DBREQ_
CPU_VDD_FB_H
CPU_VDD_FB_L
CPU_VDDIO_PWRGD
CPU_VTT_SUS_SENSE
CPU_M_ZN
CPU_M_ZP
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_H_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
CPU_TEST17_BP3
CPU_TEST16_BP2
CPU_TEST15_BP1
CPU_TEST14_BP0
CPU_TEST12_SCANSHIFTENB
CPU_TEST7_ANALOG_T
CPU_TEST6_DIECRACKMON
CPU_TEST3_GATE0
CPU_TEST2_DRAIN0
IMC_CRST_ LDT_RST-
IMC_DBREQ_ 21
IMC_TCK 21
IMC_DBRDY 21
CPUD
CPUD
C10
VDDA_1
D10
VDDA_2
A8
CLKIN_H
B8
CLKIN_L
C9
PWROK
D8
LDTSTOP_L
C7
RESET_L
AL3
CPU_PRESENT_L
AL6
SIC
AK6
SID
AK4
SA0
AL4
ALERT_L
AL10
TDI
AJ10
TRST_L
AH10
TCK
AL9
TMS
A5
DBREQ_L
G2
VDD_FB_H
G1
VDD_FB_L
F3
M_VDDIO_PWRGD
E12
VDDR_SENSE
F12
M_VREF
AH11
M_ZN
AJ11
M_ZP
A10
TEST25_H
B10
TEST25_L
F10
TEST19
E9
TEST18
AJ7
TEST13
F6
TEST9
D6
TEST17
E7
TEST16
F8
TEST15
C5
TEST14
AH9
TEST12
E5
TEST7
AJ5
TEST6
AH7
TEST3
AJ6
TEST2
C18
RSVD1
C20
RSVD2
F2
RSVD3
G24
RSVD4
G25
RSVD5
H25
RSVD6
L25
RSVD7
L26
RSVD8
VCC1.8
VCC3
12
12
R193
R193
4.7K-04
4.7K-04
B
E C
QN8 2N3904-SQN8 2N3904-S
MISC.
MISC.
INT. MISC.
INT. MISC.
R187
R187
10K-04
10K-04
CORE_TYPE
SVC/VID3
SVD/VID2
PVIEN/VID1
THERMDC
THERMDA
THERMTRIP_L
PROCHOT_L
DBRDY
VDDIO_FB_H
VDDIO_FB_L
VDDNB_FB_H
VDDNB_FB_L
HTREF1
HTREF0
TEST29_H
TEST29_L
TEST24
TEST23
TEST22
TEST21
TEST20
TEST28_H
TEST28_L
TEST27
TEST26
TEST10
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
ZIF-941P-S
ZIF-941P-S
D
VID5
VID4
VID0
TDO
PSI_L
TEST8
RSVD9
G5
D2
D1
C1
E3
E2
E1
AG9
AG8
AK7
AL7
AK10
B6
AK11
AL11
G4
G3
F1
V8
V7
C11
D11
AK8
AH8
AJ9
AL8
AJ8
J10
H9
AK9
AK5
G7
D4
L30
L31
AD25
AE24
AE25
AJ18
AJ20
AK3
CPU_THERMTRIP_L_15 CPU_THERMTRIP_L
Del R98.99.100
CPU_CORE_TYPE_L
CPU_VID5
CPU_VID4
CPU_SVC
CPU_PVEN
CPU_VID0
CPU_THERMDC
CPU_THERMDA
CPU_THERMTRIP_L_15
PROCHOT_L
CPU_TDO
PROCHOT_L
CPU_DBRDY
CPU_VDDIO_FB_H
CPU_VDDIO_FB_L
CPU_VDDNB_FB_H
CPU_VDDNB_FB_L
CPU_PSI-
CPU_HTREF1CPU_M_VREF
CPU_HTREF0
CPU_TEST29_H_FBCLKOUT_H
CPU_TEST29_L_FBCLKOUT_L
CPU_TEST24_SCANCLK1
CPU_TEST23_TSTUPD
CPU_TEST22_SCANSHIFTEN
CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST28_H_PLLCHRZ_H
CPU_TEST28_L_PLLCHRZ_L
CPU_TEST27_SINGLECHAIN
CPU_TEST26_BURNIN_L
CPU_TEST10_ANALOGOUT
CPU_TEST8_DIG_T
R122 1K-04R122 1K-04
R123 1K-04R123 1K-04
R1 300-04R1 300-04
R9 0-04-OR9 0-04-O
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
V_DIMM
12
R114
R114
10K-04
10K-04
B
E C
QN4 2N3904-SQN4 2N3904-S
1 2
R121 1K-04R121 1K-04
1 2
1 2
1 2
V_DIMM
TP12TP12
TP15TP15
TP14TP14
PROCHOT_L 10
12
TP33TP33
TP35TP35
STP11STP11
STP10STP10
TP10TP10
STP14STP14
STP12STP12
Elitegroup Computer Systems
Elitegroup Computer Systems
Elitegroup Computer Systems
AM3 CPU CONTROL&MISC
AM3 CPU CONTROL&MISC
AM3 CPU CONTROL&MISC
For AM3 CPU
-PROCHOT 20
Layout: Keep CPU_HTREF0,1
less than 1.5" from in length.
1 2
R109 44.2-1-04R109 44.2-1-04
1 2
R106 44.2-1-04R106 44.2-1-04
1 2
R139 80.6-1-04R139 80.6-1-04
TP26TP26
TP22TP22
TP31TP31
1 2
R322 300-04R322 300-04
TP25TP25
STP27STP27
STP24STP24
TP30TP30
TP19TP19
STP21STP21
Layout: Route as 80 ohms diff
STP13STP13
impedance (4/5mil).Keep trace
to resistor < 1" from CPU pins.
A960M-MV
A960M-MV
A960M-MV
E
CPU_VDDHT
1.0A
1.0A
5
5
5
1.0A
32Thursday, October 11, 2012
32Thursday, October 11, 2012
32Thursday, October 11, 2012
A
B
C
D
E
CPU_VDD_RUN CPU_VDD_RUN
4 4
VCORE
V_DIMM
VDDHT
VDDHT
3 3
2 2
CPU_VDD_RUN
V_DIMM
CPU_VDDR
CPU_VDDHT
CPUE
CPUE
B3
VDD_1
C2
VDD_2
C4
VDD_3
D3
VDD_4
D5
VDD_5
E4
VDD_6
E6
VDD_7
F5
VDD_8
F7
VDD_9
G6
VDD_10
G8
VDD_11
H7
VDD_12
H11
VDD_13
H23
VDD_14
J8
VDD_15
J12
VDD_16
J14
VDD_17
J16
VDD_18
J18
VDD_19
J20
VDD_20
J22
VDD_21
J24
VDD_22
K7
VDD_23
K9
VDD_24
K11
VDD_25
K13
VDD_26
K15
VDD_27
K17
VDD_28
K19
VDD_29
K21
VDD_30
K23
VDD_31
L4
VDD_32
L5
VDD_33
L8
VDD_34
L10
VDD_35
L12
VDD_36
L14
VDD_37
L16
VDD_38
L18
VDD_39
L20
VDD_40
L22
VDD_41
M2
VDD_42
M3
VDD_43
M7
VDD_44
M9
VDD_45
M11
VDD_46
M13
VDD_47
M15
VDD_48
M17
VDD_49
M19
VDD_50
M21
VDD_51
M23
VDD_52
N8
VDD_53
N10
VDD_54
N12
VDD_55
N14
VDD_56
N16
VDD_57
N18
VDD_58
N20
VDD_59
N22
VDD_60
P7
VDD_61
P9
VDD_62
P11
VDD_63
P13
VDD_64
P15
VDD_65
P17
VDD_66
P19
VDD_67
P21
VDD_68
P23
VDD_69
R4
VDD_70
R5
VDD_71
R8
VDD_72
R10
VDD_73
R12
VDD_74
R14
VDD_75
R16
VDD_76
R18
VDD_77
R20
VDD_78
R22
VDD_79
T2
VDD_80
T3
VDD_81
T7
VDD_82
T9
VDD_83
T11
VDD_84
T13
VDD_85
A3
VSS_1
A7
VSS_2
A9
VSS_3
A11
VSS_4
B4
VSS_5
B9
VSS_6
B11
VSS_7
B14
VSS_8
B16
VSS_9
B18
VSS_10
B20
VSS_11
B22
VSS_12
B24
VSS_13
B26
VSS_14
B28
VSS_15
B30
VSS_16
C3
VSS_17
D14
VSS_18
D16
VSS_19
D18
VSS_20
D20
VSS_21
D22
VSS_22
D24
VSS_23
D26
VSS_24
D28
VSS_25
D30
VSS_26
E11
VSS_27
F4
VSS_28
F14
VSS_29
F16
VSS_30
F18
VSS_31
F20
VSS_32
F22
VSS_33
F24
VSS_34
F26
VSS_35
F28
VSS_36
F30
VSS_37
G9
VSS_38
G11
VSS_39
H8
VSS_40
H10
VSS_41
H12
VSS_42
H14
VSS_43
H16
VSS_44
H18
VSS_45
H24
VSS_46
H26
VSS_47
H28
VSS_48
H30
VSS_49
J4
VSS_50
J5
POWER/GND1
POWER/GND1
VSS_51
J7
VSS_52
J9
VSS_53
J11
VSS_54
J13
VSS_55
J15
VSS_56
J17
VSS_57
J19
VSS_58
J21
VSS_59
J23
VSS_60
K2
VSS_61
K3
VSS_62
K8
VSS_63
K10
VSS_64
K12
VSS_65
K14
VSS_66
K16
VSS_67
K18
VSS_68
K20
VSS_69
K22
VSS_70
K24
VSS_71
K26
VSS_72
K28
VSS_73
K30
VSS_74
L7
VSS_75
L9
VSS_76
L11
VSS_77
L13
VSS_78
L15
VSS_79
L17
VSS_80
L19
VSS_81
L21
VSS_82
L23
VSS_83
M8
VSS_84
M10
VSS_85
ZIF-941P-S
ZIF-941P-S
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AC10
AC12
AC14
AC16
AC18
AC20
AC22
AD11
AD23
AE10
AE12
AF11
CPUF
CPUF
T15
VDD_86
T17
VDD_87
T19
VDD_88
T21
VDD_89
T23
VDD_90
U8
VDD_91
U10
VDD_92
U12
VDD_93
U14
VDD_94
U16
VDD_95
U18
VDD_96
U20
VDD_97
U22
VDD_98
V9
VDD_99
V11
VDD_100
V13
VDD_101
V15
VDD_102
V17
VDD_103
V19
VDD_104
V21
VDD_105
V23
VDD_106
W4
VDD_107
W5
VDD_108
W8
VDD_109
W10
VDD_110
W12
VDD_111
W14
VDD_112
W16
VDD_113
W18
VDD_114
W20
VDD_115
W22
VDD_116
Y2
VDD_117
Y3
VDD_118
Y7
VDD_119
Y9
VDD_120
Y11
VDD_121
Y13
VDD_122
Y15
VDD_123
Y17
VDD_124
Y19
VDD_125
Y21
VDD_126
Y23
VDD_127
AA8
VDD_128
VDD_129
VDD_130
VDD_131
VDD_132
VDD_133
VDD_134
POWER/GND2
POWER/GND2
VDD_135
AB7
VDD_136
AB9
VDD_137
VDD_138
VDD_139
VDD_140
VDD_141
VDD_142
VDD_143
VDD_144
AC4
VDD_145
AC5
VDD_146
AC8
VDD_147
VDD_148
VDD_149
VDD_150
VDD_151
VDD_152
VDD_153
VDD_154
AD2
VDD_155
AD3
VDD_156
AD7
VDD_157
AD9
VDD_158
VDD_159
VDD_160
VDD_161
VDD_162
AF7
VDD_163
AF9
VDD_164
VDD_165
AG4
VDD_166
AG5
VDD_167
AG7
VDD_168
AH2
VDD_169
AH3
VDD_170
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
ZIF-941P-S
ZIF-941P-S
M12
M14
M16
M18
M20
M22
N4
N5
N7
N9
N11
N13
N15
N17
N19
N21
N23
P2
P3
P8
P10
P12
P14
P16
P18
P20
P22
R7
R9
R11
R13
R15
R17
R19
R21
R23
T8
T10
T12
T14
T16
T18
T20
T22
U4
U5
U7
U9
U11
U13
U15
U17
U19
U21
U23
V2
V3
V10
V12
V14
V16
V18
V20
V22
W7
W9
W11
W13
W15
W17
W19
W21
W23
Y8
Y10
Y12
Y14
Y16
Y18
Y20
Y22
AA4
AA5
AA7
AA9
CPU_VDDNB CPU_VDDHT
A4
A6
B5
B7
C6
C8
D7
D9
E8
E10
F9
F11
G10
G12
MT1
MT2
MT3
MT4
MT5
MT6
MT7
MT8
MT9
MT10
MT11
MT12
MT13
MT14
MT15
MT16
MT17
B2
H20
AE7
MT18
MT19
MT20
MT21
MT22
MT23
MT24
MT25
MT26
CPU_VDDNB
2 1
C6
C6
.01U-25VX-04
.01U-25VX-04
SC43
SC43
.01U-25VX-04-X
.01U-25VX-04-X
Bottom Side Decoupling
V_DIMM
SC69
SC71
SC74
SC74
10U-10VY5-08-X-O
SC56
SC56
10U-10VY5-08-X
10U-10VY5-08-X
10U-10VY5-08-X-O
2 1
SC61
SC61
10U-10VY5-08-X
10U-10VY5-08-X
2 1
A
SC72
SC72
10U-6V3X5-08-X
10U-6V3X5-08-X
2 1
SC77
SC77
.22U-10VY5-04-X
.22U-10VY5-04-X
1 1
CPU_VDD_RUN
2 1
2 1
SC59
SC59
10U-10VY5-08-X
10U-10VY5-08-X
2 1
2 1
SC73
SC73
.01U-25VX-04-X
.01U-25VX-04-X
2 1
SC38
SC38
.22U-10VY5-04-X
.22U-10VY5-04-X
SC71
10U-10VY5-08-X-O
10U-10VY5-08-X-O
2 1
2 1
SC54
SC54
.22U-10VY5-04-X
.22U-10VY5-04-X
2 1
SC66
SC66
180P-50VX7-04-X
180P-50VX7-04-X
2 1
SC45
SC45
.01U-25VX-04-X
.01U-25VX-04-X
2 1
SC70
SC70
10U-6V3X5-08-X
10U-6V3X5-08-X
2 1
SC46
SC46
.01U-25VX-04-X
.01U-25VX-04-X
2 1
2 1
SC47
SC47
10U-6V3X5-08-X
10U-6V3X5-08-X
B
SC69
10U-6V3X5-08-X-O
10U-6V3X5-08-X-O
SC67
SC67
.22U-10VY5-04-X
.22U-10VY5-04-X
SC62
SC62
10U-6V3X5-08-X
10U-6V3X5-08-X
2 1
2 1
SC68
SC68
10U-6V3X5-08-X
10U-6V3X5-08-X
2 1
2 1
SC44
SC44
10U-6V3X5-08-X
10U-6V3X5-08-X
CPU_VDDNB
2 1
SC76
SC76
.01U-25VX-04-X
.01U-25VX-04-X
SC50
SC50
10U-10VY5-08-X-O
10U-10VY5-08-X-O
2 1
C131
C131
10U-10VY5-08
10U-10VY5-08
2 1
2 1
SC55
SC55
10U-6V3X5-08-X
10U-6V3X5-08-X
C120
C120
10U-10VY5-08-O
10U-10VY5-08-O
2 1
2 1
SC63
SC63
10U-6V3X5-08-X
10U-6V3X5-08-X
C
C118
C118
10U-6V3X5-08
10U-6V3X5-08
2 1
SC48
SC48
10U-10VY5-08-X-O
10U-10VY5-08-X-O
2 1
SC52
SC52
10U-10VY5-08-X-O
10U-10VY5-08-X-O
2 1
Processor Power and Ground
CPUG
CPUG
VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5
VDDNB_6
VDDNB_7
VDDNB_8
VDDNB_9
VDDNB_10
VDDNB_11
VDDNB_12
VDDNB_13
VDDNB_14
MT1
MT2
MT3
MT4
MT5
MT6
MT7
MT8
MT9
MT10
MT11
MT12
MT13
MT14
MT15
MT16
MT17
NP/RSVD
NP/VSS1
NP/VSS2
MT18
MT19
MT20
MT21
MT22
MT23
MT24
MT25
MT26
2 1
CPU_VDDHT
2 1
SC64
SC64
10U-10VY5-08-X-O
10U-10VY5-08-X-O
2 1
MT27
MT28
MT29
MT30
MT27
MT28
MT29
MT30
2 1
SC57
SC57
.22U-10VY5-04-X
.22U-10VY5-04-X
C132
C132
10U-6V3X5-08
10U-6V3X5-08
2 1
SC40
SC40
10U-6V3X5-08-X
10U-6V3X5-08-X
POWER/GND3
POWER/GND3
MT31
MT32
DHOLE1
DHOLE2
MT31
MT32
DHOLE1
DHOLE2
DHOLE3
2 1
SC51
SC51
.01U-25VX-04-X
.01U-25VX-04-X
C133
C133
.01U-25VX-04
.01U-25VX-04
2 1
AA11
VSS_171
AA13
VSS_172
AA15
VSS_173
AA17
VSS_174
AA19
VSS_175
AA21
VSS_176
AA23
VSS_177
AB2
VSS_178
AB3
VSS_179
AB8
VSS_180
AB10
VSS_181
AB12
VSS_182
AB14
VSS_183
AB16
VSS_184
AB18
VSS_185
AB20
VSS_186
AB22
VSS_187
AC7
VSS_188
AC9
VSS_189
AC11
VSS_190
AC13
VSS_191
AC15
VSS_192
AC17
VSS_193
AC19
VSS_194
AC21
VSS_195
AC23
VSS_196
AD8
VSS_197
AD10
VSS_198
AD12
VSS_199
AD14
VSS_200
AD16
VSS_201
AD20
VSS_202
AD22
VSS_203
AD24
VSS_204
AE4
VSS_205
AE5
VSS_206
AE11
VSS_207
AF2
VSS_208
AF3
VSS_209
AF8
VSS_210
AF10
VSS_211
AF12
VSS_212
AF14
VSS_213
AF16
VSS_214
DHOLE3
DHOLE4
ZIF-941P-S
ZIF-941P-S
DHOLE4
Add MTx and DHOLEx to GND for new net-in method
V_DIMM
VDDR_HT3 CPU_VDD_RUN
C165 .1U-16VY-04C165 .1U-16VY-04
21
SC49
SC49
10U-10VY5-08-X-O
10U-10VY5-08-X-O
2 1
2 1
SC53
SC53
10U-6V3X5-08-X
10U-6V3X5-08-X
D
STP7STP7
C220
C220
10U-10VY5-08
10U-10VY5-08
2 1
AJ1
AJ2
AJ3
AJ4
VDDR_HT3
A12
B12
C12
D12
V_DIMM
M24
M26
M28
M30
P24
P26
P28
P30
T24
T26
T28
T30
V25
V26
V28
V30
Y24
Y26
Y28
Y29
AB24
AB26
AB28
AB30
AC24
AD26
AD28
AD30
AF30
2 1
C214
C214
180P-50VX7-04-O
180P-50VX7-04-O
Layout: Place across each
VDDIO-GND plane split.
FOR EMC
SC65
SC65
10U-6V3X5-08-X
10U-6V3X5-08-X
2 1
CPUH
CPUH
VLDT_A_1
VLDT_A_2
VLDT: 1.2V@1.4A
VLDT_A_3
VLDT_A_4
VDDR_1
VDDR_2
VDDR: 1.2V@1.75A
VDDR_3
VDDR_4
VDDIO_1
VDDIO_2
VDDIO_3
VDDIO_4
VDDIO_5
VDDIO_6
VDDIO_7
VDDIO_8
VDDIO_9
VDDIO_10
VDDIO_11
VDDIO_12
VDDIO_13
VDDIO_14
VDDIO_15
VDDIO_16
VDDIO_17
VDDIO_18
VDDIO_19
VDDIO: 1.5V@3.6A
VDDIO_20
VDDIO_21
VDDIO_22
VDDIO_23
VDDIO_24
VDDIO_25
VDDIO_26
VDDIO_27
VDDIO_28
VDDIO_29
CPU_VDDR
C179
C179
10U-6V3X5-08
10U-6V3X5-08
2 1
V_DIMM
C215
C215
180P-50VX7-04-O
180P-50VX7-04-O
2 1
SC41 .22U-10VY5-04-X-OSC41 .22U-10VY5-04-X-O
C221
C221
10U-10VY5-08
10U-10VY5-08
2 1
21
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
H1
VLDT_B_1
VLDT_B_2
VLDT_B_3
VLDT_B_4
VDDR_5
VDDR_6
VDDR_7
VDDR_8
VDDR_9
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
POWER/GND4
POWER/GND4
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
ZIF-941P-S
ZIF-941P-S
C173
C173
180P-50VX7-04
180P-50VX7-04
2 1
VDDR_HT3
CPU_VDDNB
Elitegroup Computer Systems
Elitegroup Computer Systems
Elitegroup Computer Systems
VLDT_HT3_RUN_B
H2
H5
H6
CPU_VDDR
AG12
AH12
AJ12
AK12
Layout: Place as close as
AL12
possible to CPU socket.
AF18
AF20
AF22
AF24
AF26
AF28
AG10
AG11
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH30
AK2
AK14
AK16
AK18
AK20
AK22
AK24
AK26
AK28
AK30
AL5
C168
C168
C166
C166
10U-10VY5-08
10U-10VY5-08
1U-10VY5-06
1U-10VY5-06
2 1
2 1
C22
C22
.1U-16VY-04-O
.1U-16VY-04-O
2 1
AM3 CPU PWR&GND
AM3 CPU PWR&GND
AM3 CPU PWR&GND
A960M-MV
A960M-MV
A960M-MV
E
C122
C122
10U-6V3X5-08
10U-6V3X5-08
2 1
6
6
6
1.0A
1.0A
1.0A
32Thursday, October 11, 2012
32Thursday, October 11, 2012
32Thursday, October 11, 2012
5
4
3
2
1
VCC3 VCC3
SMBCK19,21,9
SMBDT19,21,9
D D
MEM_MA_DATA[63..0]4
MEM_MA_CHECK[7..0]4
MEM_MA_ADD[15..0]4
MEM_MA_BANK04
MEM_MA_BANK14
MEM_MA_BANK24
MEM_MA_DM[7..0]4
MEM_MA_DM84
MEM_MA_DQS_H[8..0]4
MEM_MA_DQS_L[8..0]4
MEM_MA_RAS-4
MEM_MA_CAS-4
MEM_MA_WE-4
MEM_MA_CKE04
MEM_MA_CKE14
C C
B B
A A
MEM_MA_EVENT_L4
MEM_MA_RESET-4
MEM_MB_DATA[63..0]4
MEM_MB_CHECK[7..0]4
MEM_MB_ADD[15..0]4
MEM_MB_BANK04
MEM_MB_BANK14
MEM_MB_BANK24
MEM_MB_DM[7..0]4
MEM_MB_DM84
MEM_MB_DQS_H[8..0]4
MEM_MB_DQS_L[8..0]4
MEM_MB_RAS-4
MEM_MB_CAS-4
MEM_MB_WE-4
MEM_MB_CKE04
MEM_MB_CKE14
MEM_MB_EVENT_L4
MEM_MB_RESET-4
MEM_MA0_CS_L04
MEM_MA0_CS_L14
MEM_MA0_ODT04
MEM_MA0_ODT14
MEM_MA0_CLK0_P4
MEM_MA0_CLK0_N4
MEM_MA0_CLK1_P4
MEM_MA0_CLK1_N4
MEM_MB0_CS_L04
MEM_MB0_CS_L14
MEM_MB0_ODT04
MEM_MB0_ODT14
MEM_MB0_CLK0_P4
MEM_MB0_CLK0_N4
MEM_MB0_CLK1_P4
MEM_MB0_CLK1_N4
5
SCLK0
SDATA0
MEM_MA_DATA[63..0]
MEM_MA_CHECK[7..0]
MEM_MA_ADD[15..0]
MEM_MA_BANK0
MEM_MA_BANK1
MEM_MA_BANK2
MEM_MA_DM[7..0]
MEM_MA_DM8
MEM_MA_DQS_H[8..0]
MEM_MA_DQS_L[8..0]
MEM_MA_RASMEM_MA_CASMEM_MA_WE-
MEM_MA_CKE0
MEM_MA_CKE1
MEM_MA_EVENT_L
MEM_MA_RESET-
MEM_MB_DATA[63..0]
MEM_MB_CHECK[7..0]
MEM_MB_ADD[15..0]
MEM_MB_BANK0
MEM_MB_BANK1
MEM_MB_BANK2
MEM_MB_DM[7..0]
MEM_MB_DM8
MEM_MB_DQS_H[8..0]
MEM_MB_DQS_L[8..0]
MEM_MB_RASMEM_MB_CASMEM_MB_WE-
MEM_MB_CKE0
MEM_MB_CKE1
MEM_MB_EVENT_L
MEM_MB_RESET-
MEM_MA0_CS_L0
MEM_MA0_CS_L1
MEM_MA0_ODT0
MEM_MA0_ODT1
MEM_MA0_CLK0_P
MEM_MA0_CLK0_N
MEM_MA0_CLK1_P
MEM_MA0_CLK1_N
MEM_MB0_CS_L0
MEM_MB0_CS_L1
MEM_MB0_ODT0
MEM_MB0_ODT1
MEM_MB0_CLK0_P
MEM_MB0_CLK0_N
MEM_MB0_CLK1_P
MEM_MB0_CLK1_N
MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15
MEM_MA_BANK0
MEM_MA_BANK1
MEM_MA_BANK2
MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7
MEM_MA_DM8
MEM_MA_DQS_L0
MEM_MA_DQS_H0
MEM_MA_DQS_L1
MEM_MA_DQS_H1
MEM_MA_DQS_L2
MEM_MA_DQS_H2
MEM_MA_DQS_L3
MEM_MA_DQS_H3
MEM_MA_DQS_L4
MEM_MA_DQS_H4
MEM_MA_DQS_L5
MEM_MA_DQS_H5
MEM_MA_DQS_L6
MEM_MA_DQS_H6
MEM_MA_DQS_L7
MEM_MA_DQS_H7
MEM_MA_DQS_L8
MEM_MA_DQS_H8
MEM_MA_RASMEM_MA_CASMEM_MA_WE-
MEM_MA0_CS_L0
MEM_MA0_CS_L1
MEM_MA_CKE0
MEM_MA_CKE1
MEM_MA0_ODT0
MEM_MA0_ODT1
MEM_MA0_CLK0_P
MEM_MA0_CLK0_N
MEM_MA0_CLK1_P
MEM_MA0_CLK1_N
SCLK0
SDATA0
VCC3
MEM_MA_EVENT_L
MEM_MA_RESET-
4
DDR3_1A DDR3-240P-GYDDR3_1A DDR3-240P-GY
188
A0
181
A1
61
A2
180
A3
59
A4
58
A5
178
A6
56
A7
177
A8
175
A9
70
A10
55
A11
174
A12
196
A13
172
A14
171
A15
71
BA0
190
BA1
52
BA2
125
DM0/DQS9
134
DM1/DQS10
143
DM2/DQS11
152
DM3/DQS12
203
DM4/DQS13
212
DM5/DQS14
221
DM6/DQS15
230
DM7/DQS16
161
DM8/DQS17
6
DQS0
7
DQS0
15
DQS1
16
DQS1
24
DQS2
25
DQS2
33
DQS3
34
DQS3
84
DQS4
85
DQS4
93
DQS5
94
DQS5
102
DQS6
103
DQS6
111
DQS7
112
DQS7
42
DQS8
43
DQS8
192
RAS
74
CAS
73
WE
193
S0
76
S1
50
CKE0
169
CKE1
195
ODT
77
RSVD/ODT1
184
CK0
185
CK0
63
CK1
64
CK1
117
SA0
237
SA1
118
SCL
238
SDA
236
VDDSPD
167
TEST
48
FREE1
49
FREE2
187
FREE3
198
FREE4
168
RESET
53
ERR_OUT
68
PAR_IN
79
RSVD/SPD
SMBus Addressing
Device
DIMMA0
DIMMB0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQS9
DQS10
DQS11
DQS12
DQS13
DQS14
DQS15
DQS16
DQS17
SMBus 0
8-bit Address (hex)
A0
A1
3
4
9
10
122
123
128
129
12
13
18
19
131
132
137
138
21
22
27
28
140
141
146
147
30
31
36
37
149
150
155
156
81
82
87
88
200
201
206
207
90
91
96
97
209
210
215
216
99
100
105
106
218
219
224
225
108
109
114
115
227
228
233
234
39
40
45
46
158
159
164
165
126
135
144
153
204
213
222
231
162
3
MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA32
MEM_MA_DATA33
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
MEM_MA_DATA63
MEM_MA_CHECK0
MEM_MA_CHECK1
MEM_MA_CHECK2
MEM_MA_CHECK3
MEM_MA_CHECK4
MEM_MA_CHECK5
MEM_MA_CHECK6
MEM_MA_CHECK7
MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_ADD15
MEM_MB_BANK0
MEM_MB_BANK1
MEM_MB_BANK2
MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7
MEM_MB_DM8
MEM_MB_DQS_L0
MEM_MB_DQS_H0
MEM_MB_DQS_L1
MEM_MB_DQS_H1
MEM_MB_DQS_L2
MEM_MB_DQS_H2
MEM_MB_DQS_L3
MEM_MB_DQS_H3
MEM_MB_DQS_L4
MEM_MB_DQS_H4
MEM_MB_DQS_L5
MEM_MB_DQS_H5
MEM_MB_DQS_L6
MEM_MB_DQS_H6
MEM_MB_DQS_L7
MEM_MB_DQS_H7
MEM_MB_DQS_L8
MEM_MB_DQS_H8
MEM_MB_RASMEM_MB_CASMEM_MB_WE-
MEM_MB0_CS_L0
MEM_MB0_CS_L1
MEM_MB_CKE0
MEM_MB_CKE1
MEM_MB0_ODT0
MEM_MB0_ODT1
MEM_MB0_CLK0_P
MEM_MB0_CLK0_N
MEM_MB0_CLK1_P
MEM_MB0_CLK1_N
VCC3
SCLK0
SDATA0
VCC3
MEM_MB_EVENT_L
MEM_MB_RESET-
DDR3_2A DDR3-240P-GYDDR3_2A DDR3-240P-GY
188
A0
181
A1
61
A2
180
A3
59
A4
58
A5
178
A6
56
A7
177
A8
175
A9
70
A10
55
A11
174
A12
196
A13
172
A14
171
A15
71
BA0
190
BA1
52
BA2
125
DM0/DQS9
134
DM1/DQS10
143
DM2/DQS11
152
DM3/DQS12
203
DM4/DQS13
212
DM5/DQS14
221
DM6/DQS15
230
DM7/DQS16
161
DM8/DQS17
6
DQS0
7
DQS0
15
DQS1
16
DQS1
24
DQS2
25
DQS2
33
DQS3
34
DQS3
84
DQS4
85
DQS4
93
DQS5
94
DQS5
102
DQS6
103
DQS6
111
DQS7
112
DQS7
42
DQS8
43
DQS8
192
RAS
74
CAS
73
WE
193
S0
76
S1
50
CKE0
169
CKE1
195
ODT
77
RSVD/ODT1
184
CK0
185
CK0
63
CK1
64
CK1
117
SA0
237
SA1
118
SCL
238
SDA
236
VDDSPD
167
TEST
48
FREE1
49
FREE2
187
FREE3
198
FREE4
168
RESET
53
ERR_OUT
68
PAR_IN
79
RSVD/SPD
2
3
MEM_MB_DATA0
DQ0
4
MEM_MB_DATA1
DQ1
9
MEM_MB_DATA2
DQ2
10
MEM_MB_DATA3
DQ3
122
MEM_MB_DATA4
DQ4
123
MEM_MB_DATA5
DQ5
128
MEM_MB_DATA6
DQ6
129
MEM_MB_DATA7
DQ7
12
MEM_MB_DATA8
DQ8
13
MEM_MB_DATA9
DQ9
18
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
MEM_MB_DATA10
19
MEM_MB_DATA11
131
MEM_MB_DATA12
132
MEM_MB_DATA13
137
MEM_MB_DATA14
138
MEM_MB_DATA15
21
MEM_MB_DATA16
22
MEM_MB_DATA17
27
MEM_MB_DATA18
28
MEM_MB_DATA19
140
MEM_MB_DATA20
141
MEM_MB_DATA21
146
MEM_MB_DATA22
147
MEM_MB_DATA23
30
MEM_MB_DATA24
31
MEM_MB_DATA25
36
MEM_MB_DATA26
37
MEM_MB_DATA27
149
MEM_MB_DATA28
150
MEM_MB_DATA29
155
MEM_MB_DATA30
156
MEM_MB_DATA31
81
MEM_MB_DATA32
82
MEM_MB_DATA33
87
MEM_MB_DATA34
88
MEM_MB_DATA35
200
MEM_MB_DATA36
201
MEM_MB_DATA37
206
MEM_MB_DATA38
207
MEM_MB_DATA39
90
MEM_MB_DATA40
91
MEM_MB_DATA41
96
MEM_MB_DATA42
97
MEM_MB_DATA43
209
MEM_MB_DATA44
210
MEM_MB_DATA45
215
MEM_MB_DATA46
216
MEM_MB_DATA47
99
MEM_MB_DATA48
100
MEM_MB_DATA49
105
MEM_MB_DATA50
106
MEM_MB_DATA51
218
MEM_MB_DATA52
219
MEM_MB_DATA53
224
MEM_MB_DATA54
225
MEM_MB_DATA55
108
MEM_MB_DATA56
109
MEM_MB_DATA57
114
MEM_MB_DATA58
115
MEM_MB_DATA59
227
MEM_MB_DATA60
228
MEM_MB_DATA61
233
MEM_MB_DATA62
234
MEM_MB_DATA63
39
MEM_MB_CHECK0
40
MEM_MB_CHECK1
45
MEM_MB_CHECK2
46
MEM_MB_CHECK3
158
MEM_MB_CHECK4
159
MEM_MB_CHECK5
164
MEM_MB_CHECK6
165
MEM_MB_CHECK7
126
135
144
153
204
213
222
231
162
1
7
7
7
of
32Thursday, October 11, 2012
32Thursday, October 11, 2012
32Thursday, October 11, 2012
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS9
DQS10
DQS11
DQS12
DQS13
DQS14
DQS15
DQS16
DQS17
Elitegroup Computer Systems
Elitegroup Computer Systems
Elitegroup Computer Systems
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet
DDR3 DIMM CHANNEL
DDR3 DIMM CHANNEL
DDR3 DIMM CHANNEL
A960M-MV
A960M-MV
A960M-MV
1.0A
1.0A
1.0A
A
B
C
D
E
V_DIMM DDR3_VTT
4 4
3 3
2 2
V_DIMMV_DIMM
DDR3_VTTDDR_VTT
DDR3_1B DDR3-240P-GYDDR3_1B DDR3-240P-GY
2
VSS1
5
VSS2
8
VSS3
11
VSS4
14
VSS5
17
VSS6
20
VSS7
23
VSS8
26
VSS9
29
VSS10
32
VSS11
35
VSS12
38
VSS13
41
VSS14
44
VSS15
47
VSS16
80
VSS17
83
VSS18
86
VSS19
89
VSS20
92
VSS21
95
VSS22
98
VSS23
101
VSS24
104
VSS25
107
VSS26
110
VSS27
113
VSS28
116
VSS29
119
VSS30
121
VSS31
124
VSS32
127
VSS33
130
VSS34
133
VSS35
136
VSS36
139
VSS37
142
VSS38
145
VSS39
148
VSS40
151
VSS41
154
VSS42
157
VSS43
160
VSS44
163
VSS45
199
VSS46
166
VSS47
202
VSS48
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VTT1
VTT2
VREFDQ
VREFCA
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
V_DIMM
51
54
57
60
62
65
66
69
72
75
78
170
173
176
179
182
183
186
189
191
194
197
120
240
1
67
205
208
211
214
217
220
223
226
229
232
235
239
DDR3_VTT
MEM_VREFDQ_SUS
MEM_VREFCA_SUS
C238
C238
.1U-16VY-04
.1U-16VY-04
2 1
DE-COUPLING CAP FOR DIMMs
C243
C242
C242
.01U-25VX-04
.01U-25VX-04
C243
.1U-16VY-04
.1U-16VY-04
2 1
C244
C244
.1U-16VY-04
.1U-16VY-04
2 1
C239
C239
.1U-16VY-04
.1U-16VY-04
2 1
2 1
C245
C245
10U-10VY5-08
10U-10VY5-08
2 1
C246
C246
10U-10VY5-08-O
10U-10VY5-08-O
2 1
2 1
DDR3_2B DDR3-240P-GYDDR3_2B DDR3-240P-GY
2
VSS1
5
VSS2
8
VSS3
11
VSS4
14
VSS5
17
VSS6
20
VSS7
23
VSS8
26
VSS9
29
VSS10
32
VSS11
35
VSS12
38
VSS13
41
VSS14
44
VSS15
47
VSS16
80
VSS17
83
VSS18
86
VSS19
89
VSS20
92
VSS21
95
VSS22
98
VSS23
101
VSS24
104
VSS25
107
VSS26
110
VSS27
113
VSS28
116
VSS29
119
VSS30
121
VSS31
124
VSS32
127
VSS33
130
VSS34
133
VSS35
136
VSS36
139
VSS37
142
VSS38
145
VSS39
148
VSS40
151
VSS41
154
VSS42
157
VSS43
160
VSS44
163
VSS45
199
VSS46
166
VSS47
202
VSS48
C209
C209
.01U-25VX-04
.01U-25VX-04
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VTT1
VTT2
VREFDQ
VREFCA
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
V_DIMM
51
54
57
60
62
65
66
69
72
75
78
170
173
176
179
182
183
186
189
191
194
197
120
240
1
67
205
208
211
214
217
220
223
226
229
232
235
239
C241
C241
.1U-16VY-04
.1U-16VY-04
2 1
DDR3_VTT
MEM_VREFDQ_SUS
MEM_VREFCA_SUS
C240
C240
.1U-16VY-04
.1U-16VY-04
2 1
MEM_VREFDQ_SUS
V_DIMM MEM_VREFDQ_SUS
12
R229
R229
15-1-06
15-1-06
1 1
A
12
R230
R230
15-1-06
15-1-06
C217
C217
.1U-16VY-04
.1U-16VY-04
2 1
TP43TP43
Layout: Place within 500
mils of the DIMMB1 socket.
12mil(width):20mil(spacing)
B
C
MEM_VREFCA_SUS
V_DIMM MEM_VREFCA_SUS
12
R258
R258
15-1-06
15-1-06
12
R257
R257
15-1-06
15-1-06
C234
C234
.1U-16VY-04
.1U-16VY-04
2 1
TP44TP44
Layout: Place within 500
mils of the DIMMB1 socket.
12mil(width):20mil(spacing)
D
Elitegroup Computer Systems
Elitegroup Computer Systems
Elitegroup Computer Systems
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
DDR3 DIMM PWR
DDR3 DIMM PWR
DDR3 DIMM PWR
A960M-MV
A960M-MV
A960M-MV
E
8
8
8
32Thursday, October 11, 2012
32Thursday, October 11, 2012
32Thursday, October 11, 2012
1.0A
1.0A
1.0A
5
4
3
2
1
VCC3 CLK_VDD
1 2
FB40 FB120-06FB40 FB120-06
D D
C101
10U-6V3X5-08
10U-6V3X5-08
C129
C129
C113
C113C101
.1U-16VY-04
.1U-16VY-04
.1U-16VY-04
.1U-16VY-04
1- PLACE ALL SERIAL TERMINATION
RESISTORS CLOSE TO CLOCK GEN
C112
C112
.1U-16VY-04
.1U-16VY-04
C102
C102
.1U-16VY-04
.1U-16VY-04
C106
C106
.1U-16VY-04
.1U-16VY-04
VCC3
C202
C202
.1U-16VY-04
.1U-16VY-04
For EMI
2- PUT DECOUPLING CAPS CLOSE TO CLOCK GEN POWER PIN
C110
C110
1U-10VY5-06
1U-10VY5-06
X2
X2
X-14.318M
X-14.318M
1 2
R92 1K-04R92 1K-04
Rc
R90 8.2K-04R90 8.2K-04
R89 8.2K-04R89 8.2K-04
Rd
R85 33-04R85 33-04
R91 150-1-04R91 150-1-04
R86
R86
75-1-04
75-1-04
Rb
1 2
RS780RS740
150-1-0433-1-04
VX
V
X
V
X
CLK_VDDA
CLK_VDD48
CLK_VDD
1 2
1 2
1 2
Ra
12
12
MC19
MC19
1U-10VY5-06
1U-10VY5-06
CLK_VDDREF
CLKA
CLKA
44
VDDA
43
GNDA
60
VDDREF
61
GNDREF
39
VDDSATA
42
GNDSATA
64
VDD48
3
GND48
48
VDDCPU
47
GNDCPU
56
VDDHTT
53
GNDHTT
34
VDDATIG
11
VDDSRC1
16
VDDSRC2
25
VDDSB_SRC
28
GNDATIG1
33
GNDATIG2
10
GNDSRC1
17
GNDSRC2
24
GNDSB_SRC
62
X1
63
X2
52
RESTORE#
4
SMBCLK
5
SMBDAT
51
PD#
59
REF0/SEL_HTT66
58
REF1/SEL_SATA
57
REF2
ICS9LPRS471CS
ICS9LPRS471CS
65
CLKB
CLKB
eGND65
CPUKG0T_LPRS
CPUKG0C_LPRS
CPUKG1T_LPRS
CPUKG1C_LPRS
ATIG0T_LPRS
ATIG0C_LPRS
ATIG1T_LPRS
ATIG1C_LPRS
ATIG2T_LPRS
ATIG2C_LPRS
ATIG3T_LPRS
ATIG3C_LPRS
SB_SRC0T_LPRS
SB_SRC0C_LPRS
SB_SRC1T_LPRS
SB_SRC1C_LPRS
SRC0T_LPRS
SRC0C_LPRS
SRC1T_LPRS
SRC1C_LPRS
SRC2T_LPRS
SRC2C_LPRS
SRC3T_LPRS
SRC3C_LPRS
SRC4T_LPRS
SRC4C_LPRS
SRC5T_LPRS
SRC5C_LPRS
SRC6T/SATAT_LPRS
SRC6C/SATAC_LPRS
HTT0T/66M_LPRS
HTT0C/66M_LPRS
48MHz_0
48MHz_1
THERMAL GND
THERMAL GND
50
49
46
45
38
37
36
35
32
31
30
29
27
26
23
22
21
20
19
18
15
14
13
12
9
8
7
6
41
40
55
54
2
1
R_CPUCLK
R_CPUCLK-
R_NBSRC_CLKP
R_NBSRC_CLKN
R_GFX_CLKP
R_GFX_CLKN
R_GPP_CLK0P
R_GPP_CLK0N
R_LAN_CLKP
R_LAN_CLKN
R_SBLINK_CLKP
R_SBLINK_CLKN
R_SBSRC_CLKP
R_SBSRC_CLKN
R_NBHT_REFCLK
R_NBHT_REFCLKN
SIO_CLOCK_R
48M_USB_R
OSC_14M_NB
CLK_48M_USB
CLK_48M_SIO
CPUCLK 5
CPUCLK- 5
NBSRC_CLKP 16
NBSRC_CLKN 16
GFX_CLKP 19
GFX_CLKN 19
GPP_CLK0P 19
GPP_CLK0N 19
LAN_CLKP 29
LAN_CLKN 29
SBLINK_CLKP 16
SBLINK_CLKN 16
SBSRC_CLKP 20
SBSRC_CLKN 20
Re
NBHT_REFCLK_P 16
1 2
R97 33-04R97 33-04
1 2
R96 33-04R96 33-04
CC3 22P-04-OCC3 22P-04-O
CC4 22P-04-OCC4 22P-04-O
CC5 22P-04-OCC5 22P-04-O
NBHT_REFCLK_N 16
CPU CLK
NB PCI-E GFX CLK
GFX SLOT
PCI-E 1X SLOT
LAN CHIP
A-Link (NB)
A-Link (SB)
10/01/06
HT REF CLK
CLK_48M_SIO 26SMBDT19,21,7
CLK_48M_USB 21
LAYOUT崘Diff.
NB CLOCK INPUT TABLE
* RS880 can be used as clock buffer to output two PCIE referecence clocks
By deault, chip will configured as input mode, BIOS can program it to output mode.
Clock chip has internal serial terminations for differencial pairs
NB CLOCKS
HT_REFCLKP
HT_REFCLKN
REFCLK_P
REFCLK_N
GFX_REFCLK*
GPP_REFCLK 100M DIFF(OUT)
GPPSB_REFCLK 100M DIFF
RS740 RS780
66M SE(SE)
NC
14M SE (3.3V) 14M SE (1.1V)
NC vref
100M DIFF
NC
100M DIFF
100M DIFF
100M DIFF
100M DIFF
100M DIFF
100M DIFF
FB25 FB120-06FB25 FB120-06
VCC3
C C
C99 56P-04C99 56P-04
3
C98 56P-04C98 56P-04
-HW_RST13,21,26
SEL_HTT66
B B
SEL_SATA
* default
RS740
RX780
RS780
(Single-ended)
100 MHz differential HTT clock
*
0
1
100 MHz non-spreading differential SRC clock
*
100 MHz spreading differential SRC clock
0
OSC_14M_NB
3.3V 33R serial
1.8V 82.5R/130R
1.1V 158R/90.9R
OSC_14M_SB20
OSC_14M_NB16
66 MHz 3.3V single ended HTT clock
1
SMBCK19,21,7
CLK_VDD
RS880 OSC_14M_NB 1.1V Ra/Rb=150R/75R
RS740/RS760/RS780 difference BOM table (HT LINK)
Ra
Rb
Rc
A A
Rd
Re VX
ICS9LPRS471CS
ICS9LPRS471CS
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Elitegroup Computer Systems
Elitegroup Computer Systems
Elitegroup Computer Systems
Clock Generator
Clock Generator
Clock Generator
A960M-MV
A960M-MV
A960M-MV
9 32Thursday, October 11, 2012
9 32Thursday, October 11, 2012
9 32Thursday, October 11, 2012
1
1.0A
1.0A
1.0A
5
Rb
0-04
NC
MC55
MC55
1U-10VY5-06
1U-10VY5-06
CPU_COREFB-5
VCC3
Vincent 0923
CPU_VDDNB_FB-5
CPU_VDDNB_FB+5
CPU_VDDNB
R380
R380
10K-04
10K-04
12
R379
R379
2.7K-04
2.7K-04
5
Offset
Rc
75K-04
75K-04
VCC3
12
Rc
R374 75K-04R374 75K-04
ADJ1
Rd
TP5TP5
TP6TP6
CPU_SVC5
CPU_SVD5
CPU_PVEN5
TP7TP7
R344 4.7K-04R344 4.7K-04
Del PG_VCORE
EN_8855
MC56
MC56
1U-10VY5-06
1U-10VY5-06
V1.0 Install
111107
36K-1-04
?-1-04
R381
R381
10K-04
10K-04
VRM_PWROK
CPU_COREFB-
C362 1U-10VY5-06C362 1U-10VY5-06
R373 15K-1-04-OR373 15K-1-04-O
R375 51K-04R375 51K-04
R369 36K-1-04R369 36K-1-04
1
1
1
EN_8855
VRM_PWROK
ɴ9 ɴ,5
R368 100-04R368 100-04
Rd Re
1K-04
30K-1-04NC6.2K-04
PWM1
PWM1
RT8855GQW
RT8855GQW
24
A5VCC
10
14
46
H_VID5
45
H_VID4
44
43
42
41
H_VID0
47
48
R365 1K-04R365 1K-04
C376 .01U-25VX-04-OC376 .01U-25VX-04-O
+12V_4P
Rf
C356.1U-16VY-04C356.1U-16VY-04
R319 220-1-04R319 220-1-04
T_ADJ ADJ
R345 100-04R 345 100-04
R362 330-1-04R362 330-1-04
9
3
49
ADJ
GND
FBRTN
5VCC
OFS
2
RT
IMAX
VID[5]
VID[4]
VID[3]/SVC
VID[2]/SVD
VID[1]/PVI
VID[0]/VFIXEN
VDDPWRGD
ENABLE
PWROK
FBRTN_NB
1
4
R351 100-04R351 100-04
C371
C371
33P-04
33P-04
1 2
L9 PIND-0.6UD-8X8L9 PIND-0.6UD-8X8
Idc= 22A
DCR=1.9m ohm
08-413-604322
BOM Difference
Ra
SB_CPUPWRGD20,5
Ra
R43 0-04-OR43 0-04-O
R37 0-04R37 0-04
Rb
Ca
RT8855 NC
0-04
RT8861
1.2VSB
R238
R238
4.7K-04
4.7K-04
E C
Q18 2N3904-SQ18 2N3904-S
ADJ1
ADJ1
EN_VCORE
12
B
+12V_4P
12
12
Location
RT8855
RT8861
D D
C C
ADJ
B B
A A
EN_VCORE26
C352 100P-04C352 100P-04
R315
R315
15K-1-04
15K-1-04
1U-16VX7-06
1U-16VX7-06
35
31
11
12
FB
COMP
12VCC
BOOT[1]
Ca
GND
GND
RT8855
RT8855
CSN_NB8CSP_NB
COMP_NB6FB_NB
IMAX_NB
5
13
R352 30K-1-04R352 30K-1-04
R366
R366
4.7K-04
4.7K-04
C375
C375
.01U-25VX-04
.01U-25VX-04
12
EC24
EC24
270U-16D-OS
270U-16D-OS
4
C354
C354
6800P-16VX7-04
6800P-16VX7-04
R320 2.2-06R320 2.2-06
C357
C357
C359
C359
.1U-16VX-04
.1U-16VX-04
R372
R372
0-06
0-06
PHASE1
UG1
34
33
UG[1]
PHASE[1]
12VCC_NB
7
40
R358 1K-1-04R358 1K-1-04
C374 1U-16VX7-06C374 1U-16VX7-06
R359 220-1-04R359 220-1-04
4
R316 1.5K-04R316 1.5K-04
3
1
2
LG1
32
27
LG[1]
BOOT[2]
UG_NB37BOOT_NB
36
NB_UG
12
EC26
EC26
270U-16D-OS
270U-16D-OS
C353 1000P-50VX7-04C353 1000P-50VX7-04
D29
D29
BAT54A-S
BAT54A-S
C360
C360
.1U-16VX-04
.1U-16VX-04
R371
R371
0-06
0-06
PHASE2
UG2
28
29
UG[2]
PHASE[2]
30
LG[2]
26
PWM3
25
PWM4
16
ISP[1]
15
ISN[1]
18
ISP[2]
17
ISN[2]
20
ISP[3]
19
ISN[3]
22
ISP[4]
21
ISN[4]
23
ENPS
PHASE_NB
LG_NB
38
39
Rf
NB_LG
NB_PHASE
R370
R370
0-06
0-06
C370
C370
D28
D28
.1U-16VX-04
.1U-16VX-04
1
2
BAT54A-S
BAT54A-S
NB_DPHASE
NB_ISN
C380
C380
.1U-16VY-04
.1U-16VY-04
㓡┬
”㷔ῷ檀⓷柴
090831 V1.0
+12V_MOS
12
EC25
EC25
270U-16D-OS
270U-16D-OS
CPU_COREFB+
R317 100-04R317 100-04
LG2
PWM3
R376
R376
Re
R377 6.2K-04-OR377 6.2K-04-O
R353 2.2-06R353 2.2-06
C372
C372
1U-16VX7-06
1U-16VX7-06
OCP
V1.0 change to 0402
Vincent 1110
Location of Vcore
A5VCC
1K-04
1K-04
C381
C381
100P-04-O
100P-04-O
3
CPU_COREFB+ 5
VCORE
+12V_4P
1 2
RT4
RT4
NTC-10K-1-04
NTC-10K-1-04
R340 1K-1-04R340 1K-1-04
C350 1U-16VX7-06C350 1U-16VX7-06
R341 3K-04-OR341 3K-04-O
R342 470-1-04R342 470-1-04
R346 1K-1-04R346 1K-1-04
C351 1U-16VX7-06C351 1U-16VX7-06
R347 3K-04-OR347 3K-04-O
R350 470-1-04R350 470-1-04
R354 1K-1-04R354 1K-1-04
C367 1U-16VX7-06C367 1U-16VX7-06
R355 3K-04-OR355 3K-04-O
R356 470-1-04R356 470-1-04
+12V_4P
ER72
ER72
2K-1-04
2K-1-04
NTC-10K-1-04
NTC-10K-1-04
㓦㍍役䅙㸸䘬⛘㕡
3
UG1
R318 0-06R318 0-06
PHASE1
LG1
R339 0-06R339 0-06
MF5
MF5
QM3006M6-S
QM3006M6-S
UG2
R336 0-06R336 0-06
ADJT_ADJ
DPHASE1
ISN1
C363
C363
.1U-16VY-04
.1U-16VY-04
DPHASE2
DPHASE3
ISN3
VCC
21
RT3
RT3
1 2
ISN2
C365
C365
.1U-16VY-04
.1U-16VY-04
C368
C368
.1U-16VY-04
.1U-16VY-04
VCC
21
21
3
ER73
ER73
10K-1-04
10K-1-04
ER74
ER74
3.9K-1-04
3.9K-1-04
21
V1.0 change
470-1-04
Mimic 120817
ER75 118K-1-04ER75 118K-1-04
BC129
BC129
.1U-16VY-04
.1U-16VY-04
V:1.0
Add VR_HOT
2 1
+12V_4P
3
+
+
2
-
-
PHASE2
LG2
R338 0-06R338 0-06
MF8
MF8
QM3006M6-S
QM3006M6-S
V1.0 change
0R from 3.3R
111107
UG3
R343 0-06R343 0-06
PHASE3
LG3
R349 0-06R349 0-06
NB_UG
NB_PHASE
NB_LG
V_DIMM
U35A
U35A
OP358-S
OP358-S
84
G
1
R357 0-06R357 0-06
R361 0-06R361 0-06
R378
R378
51-04
51-04
1 2
PROCHOT_L
D
Q15
Q15
2N7002-S
2N7002-S
S
MF10
MF10
QM3006M6-S
QM3006M6-S
MF12
MF12
QM3006M6-S
QM3006M6-S
+12V_MOS
G
G
+12V_MOS
G
G
+12V_MOS
G
G
+12V_MOS
G
G
2
C355 10U-16VY5-08C355 10U-16VY5-08
D1D2D3D4D5
MF1
MF1
QM3004M6-S
QM3004M6-S
S2S3S1
D1D2D3D4D5
MF6
MF6
S2S3S1
QM3006M6-S
QM3006M6-S
C361 10U-16VY5-08C361 10U-16VY5-08
D1D2D3D4D5
MF2
MF2
QM3004M6-S
QM3004M6-S
S2S3S1
D1D2D3D4D5
MF9
MF9
S2S3S1
QM3006M6-S
QM3006M6-S
C366 10U-16VY5-08C366 10U-16VY5-08
D1D2D3D4D5
MF3
MF3
QM3004M6-S
QM3004M6-S
S2S3S1
D1D2D3D4D5
MF11
MF11
S2S3S1
QM3006M6-S
QM3006M6-S
C373 10U-16VY5-08C373 10U-16VY5-08
D1D2D3D4D5
MF4
MF4
QM3004M6-S
QM3004M6-S
S2S3S1
D1D2D3D4D5
MF13
MF13
S2S3S1
QM3006M6-S
QM3006M6-S
+12V_4P
PROCHOT_L 5
2
D1D2D3D4D5
G
S2S3S1
D1D2D3D4D5
G
S2S3S1
D1D2D3D4D5
G
S2S3S1
G
S2S3S1
D21
D21
3
BAT54A-S
BAT54A-S
R364
R364
2.2-06
2.2-06
C379 1U-16VX7-06C379 1U-16VX7-06
R321
R321
1-06
1-06
C358
C358
.01U-25VX-04
.01U-25VX-04
R335
R335
1-06
1-06
C364
C364
.01U-25VX-04
.01U-25VX-04
D1D2D3D4D5
1
2
PWM3
+12V_4P
5
6
R348
R348
1-06
1-06
C369
C369
.01U-25VX-04
.01U-25VX-04
C377 .1U-16VX-04C377 .1U-16VX-04
L8 PIND-0.6UDL8 PIND-0.6UD
SU5
SU5
Short PAD
Short PAD
1 2
DPHASE1
L13 PIND-0.6UDL13 PIND-0.6UD
SU6
SU6
Short PAD
Short PAD
1 2
L14 PIND-0.6UDL14 PIND-0.6UD
SU7
SU7
Short PAD
Short PAD
1 2
DPHASE3 DPHASE2
L18 PIND-0.6UDL18 PIND-0.6UD
SU8
SU8
R360
R360
Short PAD
Short PAD
1-06
1-06
1 2
C378
C378
.01U-25VX-04
.01U-25VX-04
NB_DPHASE
PWM4
PWM4
1
BST
DRVH
4
VCC
2
IN
DRVL
3
NC
PGND
RT9612BZS
RT9612BZS
02-415-612791
U35B
U35B
OP358-S
OP358-S
84
+
+
7
-
-
1
21
SU9
SU9
Short PAD
Short PAD
1 2
ISN1
21
SU10
SU10
Short PAD
Short PAD
1 2
ISN2ISN3
21
SU11
SU11
Short PAD
Short PAD
1 2
21
R363 0-06R363 0-06
8
7
SW
5
6
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
12
EC40
EC40
820U-2V5D6H8E
820U-2V5D6H8E
12
EC36
EC36
820U-2V5D6H8E
820U-2V5D6H8E
12
SU12
SU12
Short PAD
Short PAD
EC69
EC69
820U-2V5D6H8E
820U-2V5D6H8E
1 2
NB_ISN
UG3
PHASE3
LG3
Elitegroup Computer Systems
Elitegroup Computer Systems
Elitegroup Computer Systems
Power (CPU Vcore RT8802)
Power (CPU Vcore RT8802)
Power (CPU Vcore RT8802)
A960M-MV
A960M-MV
A960M-MV
12
12
12
1
VCORE
EC38
EC38
820U-2V5D6H8E
820U-2V5D6H8E
EC37
EC37
820U-2V5D6H8E
820U-2V5D6H8E
CPU_VDDNB
EC68
EC68
820U-2V5D6H8E
820U-2V5D6H8E
10
10
10
1.0A
1.0A
1.0A
32Thursday, October 11, 2012
32Thursday, October 11, 2012
32Thursday, October 11, 2012
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