ecom EC5X43S Users Manual

Test report no. 18011460 Page 1 of 1

EUT: MODUL-AX5243_S

FCC ID: R2ZEC5X43S

FCC Title 47 CFR Part 15

Date of issue: 2018-08-16

Date: 2018-06-06

Created: P4 Reviewed: P9 Released: P1

Vers. No. 1.18

TÜV NORD Hochfrequenztechnik GmbH & Co. KG Rottland 5a, 51429 Bergisch Gladbach, Germany

Tel: +49 2207 9689-0

Fax +49 2207 9689-20

Annex acc. to FCC Title 47 CFR Part 15

relating to

ecom GmbH

MODUL-AX5243_S

Annex no. 5

User Manual

Functional Description

Title 47 - Telecommunication

Part 15 - Radio Frequency Devices

Subpart C – Intentional Radiators

ANSI C63.4-2014

ANSI C63.10-2013

AND9347/D

AX5043 Programming Manual

Advances High Performance ASK and FSK Narrow-Band Transceiver for 27−1050 MHz Range

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OVERVIEW

AX5043 is a true single chip low-power CMOS transceiver for narrow band applications. A fully integrated VCO supports carrier frequencies in the 433 MHz, 868 MHz and 915 MHz ISM band. An external VCO inductor enables carrier frequencies from 27 MHz to 1050 MHz. The on-chip transceiver consists of a fully integrated RF front-end with modulator, and demodulator. Base band data processing is implemented in an advanced and flexible communication controller that enables user friendly communication via the SPI interface.

APPLICATION NOTE

An on-chip low power oscillator as well as Wake-on-radio enable very low power standby applications. The AX5043 is also available with the AX8052F100 microcontroller in a single integrated circuit as the AX8052F143. Figure 1 shows the block diagram of the AX5043.

February, 2017 − Rev. 4

Figure 1. Block Diagram

1 Publication Order Number:

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TABLE OF CONTENTS

Overview 1........................................................................................

FIFO Operation 7...................................................................................

Programming the Chip 12............................................................................

References 74......................................................................................

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AX5043

28 27 26 25 24 23 22

8 9 10 11 12 13 14

ANTSEL

IRQ

PWRAMP

MOSI

MISO

CLK

VDD_ANA

GND

ANTP

ANTN

ANTP1

GND

VDD_ANA

FILT

DATA

DCLK

SYSCLK

CLK16P

CLK16N

GPADC2

GPADC1NCVDD_IO

SEL

AX8052F100

other mC

28 27 26 25 24 23 22

8 9 10 11 12 13 14

RESET_N

PB7/DBG_CLK

DBG_EN

PB6/DBG_DATA

PB5/U0RX/T1OUT

PB4/U0TX/T1CLK

PB3/OC0/T2CLK/EXTIRQ1/DSWAKE

RIRQ/PR5

VDD_CORE

RMOSI/PR4

RMISO/PR3

RCLK/PR2

RSEL/PR0

RSYSCLK/PR1

OMPO0/U0RX/SMISO/PC3

U 0T X/S MO SI/P C2

OMPO1/T0CLK/SSCK/PC1

XTIRQ0/T0OUT/SSEL/PC0

EXTIRQ0/IC1/U1TX/PB0

OC1/U1RX/PB1

T2OUT/IC0/PB2

PA5/ADC5/IC0/U1TX/COMPI10

PA4/ADC4/T1CLK/COMPO0/LPXTA

PA3 /AD C3/T 1O UT/L PX TAL P

PA 2/A DC 2 /OC 0/U 1R X/C OM PI0 0

PA1/ADC1/T0CLK/OC1/XTALP

PA 0/A DC 0/T 0 OU T/IC 1/X TAL N

VDD_IO

IRQ

MOSI MISO

CLK

SYSCLK

Connecting the AX5043 to an AX8052F100 or other Microcontroller

The AX5043 can easily be connected to an AX8052F100 or any other microcontroller. The microcontroller communicates with the AX5043 via a register file that is implemented in the AX5043 and that can be accessed serially via an industry standard Serial Peripheral Interface (SPI) protocol.

Reset is performed by the integrated power-on-reset (POR) block and can be performed manually via the register file.

The AX5043 sends and receives data via the SPI port in frames. This standard operation mode is called frame mode.

In frame mode, the internal communication controller performs frame delimiting, and data is received and transmitted via a 256 Byte FIFO, accessible via the register file. The FIFO is shared between receive and transmit. Figure 2 shows the corresponding diagram. Connecting the interrupt line is highly recommended, though not strictly required. With the AX8052F100, it is also recommended to connect the SYSCLK line. This allows the Microcontroller to run from the precise crystal clock of the AX5043, or to calibrate its internal oscillators from against this clock.

Figure 2. Connecting AX5043 to AX8052F100 or other mC

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Pin Function Descriptions

Table 1. PIN FUNCTION DESCRIPTION

Symbol Pin(s) Type Description

VDD_ANA 1 P Analog power output, decouple to neighboring GND

GND 2 P Ground, decouple to neighboring VDD_ANA ANTP 3 A Differential antenna input/output ANTN 4 A Differential antenna input/output

ANTP1 5 A Single-ended antenna output

GND 6 P Ground, decouple to neighboring VDD_ANA

VDD_ANA 7 P Analog power output, decouple to neighboring GND

FILT 8 A Optional synthesizer filter

L2 9 A Optional synthesizer inductor L1 10 A Optional synthesizer inductor

DATA 11 I/O In wire mode: Data in-out/output

Can be programmed to be used as a general purpose I/O pin Selectable internal 65 kΩ pull-up resistor

DCLK 12 I/O In wire mode: Clock output

Can be programmed to be used as a general purpose I/O pin Selectable internal 65 kΩ pull-up resistor

SYSCLK 13 I/O Default functionality: Crystal oscillator (or divided) clock output

Can be programmed to be used as a general purpose I/O pin

Selectable internal 65 kΩ pull-up resistor SEL 14 I Serial peripheral interface select CLK 15 I Serial peripheral interface clock

MISO 16 O Serial peripheral interface data output MOSI 17 I Serial peripheral interface data input

NC 18 N Must be left unconnected

IRQ 19 O Default functionality: Transmit and receive interrupt

Can be programmed to be used as a general purpose I/O pin

Selectable internal 65 kΩ pull-up resistor

PWRAMP 20 I/O Default functionality: Power amplifier control output

Can be programmed to be used as a general purpose I/O pin

Selectable internal 65 kΩ pull-up resistor

ANTSEL 21 I/O Default functionality: Diversity antenna selection output

Can be programmed to be used as a general purpose I/O pin

Selectable internal 65 kΩ pull-up resistor

NC 22 N Must be left unconnected

VDD_IO 23 P Power supply 1.8 V – 3.6 V

NC 24 N Must be left unconnected GPADC1 25 A GPADC input GPADC2 26 A GPADC input

CLK16N 27 A Crystal oscillator input/output CLK16P 28 A Crystal oscillator input/output

GND Center Pad P Ground on center pad of QFN, must be connected

A = analog signal I = digital input signal O = digital output signal I/O = digital input/output signal N = not to be connected P = power or ground

All digital inputs are Schmitt trigger inputs, digital input and output levels are LVCMOS/LVTTL compatible and 5 V tolerant.

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SPI Register Access

Registers are accessed via a synchronous Serial Peripheral Interface (SPI). Most Registers are 8 bits wide and accessed using the waveforms as detailed in Figure 3. These

SCK

R/W A7S7A6 A5 A4 A3 A2 A1

MOSI

MISO

S14 S13 S12 S11 S9A8S8

A11 A10 A9

111

S6 S5 S4 S3 S2 S1A0S0

Figure 3. SPI 8bit Long Address Read/Write Access

The most important registers are at the beginning of the address space, i.e. at addresses less than 0x70. These

Figure 4. SPI 8bit Read/Write Access

Some registers are longer than 8 bits. These registers can be accessed more quickly than by reading and writing individual 8 bit parts. This is illustrated in Figure 5. Accesses are not limited by 16 bits either, reading and writing data

waveforms are compatible to most hardware SPI master controllers, and can easily be generated in software. MISO changes on the falling edge of CLK, while MOSI is latched on the rising edge of CLK.

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0S10

registers can be accessed more efficiently using the short address form, which is detailed in Figure 4.

bytes can be continued as long as desired. After each byte, the address counter is incremented by one. Also, this access form also works with long addresses.

SCK

R/W A6 A5 A4 A3 A2 A1 A0

MOSI

MISO

S14 S13 S12 S11 S10 S9 S8

D7 D6 D5 D4 D3 D2 D1 D0

A A+1

Figure 5. SPI 16bit Read/Write Access

During the address phase of the access, the chip outputs the most important status bits. This feature is designed to

handler. The table below shows which register bit is transmitted during the status timeslots.

speed up software decision on what to do in an interrupt

Table 2. SPI STATUS BITS

SPI Bit Cell Status Register Bit

0 − 1 (when transitioning out of deep sleep, this bit transitions from 0→1 when the power becomes ready) 1 S14 PLL LOCK 2 S13 FIFO OVER 3 S12 FIFO UNDER 4 S11 THRESHOLD FREE ( FIFO Free > FIFO threshold) 5 S10 THRESHOLD COUNT (FIFO count > FIFO threshold) 6 S9 FIFO FULL 7 S8 FIFO EMPTY 8 S7 PWRGOOD (not BROWNOUT)

9 S6 PWR INTERRUPT PENDING 10 S5 RADIO EVENT PENDING 11 S4 XTAL OSCILLATOR RUNNING

D7 D6 D5 D4 D3 D2 D1 D0

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Table 2. SPI STATUS BITS (continued)

SPI Bit Cell Register BitStatus

12 S3 WAKEUP INTERRUPT PENDING 13 S2 LPOSC INTERRUPT PENDING 14 S1 GPADC INTERRUPT PENDING 15 S0 undefined

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Note that bit cells 8−15 (S7…S0) are only available in two

address byte SPI access formats.

Deep Sleep

The chip can be programmed into deep sleep mode. In deep sleep mode, the chip is completely switched off, which results in very low leakage power. All registers loose their programming.

To enter deep sleep mode, write the deep sleep encoding into bits 3:0 of PWRMODE. At the rising edge of the SEL line, the chip will enter deep sleep mode.

To exit deep sleep mode, lower the SEL line. This will initiate startup and reset of the chip. Then poll the MISO line. The MISO line will be held low during initialization, and will rise to high at the end of the initialization, when the chip becomes ready for further operation.

Address Space

The address space has been allocated as follows. Addresses from 0x000 to 0x06F are reserved for “dynamic registers”, i.e. registers that are expected to be frequently accessed during normal operation, as they can be efficiently accessed using single address byte SPI accesses. Addresses from 0x070 to 0x0FF have been left unused (they could only be accessed using the two address byte SPI format). Addresses from 0x100 to 0x1FF have been reserved for physical layer parameter registers, for example receiver, transmitter, PLL, crystal oscillator. Adresses from 0x200 to 0x2FF have been reserved for medium access parameters, such as framing, packet handling. Addresses from 0x300 to 0x3FF have been reserved for special functions, such as GPADC.

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FIFO OPERATION

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The AX5043 features a 256 Byte FIFO. The same FIFO is used for both reception and transmission. During transmit, only the write port is accessible by the microcontroller. During receive, only the read port is accessible by the microcontroller. Otherwise, both ports are accessible through the register file.

In order to prevent transmitting premature data, the FIFO contains three pointers. Data is read at the read pointer, up to the write pointer. Data is written to the write ahead pointer . The write pointer is not updated when data is written, therefore, new data is not immediately visible to the consumer. Writing the COMMIT command to the FIFOSTAT register copies the write ahead pointer to the write pointer, thus making the written data visible to the

Write ahead pointer

Write pointer

FIFOCOUNT

receiver. Writing the ROLLBACK command to the FIFOSTAT register sets the write ahead pointer to the write pointer, thus discarding data written to the FIFO. During transmit, this means that the transmitter will only consider data written to the FIFO after the commit command. During receive, this feature is used by the receiver to store packet data before it is known whether the CRC check passes. FIFOCOUNT reports the number of bytes that can be read without causing an underflow. FIFOFREE reports the number of bytes that can be written without causing an overflow. FIFOCOUNT and FIFOFREE do not add up to 256 Bytes whenever there are uncommitted bytes in the FIFO. Figure 6 illustrates this.

256−FIFOFREE

Figure 6. FIFO Pointer

FIFO Chunk Encoding

In order to distinguish meta-data (such as RSSI) from receive or transmit data, FIFO contents are organized as chunks. Chunks consist of a header that encodes the chunk length as well as the payload data format.

Each chunk starts with a single byte header. The header encodes the length of a chunk, and indicates the data it contains. The top 3 bits encode the length (or optionally refer to an additional length byte after the header byte), and the bottom 5 bits indicate what payload data the chunk contains. The following table lists the encoding of the length bits (top 3 bits of the first chunk header byte). Figure 7 shows the chunk header byte encoding.

Table 3. CHUNK PAYLOAD SIZE ENCODING

Top Bits Chunk Payload Size

000 No payload 001 Single byte payload 010 Two byte payload 011 Three byte payload

Read pointer

76543210

Chunk

payload

size

Figure 7. FIFO Header byte Format

Chunk

payload

data format

The following table lists the chunk payload size encoding:

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Table 3. CHUNK PAYLOAD SIZE ENCODING (continued)

Top Bits Chunk Payload Size

100 Invalid 101 Invalid 110 Invalid 111 Variable length payload; payload size is encoded in the following length byte the length byte is part of

the header (and not included in length), everything after the length byte is included in the length

The following table lists the chunk types and their encodings. The Hdr Byte column lists the complete FIFO Chunk Header Byte, consisting of the length and data format encodings.

Table 4. CHUNK TYPES AND THEIR ENCODINGS

Name Dir

No Payload Commands

NOP

One Byte Payload Commands

RSSI

TXCTRL

Two Byte Payload Commands

FREQOFFS

ANTRSSI2

Three Byte Payload Commands

REPEATDATA

TIMER

RFFREQOFFS

DATARATE

ANTRSSI3

Variable Length Payload Commands

DATA

TXPWR

T 00000000 No Operation

R 00110001 RSSI T 00111100 Transmit Control

R 01010010 Frequency Offset R 01010101 Background Noise

T 01100010 Repeat Data R 01110000 Timer R 01110011 RF Frequency Offset R 01110100 Datarate R 01110101 Antenna Selection RSSI

TR 11100001 Data T 11111101 Transmit Power

Hdr. Byte

7−0

Description

(Antenna, Power Amp)

Calculation RSSI

Direction: T = Transmit, R = Receive

NOP Command

Table 5. NOP COMMAND

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0

The NOP command will be discarded without effect by the transmitter. The receiver will not generate NOP commands.

RSSI Command

Table 6. RSSI COMMAND

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0

RSSI

The RSSI command will only be generated by the receiver at the end of a packet if bit STRSSI is set in register PKTSTOREFLAGS. The encoding is the same as that of the RSSI register.

TXCTRL Command

Table 7. TXCTRL COMMAND

7 6 5 4 3 2 1 0

0 0 1 1 1 1 0 0 0 SETTXTXSE TXDIFFSETANTANTS

TATE

SETPAPAST

ATE

The TXCTRL command allows certain aspects of the transmitter to be changed on the fly. If SETTX is set, TXSE and TXDIFF are copied into the register MODCFGA. If SETANT is set, ANTSTATE is copied into register DIVERSITY. If SETPA is set, PASTATE is copied into register PWRAMP.

FREQOFFS Command

Table 8. FREQOFFS COMMAND

7 6 5 4 3 2 1 0

0 1 0 1 0 0 1 0

FREQOFFS1 FREQOFFS0

The FREQOFFS command will only be generated by the receiver at the end of a packet if bit STFOFFS is set in register PKTSTOREFLAGS. The encoding is the same as that of the TRKFREQ register.

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ANTRSSI2 Command

Table 9. ANTRSSI2 COMMAND

7 6 5 4 3 2 1 0

0 1 0 1 0 1 0 1

RSSI

BGNDNOISE

REPEATDATA Command

Table 10. REPEATDATA COMMAND

7 6 5 4 3 2 1 0

0 1 1 0 0 0 1 0 0 0 UNENC RAW NOCRC RESIDUE PKTEND PKTSTART

REPEATCNT

DATA

The ANTRSSI2 command will be generated by the receiver when it is idle if bit STANTRSSI is set in register PKTSTOREFLAGS. If DIVENA is set in register DIVERSITY, the ANTRSSI3 command is generated instead. The encoding of the RSSI field is the same as that of the RSSI register. The BGNDNOISE field contains an estimate of the background noise.

The REPEATDATA command allows the efficient transmission of repetitive data bytes. The DATA byte given in the payload is repeated REPEATCNT times. See DATA command for a description of the flag byte. This command is especially handy for constructing preambles.

TIMER Command

Table 11. TIMER COMMAND

7 6 5 4 3 2 1 0

0 1 1 1 0 0 0 0

TIMER2 TIMER1 TIMER0

The TIMER command will only be generated by the receiver at the start of a packet if bit STTIMER is set in register PKTSTOREFLAGS. The payload is a copy of the µs timer TIMER register. This command enables exact packet timing for example for frequency hopping systems.

RFFREQOFFS Command

Table 12. RFFREQOFFS COMMAND

7 6 5 4 3 2 1 0

0 1 1 1 0 0 1 1

RFFREQOFFS2 RFFREQOFFS1 RFFREQOFFS0

The RFFREQOFFS command will only be generated by the receiver at the end of a packet if bit STRFOFFS is set in register PKTSTOREFLAGS. The encoding is the same as that of the TRKRFFREQ register.

DATARATE Command

Table 13. DA TARATE COMMAND

7 6 5 4 3 2 1 0

0 1 1 1 0 1 0 0

DATARATE2 DATARATE1 DATARATE0

The DATARATE command will only be generated by the receiver at the end of a packet if bit STDR is set in register PKTSTOREFLAGS. The encoding is the same as that of the TRKDATARATE register.

ANTRSSI3 Command

Table 14. ANTRSSI3 COMMAND

7 6 5 4 3 2 1 0

0 1 1 1 0 1 0 1

ANTORSSI2 ANTORSSI1 ANTORSSI0

The ANTRSSI3 command will be generated by the receiver when it is idle if bit STANTRSSI is set in register PKTSTOREFLAGS. If DIVENA is not set in register DIVERSITY, the ANTRSSI2 command is generated instead. The encoding of the ANT0RSSI and ANT1RSSI fields are the same as that of the RSSI register. The BGNDNOISE field contains an estimate of the background noise.

DATA Command

The DATA command transports actual transmit and receive data. While the basic format is the same for transmit and receive, the semantics of the flag byte differs.

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Table 15. TRANSMIT DATA FORMAT

7 6 5 4 3 2 1 0

1 1 1 0 0 0 0 1

LENGTH

0 0 UNENC RAW NOCRC RESIDUE PKTEND PKTSTART

DATA

LENGTH includes the flags byte as well as all DATA

bytes.

Setting RAW to one causes the DATA to bypass the

framing mode, but still pass through the encoder.

Setting UNENC to one causes the DATA to bypass the framing mode, as well as the encoder, except for inversion. UNENC has priority over RAW.

Setting NOCRC suppresses the generation of the CRC bytes.

Setting RESIDUE allows the transmission of a number of data bits that is not a multiple of eight. All but the last data byte are transmitted as if RESIDUE was not set. The last byte however contains only 7 bits or less. The transmitter looks for the highest bit set. This is considered the stop bit. Only bits below the stop bit are transmitted. If the MSBFIRST in register PKTADDRCFG is set, the algorithm

Table 16. FIFO COMMAND

0xE1 FIFO Command 0x04 Length Byte 0x24 Flag Byte: Unencoded, to ensure 0−1 remains 0−1, and Residue set, because the number of bits

transmitted is not a multiple of 8 0xAA Alternating 0−1 bits 0xAA Alternating 0−1 bits 0x1A Alternating 0−1 bits; Bit 4 is the “Stop” bit

is reversed, i.e. the lowest bit set is considered the stop bit and bits above the stop bit are transmitted.

PKTSTART and PKTEND bits enable the transmission of packets that are larger than the FIFO size. If PKTSTART is set, the radio packet starts at the beginning of the DATA command payload. If PKTEND is set, the radio packet ends at the end of the DA TA command payload. If PKTSTART is not set, this command is the continuation of a previous DATA command. If PKTEND is not set, the packet is continued with the next DATA command.

PKTSTART in RAW mode causes the DATA bytes to be aligned to DiBit boundaries in 4−FSK mode.

For example, to transmit 20 bits of an alternating 0−1 pattern as a preamble, the following bytes should be written to the FIFO (MSBFIRST = 0 in register PKTADDRCFG is assumed):

Table 17. RECEIVE DATA FORMAT

7 6 5 4 3 2 1 0

1 1 1 0 0 0 0 1

LENGTH

0 ABORT SIZEFAIL ADDRFAIL CRCFAIL RESIDUE PKTEND PKTSTART

DATA

ABOR T i s set if the packet has been aborted. An ABORT sequence is a sequence of seven or more consecutive one bits when HDLC [1] framing is used. Note that if ACCPTABR T is not set in register PKTACCEPTFLAGS, then aborted packets are silently dropped.

SIZEFAIL is set if the packet does not pass the size checks. Size checks are implemented using the PKTLENCFG, PKTLENOFFSET and PKTMAXLEN registers. Note that if ACCPTSZF is not set in register PKTACCEPTFLAGS, then packets with an invalid size are silently dropped.

ADDRFAIL is set if the packet does not pass the address checks. Address checks are implemented using the

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PKTADDRCFG, PKTADDR and PKTADDRMASK registers. Note that if ACCPTADDRF is not set in register PKTACCEPTFLAGS, then packets which do not match the programmed address are silently dropped.

CRCF AIL i s set if the packet does not pass the CRC check. Note that if ACCPTCRCF is not set in register PKTACCEPTFLAGS, then packets which fail the CRC check are silently dropped.

RESIDUE, PKTEND and PKTSTART work identical as in transmit mode, see above.

The receiver generates chunks up to PKTCHUNKSIZE bytes. If PKTMAXLEN is larger than PKTCHUNKSIZE, multiple chunks may be generated for one packet. Since

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CRC and size checks may only be performed at the end of the packet, only the last chunk can be dropped at failure of one of those tests. It is therefore important that the microcontroller receiver routine clears its receive buffer at the beginning of DATA commands whose PKTSTART bit is set, as the buffer may still contain bytes from erroneous packets.

TXPWR Command

Table 18. TXPWR COMMAND

7 6 5 4 3 2 1 0

1 1 1 1 0 0 1 0

LENGTH = 10

TXPWRCOEFFA (7:0)

TXPWRCOEFFA (15:8)

TXPWRCOEFFB (7:0)

TXPWRCOEFFB (15:8)

TXPWRCOEFFC (7:0)

TXPWRCOEFFC (15:8)

TXPWRCOEFFD (7:0)

TXPWRCOEFFD (15:8)

TXPWRCOEFFE (7:0)

TXPWRCOEFFE (15:8)

The TXPWR command allows the transmit power to be changed on the fly. This command updates the TXPWRCOEFFA, TXPWRCOEFFB, TXPWRCOEFFC, TXPWRCOEFFD and TXPWRCOEFFE registers.

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PROGRAMMING THE CHIP

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Power Modes

To enable the lowest possible application power

consumption, the AX5043 allows to shut down its circuits

Table 19. PWRMODE REGISTER STATES

PWRMODE register Name Description Typical Idd

0000 POWERDOWN Powerdown; all circuits powered down except for the register file 400 nA 0001 DEEPSLEEP Deep Sleep Mode; Chip is fully powered down until SEL is lowered

again; looses all register contents 0101 STANDBY Crystal Oscillator enabled 230 μA 0111 FIFOON FIFO and Crystal Oscillator enabled 310 μA 1000 SYNTHRX Synthesizer running, Receive Mode 5mA 1001 FULLRX Receiver Running 1011 WORRX Receiver Wake-on-Radio Mode 500 nA 1100 SYNTHTX Synthesizer running, Transmit Mode 5mA 1101 FULLTX Transmitter Running

The following list explains the typical programming flow. Preparation:

1. Reset the Chip. Set SEL to high for at least 1μs, then low. Wait until MISO goes high. Set, and then clear, the RST bit of register PWRMODE.

2. Set the PWRMODE register to POWERDOWN.

3. Program parameters. It is recommended that suitable parameters are calculated using the AX_RadioLab tool available from Axsem.

4. Perform auto-ranging, to ensure the correct VCO

when not needed. This is controlled by the PWRMODE register. Idd values are typical; for exact values, please refer to the AX5043 datasheet [2].

50 nA

7-11 mA

6−70 mA

mode, the FIFO is automatically kept powered until it is emptied by the microprocessor.

In the transmit case, PWRMODE should first be set to FULLTX. Before writing to the FIFO, the microprocessor must ensure that the SVMODEM bit is high in Register POWSTAT, to ensure that the on-chip voltage regulator supplying the FIFO has finished starting up. The transmitter remains idle until the contents of the FIFO are committed (unless the FIFO AUTO COMMIT bit is set in Register FIFOSTAT).

range setting.

The chip is now ready for transmit and receive operations.

FIFO Power Management

The FIFO is powered down during POWERDOWN and DEEPSLEEP modes (Register PWRMODE). The FIFO EMPTY and FIFO FULL bits (Register FIFOSTAT), as well as the FIFOCOUNT and FIFOFREE registers read zero. Reads from the FIFO will return undefined data, and writes to the FIFO will be lost.

In the receive case, the FIFO is automatically powered on when the chip PWRMODE is set to FULLRX. The FIFO should be emptied before the PWRMODE is set to

Autoranging

Whenever the frequency changes, the synthesizer VCO should be set to the correct range using the built-in autoranging. A re-ranging of the VCO is required if the frequency change required is larger than 5 MHz in the 868/915 MHz band or 2.5 MHz in the 433 MHz band. Each individual chip must be auto-ranged. If both frequency register sets FREQA and FREQB are used, then both frequencies must be auto-ranged by first starting auto-ranging in PLLRANGINGA, waiting for its completion, followed by starting auto-ranging in PLLRANGINGB and waiting for its completion.

POWERDOWN. In Wake-on-radio or POWERDOWN

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Figure 8 shows the flow chart of the auto-ranging process.

Set PWRMODE to STANDBY

Enable TCXO if used

Wait until crystal oscillator

Set RNGSTART of PLLRANGINGA/B

Set PWRMODE to POWERDOWN

Figure 8. Autoranging Flow Chart

is ready

RNGSTART = 1?

RNGERR = 1?

Disable TCXO if used

yes

Error

Before starting the auto-ranging, the appropriate frequency registers (FREQA3, FREQA2, FREQA1 and FREQA0 or FREQB3, FREQB2, FREQB1 and FREQB0) need to be programmed. Auto-ranging starts at the VCOR (register PLLRANGINGA or PLLRANGINGB) setting; if you already know the approximately correct synthesizer VCO range, you should set VCORA/VCORB to this value prior to starting auto-ranging; this can speed up the ranging process considerably . If you have no prior knowledge about the correct range, set VCORA/VCORB to 8. Starting with VCORA/VCORB < 6 should be avoided, as the initial synthesizer frequency can exceed the maximum frequency specification.

Hardware clears the RNG START bit automatically as soon as the ranging is finished; the device may be programmed to deliver an interrupt on resetting of the RNG START bit.

Waiting until auto-ranging terminates can be performed by either polling the register PLLRANGINGA or PLLRANGINGB for RNG START to go low, or by enabling the IRQMPLLRNGDONE interrupt in register IRQMASK1.

Choosing the Fundamental Communication Characteristics

The following table lists the fundamental communication characteristics that need to be chosen before the device can be programmed.

Table 20. FUNDAMENTAL COMMUNICATION CHARACTERISTIC

Parameter Description

XTAL

modulation FSK, MSK, OQPSK, 4−FSK or AFSK (for recommendations see below) f

CARRIER

BITRATE Desired bit rate in bit/s h Modulation index, determines the frequency deviation for FSK

encoding Inversion, differential, manchester, scrambled, for recommendations see the description of the register

Frequency of the connected crystal in Hz

Carrier frequency (i.e. center frequency of the signal) in Hz

32 > h ≥ 0.5 for FSK, 4−FSK or AFSK, f h = 0.5 for MSK and OQPSK (For AFSK, f

often approximately 3 kHz)

ENCODING.

is usually set according to the FM channel specification. For 25 kHz channels, it is

deviation

= 0.5 * h * BITRATE

deviation

The following table gives an overview of the trade-offs between the different modulations that AX5043 offers, they should be considered when making a choice.

Table 21. TRADE-OFFS BETWEEN THE DIFFERENT MODULATION

Modulation Trade-offs

XTAL

FSK For bit rates up to 125 kbit/s

Frequency of the connected crystal in Hz

Frequency deviation is a free parameter

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x16+x12+x5+1

Table 21. TRADE-OFFS BETWEEN THE DIFFERENT MODULATION (continued)

Modulation Trade-offs

MSK For bit rates up to 125 kbit/s

Robust and spectrally efficient form of FSK (Modulation is the same as FSK with h = 0.5) Frequency deviation given by bit rate The advantage of MSK over FSK is that it can be demodulated with higher sensitivity. Slightly longer preambles required than for FSK

OQPSK For bit rates up to 125 kbit/s

Very similar to MSK, with added precoding / postdecoding For new designs, use MSK instead

PSK For bit rates up to 125 kBit/s

Spectrally efficient and high sensitivity Very accurate frequency reference (maximum carrier frequency deviation ±

preambles required

4−FSK For bit rates up to 100 kSymbols/s, or 200 kbit/s

Similar to FSK, but four frequencies are used to transmit 2 bits simultaneously Very slightly more spectrally efficient compared to FSK

((1 + 3 h/2) ⋅ BITRATE versus (1 + h) ⋅ BITRATE) for small h. Longer preambles required as frequency offset estimation needs to be more precise to successfully

demodulate For new designs, use FSK instead

AFSK For bit rates up to 25 kbit/s

Bits are FSK modulated in the audio band, then frequency modulated on the carrier frequency. For legacy compatibility applications only.

/4 ⋅ BITRATE) and long

Given these fundamental physical layer parameters, AX_RadioLab should be used to compute the register settings of the AX5043.

Framing

Figure 1 shows the block diagram of the AX5043. After the user writes a transmit packet into the FIFO, the Radio Controller sequences the transmitter start-up, and signals the Packet Controller to read the packet from the FIFO and add framing bits, allowing the receiver to lock to the transmit waveform, and to detect packet and byte boundaries. If MSB first is selected (register PKTADDRCFG), then the bits within each byte are swapped when the data is read out from the FIFO.

The Packet Controller also (optionally) adds cyclic redundancy check bits at the end of the packet, to enable the receiver to detect transmission errors. Both 16 and 32 Bit CRC can be selected, as well as different generator polynomials. The CRC polynomial can be selected in register FRAMING. The following polynomials are supported:

• CRC-CCITT (16bit):

(hexadecimal: 0x1021)

• CRC-16 (16bit):

+ x15+ x2+1

(hexadecimal: 0x8005)

• CRC-DNP (16bit):

+ x13+ x12+ x11+ x10+ x8+ x6+ x5+ x2+1

(hexadecimal: 0x3D65)

This polynomial is used for Wireless M-Bus.

• CRC-32 (32bit):

+ x26+ x23+ x22+ x16+ x12+ x11+ x10+ x8+ x7+

x4+ x2+x+

(hexadecimal: 0x04C11DB7)

The CRC is always transmitted MSB first regardless of the MSB first setting of register PKTADDRCFG, to enable the receiver to process CRC bits as they arrive (otherwise, they would have to be stored and reordered). For an in-depth guide on how CRC’s are computed, see [3].

Finally, the encoder is able to perform certain bit-wise operations on the bit-stream:

• Manchester:

Manchester transmits a one bit as 10 and a zero bit as 01, i.e. it doubles the data rate on the radio channel. Its advantage is that the resulting bit-stream has many transitions and thus simplifies synchronizing to the transmission on the receiver side. The downside is that it now requires twice the amount of energy for the transmission. Manchester is not recommended, except for compatibility with legacy systems.

• Scrambler:

The scrambler ensures that even highly regular transmit data results in a seemingly random transmitted bit-stream. This avoids discrete tones in the spectrum. Do not confuse the scrambler with encryption – it does not provide any secrecy, its actions are easily reversed. Its use is recommended.

• Differential:

Differential transmits zero bits as constant level, and one bits as level change. This allows to accomodate

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modulations that can invert the bit-stream, such as PSK. It is available for compatibility with other Axsem transceivers, but usually not used on the AX5043.

• Inversion:

If on, the bit-stream is inverted. Useful for example for compatibility with legacy systems, such as POCSAG, which differ from the usual convention that the higher FSK frequency signifies a one.

The encoder is controlled using the register ENCODING. It may be temporarily bypassed except for the inversion by setting the UNENC bit of the FIFO chunks DATA or REPEATDATA. This is useful for synthesizing preambles.

The receiver performs these tasks in reverse order.

Transmitter

Figure 9 shows the transmitter flow chart. The microprocessor first places the chip into FULLTX mode. This prepares the chip for a future transmission, enables the FIFO in transmit direction, but does not yet power-up the synthesizer or any other transmit circuitry.

The microprocessor can now write the preamble and the actual packet to the FIFO. The preamble is programmable to allow standards to be implemented that specify a specific preamble to be used. Otherwise, the recommendations for preambles can be found below.

Waiting for the crystal oscillator to start up may be performed by polling the register XTALSTATUS, or by enabling the IRQMXTALREADY interrupt in register IRQMASK1.

After the FIFO contents are committed (writing the Commit command to the FIFOSTAT register), the transmitter notices that the FIFO is no longer empty. It then powers up the synthesizer and settles it (registers TMGTXBOOST and TMGTXSETTLE determine the timing). The Preamble and the Packet(s) are then transmitted, followed by the transmitter and synthesizer shut-down.

The transmitter is automatically ramped up and down smoothly, to prevent unwanted spurious emissions. The ramp time is normally one bit time, but may be longer by changing the SLOWRAMP field of register MODCFGA.

The PWRMODE register should stay at FULLTX until the transmission is fully completed. The end of the transmission may be determined by polling the register RADIOSTATE until it indicates idle, or by enabling the radio controller interrupt (bit IRQMRADIOCTRL) in register IRQMASK0 and setting the radio controller to signal an interrupt at the end of transmission (bit REVMDONE of register RADIOEVENTMASK0).

Set PWRMODE to FULLTX

Enable TCXO if used

Write Preamble to FIFO

Write Packet to FIFO

Wait until crystal oscillator

Wait until transmission is done

Set PWRMODE to POWERDOWN

is running

Commit FIFO

Disable TCXO if used

Figure 9. Transmitter Flow Chart

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Recommended Preamble

The main purpose of the preamble is to allow for the receiver to acquire vital transmission parameters before the actual packet data starts. The minimum duration of the preamble is dependent on how much time the receiver needs to acquire these parameters to sufficient precision. More specifically, it depends on:

• The time needed for the receiver adaptive gain control

(AGC) to acquire the signal strength.

• The time needed for the receiver to acquire the

maximum possible frequency offset (registers MAXRFOFFSET0, MAXRFOFFSET1 and MAXRFOFFSET2).

• The time needed for the receiver to acquire the

maximum possible data rate offset (registers MAXDROFFSET0, MAXDROFFSET1 and MAXDROFFSET2).

• The time needed for the receiver to acquire the exact bit

sampling time (registers TIMEGAIN0, TIMEGAIN1, TIMEGAIN2 and TIMEGAIN3).

• The time needed to acquire the actual frequency

deviation in 4−FSK mode (registers FSKDMAX0, FSKDMAX1, FSKDMIN0 and FSKDMAX0).

On the AX5043, these loops run in parallel. An AGC that is significantly off however causes the received signal to fall outside the IF strip dynamic range, and thus prevents the other loops from working. And a frequency offset that is compensated insufficiently causes the received signal to fall (partially) outside the IF filter, thus also preventing the timing and 4−FSK loops from working.

The minimum possible preamble duration can be achieved under the following conditions:

• Use a transmitter with a sufficiently precise bit timing.

If the maximum deviation of the transmitter data rate from the receiver data rate is less than approximately

0.1%, then the data rate acquisition loop should be switched off completely (setting registers

MAXDROFFSET0, MAXDROFFSET1 and MAXDROFFSET2 to zero). The AX5043 is able to track the remaining small offset without the data rate offset loop. All Axsem transmitters derive the bit rate timing from the crystal reference and can therefore easily meet this requirement.

• Use an FSK frequency deviation that is larger than the

maximum frequency offset between transmitter and receiver. In this case, receiver frequency offset acquisition is not needed. Do not use 4−FSK.

• Use the AX5043 receiver parameter set feature, below.

Finally, the frame synchronization word achieves byte

synchronization.

The recommended preamble bit pattern is now discussed. If the standard to be implemented requires a specific

preample, use it.

In FEC mode, HDLC [1] flags (pattern 01111110) must be transmitted. The convolutional encoder ensures enough bit transitions, and the AX5043 receiver needs flags to synchronize its interleaver.

If the scrambler or manchester is enabled, send RAW bytes 00010001. The scrambler or manchester encoder ensure enough transitions to acquire the bit timing.

In 4−FSK mode, send UNENCODED bytes 00010001. This ensures that the preamble toggles between the highest and the lowest frequency. The frequent transitions ensure the bit timing is acquired as quickly as possible, and the maximum and minimum frequencies allow the deviation to be acquired.

Otherwise, use UNENCODED 01010101. This preamble ensures the maximum number of transitions for bit timing synchronization. This preamble could also be used with the scrambler enabled; the main purpose of the scrambler is however to ensure no spectral lines (tones), this would be defeated by this preamble.

If MSBFIRST in register PKTADDRCFG is set, then the preamble sequences should be reversed.

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AND9347/D

Receiver

Figure 10 shows the receiver flow chart. When the microprocessor places the chip into FULLRX mode, the AX5043 immediately powers up the synthesizer, settles it

Set PWRMODE to FULLRX

Enable TCXO if used

yes

Timeout?

Packet Received?

(FIFO not empty)

yes

Read Packet from FIFO

(registers TMGRXBOOST and TMGRXSETTLE determine the timing) and starts receiving. The reception continues until the microprocessor changes the PWRMODE register.

Set PWRMODE to WORRX

TCXO controlled by PWRAMP or

ANTSEL if used

Packet Received?

(FIFO not empty)

yes

Read Packet from FIFO

Continue

yes

Reception?

Set PWRMODE to POWERDOWN

Disable TCXO if used

Figure 10. Receiver Flow Chart

If antenna diversity is enabled, the AX5043 continuously switches between the antennas (controlled by the ANTSEL pin) to find the antenna with the better signal strength, until a valid preamble is detected. Antenna scanning is resumed after a packet is completed.

Actual packet data in the FIFO may be preceded and followed by meta-data. Meta-data may be a time stamp at the beginning of the packet, and signal strength, frequency offset and data rate offset at the end of the packet. Which meta-data is written to the FIFO is controlled by the register PKTSTOREFLAGS.

Wake-on-Radio mode allows the AX5043 to periodically poll the radio channel for a transmission while using only very little power. Figure 11 shows the wake-on-radio flow

yes

Continue

Reception?

Set PWRMODE to POWERDOWN

Disable TCXO if used

Figure 11. Wake-on-Radio Receiver Flow Chart

chart. The AX5043 periodically wakes up. The wake-up is controlled by the on-chip low-power 640 Hz/10 kHz RC oscillator and the period is programmed using the WAKEUPFREQ1 and WAKEUPFREQ0 registers.

After waking up, the AX5043 quickly settles the AGC and computes the channel RSSI. If it is below an absolute threshold (register RSSIABSTHR) and a dynamic threshold (register BGNDRSSITHR), it is switched off immediately. Otherwise, it looks for a valid preamble. If none is found within a preprogrammed time (registers TMGRXPREAMBLE1 and TMGRXPREAMBLE2), the receiver is powered down. Otherwise, it continues to receive the packet.

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AND9347/D

If a packet is successfully received, the receiver may either be shut down again, or continue to run if WORMULTIPKT is set in register PKTMISCFLAGS.

In Wake-on-Radio mode, the AX5043 is completely autonomous until a packet is received. The microprocessor may be shut down and only wake up once the FIFO is no longer empty (IRQMFIFONOTEMPTY interrupt in register IRQMASK0).

Receiver State Machine

Figure 12 shows the receiver timing diagram. The actions in the first two lines are time controlled. The arrows below indicate which register controls the timing. The actions colored in a darker shade of blue are only performed when diversity mode is enabled (DIVENA is set in register DIVERSITY). The actions in the last line are detailed in the state diagram Figure 13.

SYNTHBOOST SYNTHSETTLE IFINIT COARSEAGC AGC RSSI

TMGRXBOOST TMGRXSETTLE TMGRXOFFSACQ TMGRXCOARSEAGC TMGRXAGC TMGRXRSSI

SYNTHBOOST and SYNTHSETTLE form the two stage procedure to settle the synthesizer on the first LO frequency. During SYNTHBOOST, the synthesizer is operated at a higher loop bandwidth (register PLLLOOPBOOST), while during SYNTHSETTLE, the final settling is done at the nominal, lower noise, loop bandwidth (register PLLLOOP).

IFINIT settles the IF strip. COARSEAGC uses a fast AGC time constant to quickly settle the AGC to a value close to the correct one. This is especially important during wake-on-radio, as it is desirable to keep the receiver powered the shortest possible time to save power. AGC settles the AGC using a slower time constant. RSSI measures the received signal strength. This value is then used to determine whether the receiver should be kept running in wake-on-radio, or to select the antenna with the stronger signal in diversity mode.

Antenna #0

Antenna #1 Selected Antenna

IFINIT COARSEAGC AGC RSSI IFINIT

TMGRXOFFSACQ TMGRXCOARSEAGC TMGRXAGC TMGRXRSSI TMGRXOFFSACQ

PREAMBLE1 PREAMBLE2 PREAMBLE3 PACKET

MATCH0MATCH1 SFD detected

Figure 12. Transmitter Flow Chart

Once the receiver is initialized, PREAMBLE1, PREAMBLE2, PREAMBLE3, and PACKET coordinate the reception of packets. The receiver contains several loops that acquire and track transmission parameters the receiver needs to know in order to correctly receive a packet.

• The AGC acquires and tracks the signal strength

• The frequency tracking loop acquires and tracks the

frequency offset

• The timing and data rate tracking loop acquires and

tracks the sampling time and the data rate offset

The bandwidth of these loops is programmable. The bandwidth controls the acquisition time as well as the

Antenna

Diversity only

noisiness of the parameter estimates. In order to allow both fast acquisition to enable short preambles and low steady state noise performance to enable high receiver sensitivity, the receiver supports multiple acquisition and tracking loop parameter sets. When the receiver searches for a transmission signal, it uses wide loop bandwidths. Once it detects a preamble with sufficient probability, it switches to a lower loop bandwidth. Once a frame start is detected, it switches to an even lower loop bandwidth. Figure 13 shows the state diagram that controls which receiver parameter set is used.

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AND9347/D

Crystal

or TCXO

LPOSCREF

LPOSCKFILT LPOSCFREQ

Figure 13. Receiver State Diagram

Conditions are evaluated in priority order. The priority number is given in parentheses at the beginning of arrow labels.

In order to reduce the number of registers that need to be programmed if not all parameter sets are different, the parameter set number of Figure 13 is not directly used to address the parameter set. Instead, it indexes into register RXPARAMSETS, where the actual parameter set number is read out.

Low Power Oscillator Calibration

The low power oscillator is used to control the wake-up frequency , o r polling period, during wake-on-radio mode. In

Figure 14. Low Power Oscillator Calibration Logic

order to increase the precision of the wake-up frequency, calibration logic allows the low power oscillator to be calibrated against the crystal oscillator or TCXO.

Figure 14 shows a block diagram of the calibration logic. It works similarly to a PLL. The reference frequency from the crystal or TCXO is divided by the value of the LPOSCREF register. This signal is then compared to the actual frequency of the Low Power Oscillator. The frequency difference is then low pass filtered (LPOSCKFILT register) and used to adjust the Low Power Oscillator frequency (LPOSCFREQ register).

When enabled (LPOSCCALIBR or LPOSCCALIBF enabled in register LPOSCCONFIG), the calibration logic is only activated when the crystal oscillator or TCXO is

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enabled as well. This allows “opportunistic” calibration – the Low Power Oscillator is calibrated whenever the reference frequency is enabled.

AND9347/D

PWRAMP

or ANTSEL

GND

DAC Voltage

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TRK_AMPLITUDE + 0x8000

00000000

TRK_RFFREQUENCY

0000

TRK_FREQUENCY

00000000

TRK_FSKDEMOD

0000000000

0001

DACINPUT

0010

0011

0100

RSSI

0000 000000

SOFTDATA

0000000000

GPADC13

00000000000000

Shifter

Limiter

DACVALUE

to DAC

0110

0111

1000

1001

1100

0000

000000

Auxiliary DAC

The AX5043 contains an auxiliary DAC. It can be used to output various receiver signals, such as RSSI or Frequency Offset, or just a value under program control. The DAC signal can be output either on the PWRAMP or ANTSEL pad.

The DAC may be operated in two modes. ΣΔ mode employs a digital modulator to output a high resolution signal. Its output voltage range is ¼ VDDIO to ¾ VDDIO for a DACVALUE range from *2048 to 2047.

PWM mode outputs a pulse width modulated signal. It is only suitable for low frequency signals. Its output voltage range is 0 to VDDIO for a DACVALUE range from *2048 to 2047.

Figure 15. DAC RC Filter

A low pass filter, such as a simple R-C filter as shown in

Figure 15, must be used to obtain the analog voltage.

Figure 16. DAC Signal Scaling

Figure 16 shows the DAC Signal scaling. DACINPUT in register DACCONFIG selects the source signal. The input signals are left aligned to 24 bits and padded with zeros. A signed shifter then shifts the selected value to the right by 0 to 15 digits as selected by the lower four bits of the

value range of *2 DAC core. Note that if DACVALUE is selected as input, the register value is directly sent to the DAC, the shifter is not used. In fact, DACVALUE and DACSHIFT share the same register bits.

DACVALUE register. The signal is then limited to the DAC

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11…211

*1. This signal is then sent to the

AND9347/D

Table 22. CONTROL REGISTER MAP

Addr

Hex 7 6 5 4 3 2 1 0

Revision & Interface Probing

000 001 SCRATCH RW R 11000101 SCRATCH(7:0) Scratch Register

Operating Mode

002

Voltage Regulator

003

004 POWSTICKYSTAT R R −−−−−−−− SSSUM SSREF SSVREF SSVANA SSV

005 POWIRQMASK RW R 00000000 MPWR

Interrupt Control

006 007 IRQMASK0 RW R 00000000 IRQMASK(7:0) IRQ Mask 008 RADIOEVENTMASK1RW R −−−−−−−0 − − − − − − − RADIO

009 RADIOEVENTMASK0RW R 00000000 RADIO EVENT MASK (7:0) Radio Event

00A IRQINVERSION1 RW R −−−00000 − − − IRQINVERSION (12:8) IRQ Inversion 00B IRQINVERSION0 RW R 00000000 IRQINVERSION (7:0) IRQ Inversion 00C IRQREQUEST1 R R −−−−−−−− − − − IRQREQUEST (12:8) IRQ Request 00D IRQREQUEST0 R R −−−−−−−− IRQREQUEST (7:0) IRQ Request 00E RADIOEVENTREQ1R −−−−−−−− − − − − − − − RADIO

00F RADIOEVENTREQ0R −−−−−−−− RADIO EVENT REQ (7:0) Radio Event

Modulation & Framing

010

011 ENCODING RW R −−−00010 − − − ENC

012 FRAMING RW R −0000000 FRMRX CRCMODE (2:0) FRMMODE (2:0) FABORT Framing settings 014 CRCINIT3 RW R 11111111 CRCINIT (31:24) CRC Initialisation

015 CRCINIT2 RW R 11111111 CRCINIT (23:16) CRC Initialisation

016 CRCINIT1 RW R 11111111 CRCINIT (15:8) CRC Initialisation

017 CRCINIT0 RW R 11111111 CRCINIT (7:0) CRC Initialisation

Name Dir R Reset

REVISION R R 01010001 SILICONREV(7:0) Silicon Revision

PWRMODE RW R 011−0000 RST REFEN XOEN WDS PWRMODE(3:0) Power Mode

POWSTAT R R −−−−−−−− SSUM SREF SVREF SVANA SV

MSREF MSVREF MS VANA MSV

GOOD

IRQMASK1 RW R −−−00000 − − − IRQMASK(12:8) IRQ Mask

MODULATION RW R −−−01000 − − − RX HALF

SPEED

NOSYNC

Bit

MODEM

MODEMSSBEVANA

MODEMMSBE VANA

MODULATION(3:0) Modulation

ENC MANCH

SBE VANA

ENC SCRAM

SBEV MODEM

SSBEV MODEM

MSBEV MODEM

ENC DIFF

SVIO Power

SSVIO Power

MSVIO Power

EVENT MASK (8)

EVENT REQ(8)

ENC INV Encoder/Decoder

Description

Management Status

Management Sticky Status

Management Interrupt Mask

Radio Event Mask

Mask

Radio Event Request

Request

Settings

Data

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Table 22. CONTROL REGISTER MAP(continued)

Addr

Hex

Forward Error Correction

018

FEC RW R 00000000 SHORT

019 FECSYNC RW R 01100010 FECSYNC (7:0) Interleaver

01A FECSTATUS R R −−−−−−−− FEC INV MAXMETRIC (6:0) FEC Status

Status

01C

RADIOSTATE R − −−−−0000 − − − − RADIOSTATE (3:0) Radio Controller

01D XTALSTATUS R R −−−−−−−− − − − − − − − XTAL

Pin Configuration

PINSTATE R R −−−−−−−− − − PS PWR

020

021 PINFUNCSYSCLK RW R 0−−01000 PU

022 PINFUNCDCLK RW R 00−−−100 PU DCLK PI DCLK − − − PFDCLK (2:0) DCLK Pin

023 PINFUNCDATA RW R 10−−−111 PU DATA PI DATA − − − PFDATA (2:0) DATA Pin

024 PINFUNCIRQ RW R 00−−−011 PU IRQ PI IRQ − − − PFIRQ (2:0) IRQ Pin Function 025 PINFUNCANTSEL RW R 00−−−110 PU

026 PINFUNCPWRAMP RW R 00−−0110 PU

027 PWRAMP RW R −−−−−−−0 − − − − − − − PWRAMP PWRAMP Control

FIFO

028

FIFOSTAT R

W − FIFOCMD (5:0)

029 FIFODATA RW −−−−−−−− FIFODATA (7:0) FIFO

02A FIFOCOUNT1 R R −−−−−−−0 − − − − − − − FIFO

02B FIFOCOUNT0 R R 00000000 FIFOCOUNT (7:0) Number of Words

02C FIFOFREE1 R R −−−−−−−1 − − − − − − − FIFO

02D FIFOFREE0 R R 00000000 FIFOFREE (7:0) Number of Words

02E FIFOTHRESH1 RW R −−−−−−−0 − − − − − − − FIFO

02F FIFOTHRESH0 RW R 00000000 FIFOTHRESH (7:0) FIFO Threshold

ResetRDirName

MEM

SYSCLK

ANTSEL

PWRAMP

R 0−−−−−−− FIFO

AUTO COMMIT

RSTVI TERBI

− − PFSYSCLK (4:0) SYSCLK Pin

PI ANTSEL

PI PWRAMP

− FIFO FREE

FEC NEG FEC POS FECINPSHIFT (2:0) FEC ENA FEC (Viterbi)

AMP

− − − PFANTSEL (2:0) ANTSEL Pin

− − PFPWRAMP(3:0) PWRAMP Pin

THR

PS ANT SEL

FIFO CNT THR

Data

Bit

PS IRQ PS DATA PS DCLK PS SYS

FIFO OVER

FIFO UNDER

FIFO FULL

01234567

RUN

CLK

FIFO EMPTY

COUNT (8)

FREE(8)

THRESH (8)

Description

Configuration

Synchronisation Threshold

State

Crystal Oscillator Status

Pinstate

Function

FIFO Control

Number of Words currently in FIFO

currently in FIFO

Number of Words that can be written to FIFO

that can be written to FIFO

FIFO Threshold

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AND9347/D

Table 22. CONTROL REGISTER MAP(continued)

Addr

Hex

Synthesizer

030

PLLLOOP RW R 0−−−1001 FREQB − − − DIRECT FILT EN FLT (1:0) PLL Loop Filter

031 PLLCPI RW R 00001000 PLLCPI PLL Charge

032 PLLVCODIV RW R −000−000 − VCOI

033 PLLRANGINGA RW R 00001000 STICKY

034 FREQA3 RW R 00111001 FREQA (31:24) Synthesizer

035 FREQA2 RW R 00110100 FREQA (23:16) Synthesizer

036 FREQA1 RW R 11001100 FREQA (15:8) Synthesizer

037 FREQA0 RW R 11001101 FREQA (7:0) Synthesizer

038 PLLLOOPBOOST RW R 0−−−1011 FREQB − − − DIRECT FILT EN FLT (1:0) PLL Loop Filter

039 PLLCPIBOOST RW R 11001000 PLLCPI PLL Charge

03B PLLRANGINGB RW R 00001000 STICKY

03C FREQB3 RW R 00111001 FREQB (31:24) Synthesizer

03D FREQB2 RW R 00110100 FREQB (23:16) Synthesizer

03E FREQB1 RW R 11001100 FREQB (15:8) Synthesizer

03F FREQB0 RW R 11001101 FREQB (7:0) Synthesizer

Signal Strength

040

RSSI R R −−−−−−−− RSSI (7:0) Received Signal

041 BGNDRSSI RW R 00000000 BGNDRSSI (7:0) Background RSSI 042 DIVERSITY RW R −−−−−−00 − − − − − − ANT SEL DIV ENA Antenna Diversity

043 AGCCOUNTER RW R −−−−−−−− AGCCOUNTER (7:0) AGC Current

Receiver Tracking

045

TRKDATARATE2 R R −−−−−−−− TRKDATARATE (23:16) Datarate Tracking

046 TRKDATARATE1 R R −−−−−−−− TRKDATARATE (15:8) Datarate Tracking 047 TRKDATARATE0 R R −−−−−−−− TRKDATARATE (7:0) Datarate Tracking 048 TRKAMPL1 R R −−−−−−−− TRKAMPL (15:8) Amplitude

049 TRKAMPL0 R R −−−−−−−− TRKAMPL (7:0) Amplitude

04A TRKPHASE1 R R −−−−−−−− − − − − TRKPHASE (11:8) Phase Tracking 04B TRKPHASE0 R R −−−−−−−− TRKPHASE (7:0) Phase Tracking

ResetRDirName

MAN

PLL LOCK RNGERR RNG

LOCK

PLL LOCK RNGERR RNG

LOCK

VCO2INT VCOSEL − RFDIV REFDIV (1:0) PLL Divider

START

Bit

01234567

Description

Settings

Pump Current (Boosted)

Settings

VCORA (3:0) PLL Autoranging

Frequency

Settings (Boosted)

Pump Current

VCORB (3:0) PLL Autoranging

Frequency

Strength Indicator

Configuration

Value

Tracking

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Frequently Asked Questions

User Manual