EACA EG 3014, EG 3021, EG 3020, EG 3022 Technical Manual

EG

30

1

4

EG

EXPANSION

TECHNICAL

302

MANUAL

PREFACE

This manual

the Expander

regarded

as a

should have

Please

pleased

to correct

EG3014

reference

the

basic

do

not

is

written

knowledge

hesitate

the

mistakes

and

or

to give

the

reminder

a

inform

to

brief

a

optional

to

of digital electronics

us

and up-date

view

interface

the

experienced

about

this

of the

boards

any

errors,

manual.

theory

in

order

of

operation

that can

technical

make full

to

mistakes and

be

added

people.

and technical information

The

to it.

is expected

It

use

of this manual.

information

manual can

that the reader

out of

date.

We

1981

of

be

are

TABLE

1.

EG3014

1.1 Buffers

1.2

1.3 Floppy

1.4

1.5

1.6

CONTENTS

OF

EXPANDER PAGE

Address Decode

and

Memory

1.3.1 Controller

1.3.2

1.3.3 Address

1.3.4

1.3.5 Side Select

1 .3.6

Parallel Printer

1.4.1

1 .4.2 Card-Edge

Connectors for

1.5.1

1.5.2

Power

(RAM)

Interface

Disk

Drive

Select

Decode

Separation _

Data

1.3.4.1

1.3.4.2

Card-Edge

for Floppy Disk

Interface _ _ _

Printer

for

Pin

Pin

Supply

Status _

Parallel

Further Expansion

Assignment for
Assignment

and

_____.____..____.

Chip

Internal

External Data Separator

Pin Assignemnt

Pin

Printer

Regulators __

Logic

_

_ _ _

_

_ _ _ .

_

________________

Clock

and

__„__„___. 7

__„„_„______.

____________

_

Data

Separator

_

__

_ _ _ _ _ _. 8

__

_ — __ _. __

__„„____.

_

_. _ _ _ _ _ _ _

Interface _ — _ _ „ _ __

_

_ _ _

Assignment

Interface

50-pin

the

for the 20-pin

Connector
Connector

_'„

_ _ __

„ _

—

_ _ _ _ _ _

_ _

_

_ _ _ _ _ _.

_

_

—

_ _ _ — _

_

_ _ __ _

__

_

_.

_

__ _

_ _ .

_ _

_ „ „ .

_. 8

_.11

_.

_.12

_ .

6
6

7

7

8

9

1

.

12

12

.

13
13

14

.

15

EG3020 RS-232-C INTERFACE

2.

2.1

UART

2.1.1

2.1.2 Clock

2.2 Baud Rate

Address Decode

2.3

TTL/E

2.4

2.5 Busses

2.5.1

2.5.2

2.6 Voltage

EG3021 DOUBLE

3.

Introduction

3.1

Floppy Disk

3.2

Chip Select

3.3

3.4

16

Write Precompensation

3.5

3.6 Data

3.6.1

3.6.2 Double

4.

EG3022

4.1

introduction

4.2 Address

4.3

Data

4.4

Control/Status Lines

Vectored Interrupt

4.5

Power

4.6

MHz

S-100

__„_____„____.

Control Bits _ _ _ _ - _ _ _ _ _ _ .

Generator

A Level Shifters

I

_ _ - - - - - - - _ - - _

Pin

Assignment

Pin

Connections

Regulator

DENSITY

Controllers

Decode

Clock

Separator

Single Density

BUS

Lines _

Lines

Lines

_ _ _ _ _

__

_ _ _

__„________„.

_ _ _ _ _, - _ __ _ _

_

___

_ _ __ _ _.___.

___________ 18

for

the

RS-232-C

between

_

the

__ _ __ _ _ _ _ _ _

Bus

Expander

ADAPTER (FLOPPY

_ - _ _ _ _ _

and the RS-232-C

DISK)

_

Interface

_ _ _ _

__ _

______ _„____.

___________

Logic

Generator

_ _ _ _ __ __ _ _ _ _

Density

INTERFACE

_

Multiplexer _ _ _ _ _. _ _ .

and

_„„_„„____.

__ _ _

_

_.

_

__ _

_

_ _

_

_ __ — _ _ _ _ _ _ _ .

___

___ ______

_

_______

_ _ __ _

_ _

____„___.

___

__ __ _ _ _

____„_______ 24

_„_____

Lines __

_ _ _ _

„ _ _

_

_

_

_ __

_ _ _ _ .

_ _

_

__ _

_ _
_

. 16

_.17

.

.

. 19

-.19

20

.

20

20

.

.

23

.

24

24

.

24

24

. 25

25

.

__

16
16

16

17

18

18

20

21

21

21
21

4.7 Bus

4.7.1

4.7.2

4.7.3

Connector Pin Assignment

and

Pin Assignment for

and

the

S-100

Pin Assignment for

Board

4.7.2.1 50-pin

4.7.2.2

Pin

and

34-pin

Assignment

the

Bus

Mother

PCB
PCB

for the

______

50-pin Connector

the

Interface

the

Solder-to-board
Solder-to-board

S-100

Board.

Connectors

Board.

Bus

Connector

between the

- - - - -

-

between

the

S-100

_ _ — —

Connector

Connector

on the Mother Board

_ _

Expander

Interface

Bus

— — -

_ _ _ _

—

_ —

PAGE

.25

—

_

25

.

_

_ 26

-.26

-.27

-

_

27

.

_

COMPONENT

5.

SCHEMATICS

6.

APPENDIX

LAYOUT

—

A

DIAGRAMS

_____--_

_„_____-----•

Genie System

Connections

Pin

between

the Expander and the

Video

30

-

35

.

_

43

INTRODUCTION

The

includes

interface.

interface

The

their

Expander

Expander

32K bytes

There

and

S-100 Bus interface.

circuits of

are

more

EG3014

of

dynamic

optional

these

quickly

interfaces are

provides

useful

RAM memory, floppy

interface

and

boards

described

modify it to suit

interfaces

that can

briefly

their

to

disk

be

own

the

main

controller

added

part

by

use.

to the

part

unit

of the

and

Expander.

so that

Video Genie

interface,

They

the

and parallel

are the

users

may

System.

printer

RS-232-C

understand

It

1.

EG3014

INTRODUCTION

EXPANDER

This expander

buffers

1

memory

2)

floppy

3)

parallel printer interface

4)

connectors

5)

power

6)

These

Fig

1.1

CJ

and address decode

(RAM)

disk interface

for

supply and

functional blocks

ZJ

CQ

c

o

\n

C

Q.

X

LU

board can

further expansion

regulators

are

Address

Buffer

Data

Buffer

Control/

Status

Buffer

divided into

be

illustrated

Y//

six

parts:

1.1.

Fig

in

Address

Decode

Memory

(RAM)

Floppy

Disk

Interface

^

"7^

>

Disk

Drive

Power

Supply

Regulators

&

^

±5V

+12V

+8V

±16V

Parallel

d

Printer

Interface

Connectors

For

Expansion

_^

Parallel

Printer

RS232C

Interface

or

S-100

Bus

Interface

1.1 BUFFERS AND

The

data

are Z28,

resistance

control

Z30, Z33,

terminators

status

and

Z29 and

Z34

RAM's,

enable

generates the decoded

signals

of

ADDRESS

lines, address

Z26

buffers.

Z32

provide the memory block select signals,

serial port,

a

DECODE

lines,

Z20. In order

and

and 220 ohms)

(680

F8H or F9H,

LOGIC

control

and

read/write

and status

minimize

to

are added

signals

and of

parallel

a

lines

ringing

the

the inputs of

at

floppy

the

to

printer

are buffered by

transient on

and

the address

48K

and

32K

interface.

disk

of FDH.

port

74LS244.

buffers and

control

to

Z27

The buffers

the signal

CAS

Z31 give

and

lines,

the

of the

MEMORY

1.2

This

control

row

timing

shown

timing

and

logic

in

We may

sockets

higher

Fig

1.2 GENERATION

(a)

of

16K bytes

(RAM)

part

column

generates

1.2.

Fig

get

Z11

RFSH

dynamic

The

RAS,

16K

RAM.

of

chips

RAM

obtained

are

MUX

byte RAM's

Z11

Z18.

consists

logic.

addresses

through

of

OF RAS, MUX AND CAS

>

and

is

RAM

are

from two

CAS

from

the

chips,

4116,

this

MSB

address

16K x

multiplexers,

Z10,

from

expansion

Z18

and

multiplexer,

each

bits

1

the

and

just by

unit

the LSB.

and

Z9

and

simplified

Z1

buffers

data

250nsec

of

Z19 (74LS157).

circuit

inserting

through

RAM

Z8 are

(74LS244)

time.

access

The control

timings

and

chips

sockets

into

for

and

The

are

the
the

MREQ

>

^CAS

Fig

1.2

(b)

Timing

Diagram

RAS,

MREQ

RFSH

MUX

D

CAS

T1

\

row

T2

M1

col

Cycle

T3

/

\

memory

T4

J<

—

T1

or

R

W

Cycle H

T2

T3

A_

\

r

i

r

1.3 FLOPPY

1.3.1

1.3.2

DISK

Controller

The

derived

is

time

real

a

dividers,

of

Select

Drive

In

latch,

the

Port

37E0WR

time selecting

Any

one-shot,

INTERFACE

and

chip

floppy

from a

order to

Z42.

Z47

disk

8

occurs

clock

Z54, Z50,

select

The data

and sent to

Clock

controller

MHz crystal

every

and

Z45

drive,

a

lines

(active 'one'

drive,

a

a

the

(FDC)

oscillator

msec.

25

Z44.

required to

it is

assigned

Data

for

Bit

D0

D1

D2
D3

signal Motor

drive

turn on its

to

used

and

This

drive

is

divide-by

a

40

On

FD1771

interrupt

Hz

write

a

selection

of

about

motor.

eight

are as

sec.

2

operates

counter,

signal

follows.

Drive

(active

duration is

which

logical one to

MHz.

at

1

Z54. An

obtained

is

corresponding

the

Select Signal

DS1

DS2

DS3
DS4

'zero')

generated

This clock

interrupt

from

a

by

for

series

bit

the

of

1.3.3

Address Decode

The

address decode for

Table 1.1

Control

Signal

37E0RD

37E0WR

37ECRD

37ECWR

Transfer of

ress

1

1

1

1

low)

in

Table 1.2.

(active

signals

Table 1.2

Add

A1 A0

data

this floppy

Signal

Interrupt Logic

Drive

Disk
Disk

between

37ECRD

(RE)

Status

Track

Sector

Data

interface is assigned

disk

To

Select

Controller
Controller

Disk Controller and

the

Register

Register

Register

Register

in Table

as

Function

Interrupt

Read

Drive®-

Select

Data

Read

Write Data To

accomplished by

is

CPU

37ECWR

(WR)

Command

Register

Track

Sector

Data

Register

Register

1.1.

Status

From Disk

Disk

Register

Controller

Controller

following

the

1.3.4

Data

1.3.4.1

Separation

Internal

Data

FD1771

XTDS (pin

fed

is

into

of

soft

sectored recording format on

Practical

data recovery

external

data separation.

FDDATA respectively.

In

each

component

external

data

Separator

provides an internal

and

25)

FDDATA

FDCLOCK

(pin

experience

than

the

27 of FD1771).

tells

internal

The

case, select the

layout

diagram.

separation.

data

(pin

26).

the

us that an

data separation.

separated

jumpers J1

Normally,

separation

The

raw

READ

Note

that

diskette.

external

data

XTDS is pulled

clock and

J3

,

these jumpers

and

data

J4

pulling

by

DATA

FD1771

referring

are

has

separator

are

fed into

to

connected in the

HIGH

from

the

the

disk

the

compatibility

is

more reliable in

LOW to

FDCLOCK and

the

schematics and

signals,

drive

select

mode

of

1.3.4.2

External

The

timings of

Separator

Data

external

data

the

separator

data

separator.

can

simplified

be

in Fig 1 .3a

as

Fig

1

.3b

shows

the

a)

Circuit

9

C

13

FROM

Z47-13

Z59 1

c

Z55

LI

R

Q-

S

Fig

10

1

.3

v

READ

DATA

Z59

3>

EXTERNAL DATA

Z55

tf>

r-.

FF1

13 1

>

CK

0.1

R

2

Z60

>-

FF3

>CK

3_

SEPARATOR

11

Q3

>->

R

-»SEP

">-

Z56

SI

Q

13

DATA

i

Z59

*

10

SEP

CLOCK

Z56

S2

Q

i>

R

11

Fig

1.3

EXTERNAL

(b)

Timing

DATA

Diagram

SEPARATOR

data

address

mark

+

Sep.

Sep.

READ

DATA

Data

Clock

L1

S1

FF1

FF2

c

)

f

II

c

:

t r*

\

t

c

)

f

misi

c

;ing

clo

)

ck

[

y

r

-*

)

c

f

c )

F

\

[

u

X i-

c

i\

1

i

1

1

\

)

c

*

FF3

S2

The

(one-shot).

output

separating

is

opened

window

i \

raw

READ

Positive-going

Z47

of

the

data

with

is

opened

(pin

the

with

i

DATA which

pulses with

Z55

13).

pulses

clock

the

and

window

data

forms

clock

window

are

negative-going

width

of

a

data

window

pulses. When

closed,

and

closed.

>

t

about

Z56-5

when

pulses

200 nsec.

and

is

HIGH,

Z56-5

pass through

are

obtained

a

clock

the

is

LOW, the

window.

data

window

n

Z47

from

for

clock

Z56

pulse

width

separated

missing

falling

edge

period.

edge

of

open

the

reset

to

control

(S2) is

clock.

clock

of

At the

the

separated

clock

a

LOW

the

clock

of

period

S1

4

end

a

one-shot

ysec.

S1

is

triggered

in

Therefore,

.

of three

window.

level

and

data

with

One-shot

case of

the

missing

data.

In turn,

Fortunately,

again.

S2

windows.

output

S2

pulse

is

normally

by the falling

data

address

separation

clocks,

S2

output

a

separated

is

released

of

edge

mark,

stays

FF3

from

5 ysec

triggered

of

the

S2

in

sync

(Z60)

will

be

clock

reset,

in

width,

by

the falling

separated

is

triggered

through

will

go

reset

to LOW,

appears,

and

will

and Z56

data.

to

the

HIGH

and

work

(S1

edge

During

HIGH

missing

at the

and

this

FF3

(Z60)

normally

)

has

of the

the

by the

clock

falling

will

to

is

1.3.5

1.3.6

Side

Select

Since

double-sided

the Drive

Select

is

HIGH, the

When

Side

are

accessed.

Card-Edge

(Refer

to

Pin

pins

odd

2

4

6
8

10

12

14

16

18

20

22

24

26
28

30
32

34

the

Side Select

drive will

Select

signals. For

Select is

Pin

Assignment

the

component

Signal

GND

NC

NC

SIDE

INDEX/SECTOR

DS1

DS2

DS3

MOTOR

DIR

STEP

WRITE
WRITE

TRACK

WRITE

READ

DS4

NC

replace

Side

of

LOW, the

layout

SELECT

ON

SEL

DATA

GATE

00

PROTECT

DATA

signal

instance,

diskette

for

Floppy

is generated,

two

single-sided

jumpers

corresponding

sides

of

diagram)

drives. This

in

positions

diskette

Disk Interface

Description

odd

To

Input

corresponding

pins

of

double-sided

to FDC,

(Output from

(active

(

step

Drive

Output

Output

in

Output

LOW

Select

from

from

when

from
Output from
Output from

read

data

when

Input

to FDC,

Input

to FDC,

Input

to

FDC,

Output

from

double-sided drives can

Side

Select signal is derived

2 and 4

to DS1 and

1 through

drives

active

at

J5 are added. When

DS3 respectively

to

33

DS2

all

and

GND

fr

cirt

LOW

FDC,

and

, 2

1

FDC,

FDC,

3

active

step out

LOW

when

LOW

FDC,

active

LOW-to-HIGH

FDC,

low

going

pulses.

FDC,

write

data when

HIGH

active

LOW

active

LOW

low

going

pulses

FDC,

Drive

Select

4,

be used.

DS4

on-t^

HIGH,

LOW,

active

from

Side

are

accessed.

respectively

LOW

%

One

ZidtStlect

QZ

-vroto\

PARALLEL

1.4

This 8-bit

The serial

This

lines

from

which

strobes

Z52-13

are clocked

data

the printer sets the

PRINTER

printer port is of

printer port, SPR,

Interface consists

the

printer.

the

data

activate

to

the BUSY

into

signal BUSY.

INTERFACE

when

of

There are

into the

line, bit

the

latch, and

address

will disable this

LOW

8-bit

a

data

also two

register of

7 of status lines.

inhibits further

FDH or

latch,

one-shots

a

37E8H

parallel

(Z48 and

(Z57); one

printer, and

This

transfer

data

and is

Z49)

the

positive

enabled

printer port.

other

by

buffer

and

a

generates the

generates a

pulse is

from the CPU

decoded

the

(253)

signal DATA

generated just after

to the

signal

for

the

positive pulse

printer before

PPR.

status

STRB

at

the

1.4.1

1.4.2 Card-Edge Pin Assignment for Parallel Printer Interface

Printer Status

are assigned

The status

Bit

7

lines

as

6

5

4

(Refer

Pin

1

3 D0
5 D1

7 D2

9 D3 10

11

13
15

17
19

21 BUSY

23 OUT OF

25

27

the

component layout diagram)

to

Signal

DATA

STROBE

D4
D5 14

D6

D7

NC

PAPER

UNIT

SELECT

NC

29 NC

31

33

NC 32 NC
NC 34

below.

Status

BUSY

OUT OF

DEVICE

ALWAYS HIGH

Pin

2
4
6 GND
8

Signal

GND
GND

GND
GND

12

GND

GND

16
18

20
22 GND

24

26 NC
28 NC
30 NC

GND
GND

GND

GND

NC

(active

PAPER

SELECTED

HIGH)

1.5

CONNECTORS

on

* ocoior.

tor

Th

e

TD

HbZ32C

re

if

interface

FOR

tW

connectors

°

5(>Pm

FURTHER

connector

board.

The

EXPANSION

Provided

mav

positions

on

the

be for

of

expander

S-100 bus

the

connectors

board;

interface

refer

one

to

has

board

the

component

50 pins (P2)

and the

20-pin

and

layout

the

other

connector

diagram

1.5.1

20

21

22

23

24

25

26

27

28.

29

30

31

32
33

34

35
36

37

38 PWAIT

Pin

Assignment for

Pin

1

2

3 -16V

4

5
6

7

8 INTA

9 BD6

10

11

12
13
14

15

16

17

18

19

SIGNAL

+16V

CLOCK

MEMDIS

+8V

FX

D4

BD5

BD0

BD7

BD2

BD1

BA2

BD3

BA0

BA1

BA15
BA14
BA4

BA11

BA6 H

BA5

BA12

BA7

BA9

BA10

BA8

BA13

BA3

PHLDA

PINT

HALT

PHANTOM

IORQ

the

50-pin

ACTIVE

Connector

LEVEL

L

L

L

H

H

H

H

H

H

H

H

H
H
H
H
H
H

H

L

L
L

L

L

L

DESCRIPTION

SEMI-REGULATED

MHz,

2

50% DUTY

SEMI-REGULATED

HIGHEST

32K

MEMORY

DISABLE

SEMI-REGULATED

RESERVED

PORT

DATA BIT 4

DATA IN

DATA BIT
DATA BIT

ENABLE

6
5

DATA BIT
DATA
DATA

BIT

BIT

7

2

DATA BIT 1

ADDRESS

DATA

ADDRESS

BIT

LINE

3

LINE0

ADDRESS LINE
ADDRESS

LINE

ADDRESS LINE 14

ADDRESS

ADDRESS

ADDRESS LINE

ADDRESS

LINE 4

LINE

LINE

6
5

ADDRESS LINE
ADDRESS

ADDRESS

ADDRESS

ADDRESS

LINE 7

LINE

LINE
LINE

9

8

ADDRESS LINE

MASTER

ADDRESS

PROCESSOR

INTERRUPT

PROCESSOR

MEMORY

BOOT-STRAPPING

I/O

PROCESSOR

SIGNAL

CLOCK,

LINE

DISABLE

REQUEST

3

HOLD

REQUEST

HALT

CYCLE

WAIT

CYCLE

ADDRESS

2

1

15

11

12

10

13

1.8

MHz

ACKNOWLEDGE

ACKNOWLEDGE

FOR

CONTROL

13

PIN

SIGNAL

ACT IVE

LEVEL

DESCRIPTION

39

40

41

42

43

44 RESET

45

46
47
48

49

50

1.5.2 Pin Assignment for

PIN

1

2

3

4

5

6 BD0

7

8 BD2
9 BWR

10

11

12
13

14

15

16

17

18

19

20

WR

PHOLD

CCDBS/STATDBS

DODBS/ADDBS

NMI

M1

RFSH

MREQ

RD

GND
GND

SIGNAL

BD5

BD4
BD7

BD6

BD1

BD3

BAO
BRD

SRESET

8MHz<2

SP*

-16V

PPR

+

12V

+5V

SPR

GND

the

20-pin

Connector

ACTIVE

L
L

L

L

L
L
L
L
L

L

LEVEL

L

H

H

L

PROCESSOR
PROCESSOR

SIGNAL

CONTROL

SIGNALS

DISABLE

DATA

LINE

OUTPUTS

DISABLE

NON-MASKABLE

RESET

OP-CODE FETCH

REFRESH

-

MEMORY

CONTROL

CYCLE

REQUEST

PROCESSOR

DESCRIPTION

DATA BIT
DATA

DATA

DATA BIT

DATA BIT

BIT

BIT 7

5

4

6

1

DATA BIT
DATA BIT
DATA

PROCESSOR

BIT

3

2

WRITE

ADDRESS LINE0

PROCESSOR

SYSTEM

MHz,

8

SERIAL

RESET

50%

PORT

READ

DUTY

SEMI-REGULATED

PARALLEL

PRINTER

SELECT

REGULATED
REGULATED

PARALLEL

PRINTER

GROUND

WRITE

HOLD

AND

INTERRUPT

SIGNAL

CYCLE

READ

CYCLE

SELECT

CYCLE

CONTROL

AND STATUS

ADDRESS

CYCLE

CYCLE

CYCLE

CYCLE

PORT

DISABLE

14

POWER SUPPLY AND

1.6

The power supply
The

specifications for

Voltage

+8V

+16V

-16V

There

(Z61

are

)

used

zener

diode

REGULATORS

provides

these

No

Load

min.

10.5V 11.5V 8V 9V F.L. +8V@1.2A

20V 24V

20V 24V 15V 18V F.L.

are

three voltage regulators

to supply +5V

regulates -16V

to obtain

three

voltages

Voltage

max.

+12V

and

semi-regulated output voltages: +8V,

are

follows:

as

Full

min. max.

15V

the expander

on

respectively.

-5V supply

Voltage

Load

18V

board.

simple regulator with transistor

A

for

the RAM's and

Remark

F.L.

IC regulators

FD1771.

+16V and

+16V@1

—16V.

50mA

-16V@100mA

(Z62)

7805

and

03 and

7812

5.6V

2. EG3020

This

RS-232-C Interface is an optional board

EG3014

2.1

received

be determined

switches,

expander.

1. UART

2. Baud rate generator

3. Address decode

Level

4.

5.

Busses

Voltage

6.

This

shifters

regulator

UART

The

UART chip

lines

data

by properly

-

SI

S5

of DP1.

RS-232 INTERFACE

board

used

output

consists of

(-12V)

is TR1863

the

to

CPU and

setting the

six parts:

or

AY-3-1014A which

lines

8 data

control

bits. This can

be plugged into the

to

needs

input

to

the

UART.

be done

single

by

20-pin connector (P1)

+5V

supply.

The

serial

data format

turning

ON

or OFF

It has

the

of

8

can

dip

2.1.1

Control Bits

(ON

2.1.1.1

2.1.1.2

2.1.1.3

2.1.1.4

2.1.2 Clock

desired

=

The

'0'

baud

OFF

and

Parity

No

S1:

ogic

Number of stop

S2:

logic

~W

Number of

S3:

Odd/Even

S5:

transmitter

rate.

NB2

logic

'1')

(NP)

1

Bits

1

1

Bits/Character

S4

1

1

Parity

Select

1

and

the

receiver

parity

parity

with

bit

parity

no

(TSB)

bit

stop

1

2

if

Vi

(NB2,

5

bits/character

NB1)

1

NB1

1

1 8

t(EPS)

pairty

odd

even

use

the

same

bit

added

is

Bits/Character

5
6

7

clock

whose frequency

selected.

is 16

times the

ia

BAUD

2.2

19200

programmed

2.3 ADDRESS DECODE

addresses

is the signal

Table

RATE

The

baud

baud.

to

The

address decode

F8 and/or

fed

Address Decode

2.1

GENERATOR

rate

They

be

divide-by

back to

PORT

SERIAL

SERIAL OUTPUT

SERIAL PRINTER

The mode

INPUT

operation can

of

MODE

Printer OFF

Serial

Communication

The

bit assignment for

Table 2.2

STATUS PORTS

DATA

BIT

D0

D1

D2

D3

D4

D5

D6

D7

OUT PORT F8H

Request-to-send

Terminal

Data

Ready

UART reset

=

1

true

unused

unused

unused

unused
unused

is

obtained

can

F9.

be

selected

1

accomplished

is

Table 2.1.

See

expander

the

by

1 and

dividing

by

divide-by

board to

ADDRESS

F8H DATA
F9H STATUS

FDH STATUS

chosen

be

as

DP1

S6

ON

status

ports is

illustrated

COMMUNICATION

IN PORT F9H

Data

=

1

Overrun Error

=

1

Framing

=

1

Parity

=

1

Carrier Detect

Data Set Ready

Clear-to-send

Transmitting

Buffer Empty

=

flipping

by

If

S7

INPUT TO

below.

SZ

ON

OFF

Available

true

true

Error

true

Error

true

true

the

MHz

8

the

13

respectively.

Z1

(74LS138).

DP1

of

disable the

S8

OFF

ON

in

Table

clock,

switches

is ON,

parallel printer

and

has

of DP2.

SP*

serial printer mode

a

is

Z10and

serial

a

interface.

CPU OUTPUT TO

STATUS

DATA
DATA

2.2

SERIAL PRINTER

IN

PORT

unused

unused

unused

unused

Carrier Detect

Data Set

Always LOW

Transmitting

Buffer Empty

0=

FDH

Ready

true

eight

choices

Z11

port

is

from

(74LS161) are

enable signal with

selected,

INTERFACE

and

110

to

SPR

17

TTL/EIA

2.4

equipment. El

Logic 'V

than

receiver 1489

2.5

BUSSES

2.5.1

LEVEL SHIFTERS

Drivers/level shifters

A RS232-C

or

+3V.

Driver

The

PIN

1

2
3

4 RTS

5

6

7

8

20 DTR

means

OFF

(Z2)

1488

is

(Z3)

pin assignment for

used

SIGNAL

PGND

TXD

RXD

CTS

DSR

SGND Signal

CD Carrier

required

are

standard specifies that

signal voltage

with ±Vcc

for signals inputs

the

to

less

±12V

of

RS-232-C Bus

DESCRIPTION

Protective

Transmit

Receive

Request-to-send

'ON'

'OFF'

Clear-to-send

'ON'

'OFF'

Data

'ON'

'OFF'

'ON'

'OFF'

Data

'ON'

'OFF'

Data

—

peripheral

—

—

peripheral

—

Set

—

peripheral

—

Ground

Detect

—

peripheral

—

Terminal

—

peripheral

channel.

—

interface this RS232-C

voltage

signal

—

than

3V,

is

used for

from

the RS-232-C bus to

is

logic

and

signals output to

as

follows:

Ground

Data

(OUT)

(IN)

(OUT)

to

transmit

peripheral

no

data should

Ready

handshaking

no

carrier

or

the signal

remove

to receive

can

receive

handshaking

not

is

receiving

is

received

is

Ready

(OUT)

should

connection

(|[\|)

be transferred.

(IN)

ready

(IN)

too

bad for

connected

be

to

interface

levels

'0'

data

(or

data.

should

or ON

the

non-transmit)

completed

carrier

a

data

the

channel

with

have threshold of

communication

data

±3V.

means signal voltage greater

the

RS-232-C

interface board.

recognition

the

to

communication

bus. Line

18

2.5.2

connections

Pin

_PJN

1

2
3
4
5
6

7

8

9

10

11

12
13

14

15

16

17

18
19

20

between

NAL

SIG

BD5

BD4

BD7

BD6

BD1

BD0

BD3

BD2

BWR

BA0

BRD

SRESET

8MHz0

SP*

-16V

PPR

+12V

+5V

SPR

GND

Expander

the

DFSCRIPTION

DATA

DATA

DATA

DATA

DATA

DATA

DATA
DATA

PROCESSOR

ADDRESS

PROCESSOR

SYSTEM

MHz,

8

SERIAL

SEMI-REGULATED

PARALLEL

REGULATED
REGULATED

PARALLEL

GROUND

and

BIT

BIT
BIT

BIT 6
BIT

BIT

BIT

BIT

RESET

50%

PORT

RS-232-C

this

5

4

7

1

3

2

WRITE

LINE®

READ

DUTY

SELECT

PRINTER

PRINTER

CYCLE

PORT

DISABLE

Interface:

SELECT

2.6

VOLTAGE

REGULATOR

+5V and +12V

shifter 1488.

level

—

from the semi-regulated

12V

have been

simple

a

So,

regulated

regulator

—16V.

on the

with Q1

expander

(9012)

board.

and a

-12V

13V

supply

zener diode

required

is

used

is

to

the

for

supply

3.

3.1

EG3021

INTRODUCTION

This

storage.

EG3014.

expansion

This

multiplexer,

3.2

FLOPPY

The

density

pin-out

precompensation

optional

It

is

Jumpers

board.

adapter

a

16

DISK

two

(FM)

of

FD1771

DOUBLE

board

to

be plugged

at J1-1

board

MHz

CONTROLLERS

chips

storage

outputs

crystal

used

and

is

similar

consists

facilitates

and

are FD1771

the

ie.

DENSITY

onto

the

J4

should

of

oscillator,

FD1791

to

that

EARLY

both

two

of

and

single

40-pin

be

write

and

controls

IC

removed,

floppy

precompensation

FD1791.

FD1791.

LATE,

ADAPTER (FLOPPY DISK)

density

disk

the

and

and

socket

and

controller

The

operation

Some

does

double

of Z41

jumper

at

chips,

logic,

FD1771

of

double

exceptions

not

require

density

(1771)

J1-2

chip

and

controls

are

-5V

formats

of the

should

select

data

density

that

supply

of floppy

expansion

be

connected

decode

separator.

the

operation

(MFM)

FD1791

storage

has

on

logic

of

two

disk

board,

the

and

single

The

write

CHIP

3.3

the

division

signal,

below.

SELECT

Z11,

37ECWR

This

chip

BD

Z12,

of

DECODE

Z9

Z4

when

select

®

and Z6

(74LS161)

BD3

is

®

1

The

signals,

controlled

by the

STEP,

chip

select

LOGIC

also

DIRC,

form

of

through

the

selection

WD

signal

AND

the

decode

the

data

BD7

and

mentioned

MULTIPLEXER

logic

to

select

separator.

are

logic

of

either

Operation

single

double

WG

of

above.

The

T,

single

density

density

FD1771

and

either

selection

A0

density

and

FD1791

and

FD1771

is

enabled

A1

are

or

double

are

or

FD1791

at

the

'&

logic

density,

multiplexed

and

rising

and

by Z8

to

edge

is

assigned

control

of

a

which

the

as

is

3.4

MHz CLOCK

16

GENERATOR

The clock generator is composed of

required

by

the

separation and

data

the write

MHz crystal and

a 16

precompensation.

three

logic

inverters.

This

clock

is

WRITE

3.5

caused by

tracks.

direction.

WRITE

Z7 (74LS153).

DATA

3.6

3.6.1

3.1

Fig

(FM)

RAW

READ

PRECOMPENSATION

The write

The

DATA

The

precompensation

particular

some

shift is

bit

WRITE DATA

The

which are

Z7

of

is

circuit

SEPARATOR

data

Counter

PULSE

type

Single

shaping

enabled and

Density

The

(74LS161).

circuit

the

pulse

data

shaping

SHAPING

Z5-11

DATA

data

compensated by

which

expected

precompensation

write

controlled

separator

window

by

and

The raw READ

formed

Z4

5

circuit can be

READ

OF

becomes

pin

CDC

aimed

is

patterns,

are

be

to

signals,

the

employed

is

clock

DATA

Z5 and

by

DATA

eliminating

at

the

and

shifting

late

the

expected

delibrately

are

contains

EARLY

for

window

before entering

Z6 (74LS74).

'0'.

logic

illustrated

the

tracks

inner

bits

to

be

to

delay

a

and LATE

single

both

controlled by

are

Z4

Then

the

by

predictable

have

written

be

are

early

shifted

circuit,

density

window gating

the

Assume

divide-by

a

is

following

8

shift.

bit

greater bit

diskette

the

on

delibrately

early.

Z13 (74LS74),

Z1

from

timing diagram

usee

(FD1791).

double

and

the counter

single density

that

counter.

8

The

bit

shift than

shifted

and a

density

output,

passes

The

in Fig 3.1

C

may

shift

the

the opposite

in

Also

late.

multiplexer

operations.

pin

11

through a

operation

operation of

be

outer

the

of Z3

pulse

is

Q

Q

Z5-8

Z5-6

RIPPLE

is

Z4-15

equal

Z6-6

the duration

to

CARRY

-

READ

DATA

Note:

Tw

clock pulses

of 8

of

the

16

62.5

MHz

nsec

clock,

and

is

about

500

nsec.

21

During single

whenever

state

output

in Fig.

of

3.2.

Z4

density operation,

Z4

becomes

finished

has

active HIGH.

Z4

divide-by eight counting cycle,

a

is a

divide-by

The window

eight counter.

generated

Z3

counts up by

the

and

Z3-1

at

1

can

RIPPLE

illustrated

be

one

CARRY

below

Fig

Q

READ

DATA

WINDOW

B

Qa

3.2

DATA

"

Z5

6

Z3-9

26-6

Z3-II

Z3-II

Z3-I2

Z3-I3

Z3-I4

SEPARATION

COUNT

UP

-

SINGLE

DENSITY (FM)

8yusec

pulse

Whenever the

count

will

forced

phase-locked

are

Separated

FD1771

up

continue to

to

respectively.

clock

from

and

data

preset

the

count up

synchronous

separated

and

22

of a

state,

from

with the

bit

0100

the

clock

cell is

state,

READ

are

encountered,

(binary).

If

1 100.

DATA.

fed to

the

Z3-9

data

a

In

this way,

inputs

becomes

is

pulse

the

FDDATA

LOW-going

encountered,

counters

and

Z3 and

FDCLOCK

and

Z3

Z3

is

Z4

of

3.6.2

Double

During

single

READ

FD1791

CLOCK.

window

active

CLOCK

The

Density

density

DATA

Hence,

required

LOW

input

timing

double

operation

is in

requires

READ

to

during

of

FD1791.

diagram

density

except

MFM

format.

two

DATA is directly

be generated

read

operation

of

generating

operation,

that

Z4

is

external

by

so

the

generation

the

counting

programmed

signals for

applied

the

counters.

that

the

the

window

of

frequency

to become

data recovery,

pin

to

27

VFOE

window

is

shown

signal

data window

Z3

of

is

a divide-by

RAW

FD1

of

(pin

in

can

Fig.

791.

33 of

be

3.3.

is similar

doubled,

4 counter.

READ

READ

FD1791)

applied

that

to

and that

and

the

READ

CLOCK is the

is

normally

to the

READ

in

Fig

3.3

BIT

CELLS

Q Z5-6

READ

DATA

Z6-6

WINDOW

Z3-11

Z3-11

Qd

Z3-12

Qc

Z3-13

O-A

Z3-14

COUNT UP

DATA

SEPARATION

1

1

t

A

-

DOUBLE

'

1

i

|

I

6

ysec

DENSITY

D D

U«-

4

l

(MFM)

(isec-»

1 bit cell

psec

[<-4

1

D

usee

8

i

1

,

I 1

|0

I

I

1

A

Note:

edge

data bit

pulses is

for

is

A

Recall

of current

at

8

maximum

a

the

phase

MFM

that

bit cell if

the

current

psec, that

period of

correction point

format follows

there

cell.

bit

is, the counters may

psec.

8

of

the rule

no

is

data

Therefore, the

the

counters,

bit

count up

Z3

and Z4.

in

which

the preceding bit cell,

at

maximum

clock bit

a

time interval

asynchronously

is

present at

and

between

with

the

if

there

the leading

is

two data

READ

also

DATA

no

23

4.

4.1

4.2

EG3022

INTRODUCTION

plugged

board

ADDRESS

There

and

680 ohms

This

S-100 Bus

into the 50-pin

of

two 100-pin

LINES

are

on

S-100

Interface

connectors

address

16

the

mother

an

is

connector

for

lines

from

board.

BUS

option

(P2)

S-100 bus

A0 to

INTERFACE

to be

added

on the expander

standard

A15.

They

the

to

boards to

are

expander,

board. This

be added.

terminated

EG3014.

interface

by

resistor

is

It

designed

contains

arrays,

a

220

to be

mother

ohms

4.3

DATA

LINES

The

These

lines

4.4

CONTROL/STATUS

The

combinational

(74LS244)

The

will

disable

Remark:

Port

address

added

to the

eight

data lines

are

buffered

control/status

logic

and

are

terminated

signal,

FX*

the

DATA

from

expander,

F8

by Z8

LINES

lines

gates,

is

active

IN

buffer

FF

to

EG3014.

from

Z5, Z10

are

the

and Z9

of

S-100

by

resistor

LOW

(Z8

reserved

expander

(74LS244).

bus

and Z12.

arrays

when

Z9)

and

and

any

are

are

Most

which

port

of

the

cannot

split

into

generated

of

are

address

S-100 Bus.

be

8

DATA

from

these

on

the

from

used in

the

lines

mother

F8

S-100

IN

lines

expander

are

to

BUS

and

buffered

board.

FF

are

boards

8

DATA

signals

Z11

by

selected

which

OUT

lines

by simple

and

Z13

This

signal

are

to

be

4.5

4.6

4.7

encoded

Z3

the

The

BUS

i)

ii)

iii)

VECTORED

There

into

interrupt

POWER

interface

TTL

vector

D7

-

will

15

vectored

interrupt

LINES

Semi-regulated

board

logic

AND

CONNECTOR

There

between

between
between

INTERRUPT

are

eight

a

3-bit

is:

D6

1

IC's

are

1

send

out

interrupt

acknowledge

contains

of

the

connections

3

the

expander

the

S-100 Bus

the

mother

LINES

interrupt

vector

D5

V2

an

interrupt

lines

is

signal,

+8V,

+16V

a"

S-100 Bus

PIN

and

board

lines,

(V2,

VI

and

D4

V1

request

activated

SINTA

and

-16V

voltage

regulator,

interface

ASSIGNMENT

from

the

expander

the

S-100 Bus

interface

and

board

the

and

VI0

V0)

D3

V0

signal

by pulling

when

dc

Z1

board.

interface

and

S-100 Bus.

has

by

a

D2

1

to the

that

active

supply

(7805).

the

to

the

the

priority

D1

1

CPU

line

will

lines

S-100

board,

mother

highest

encoder

through

to a

LOW

gate the

are

Z1

regulates

Bus:

board,

priority.

D0

1

level.

interrupt

required

74148

the

line

in

+8V

These

interrupt

The

(73).

PINT

when

vector

into

S-100 Bus.

supply

format

any

the

TheS-100

into

+5V

lines

data

of the

one

bus

for

are

of

Bus

the

4.7.1

Pin

Assignment

Board

(Refer

PIN

1

3

5

7

9

11

13
15

17

19

to

the

component

SIGNAI

+

16V

-16V

+8V

BD4

BD6

BDO

BD2

BA2

BA0

BA15

for

the

50-pin

layout

Connector

diagram)

PIN

2

4
6

8

10

12

14

16

18

20

between

the

Expander

SIGNAI

2MHzCLOC

MEMDIS

FX*

INTA

BD5

BD7

BD1

BD3

BA1

BAH

and

the

S-100

Bus

Interface

25

PIN

SIGNAL

PIN

SIGNAL

21

23
25

27

29

31

33
35

37

39

41

43

45

47

49

4.7.2

BA4 22

BA6 24

BA12 26

BA9

BA8

PHI

(1.78

PHLDA

HALT

MHz) 32

28 BA10

30

34 PINT]
36 PHANTOM

IORQ 38 PWAIT

WR

CCDBS/STATDBS

NMI

M1

MREQ

40

42
44
46
48

GND 50

the Connectors

Assignment

Pin

Mother

(Refertothe

4.7.2.1

PIN

10

11

12

13
14

15

16
17

18

19

20

21

22

23
24
25

Note:

Board

1

2
3
4

5

6

7

8

9

description

50-pin

for

component

Solder-to-board

PCB

SIGNAL

VM

GND

+16V

+5V

VI2

VI©

-16V

+8V

VI6

VI5
VI4
VI3

MREQ

NC

NMI

VI7

CDSB/SDSB

MWRT

CDSB/SDSB

PHANTOM

REFSH

GND
GND

ADSB/DOSH

INT

these

of

layout

signals

diagram)

refers to

BA11

BA5

BA7

BA13

BA3

PHOLD

DODBS/ADDBS

RESET

RFSH

RD

GND

between the

Connector

PIN
26

27

28

29

30

31

32

33

34
35

36
37
38

39

40

41

42

43
44

45

46

47

48

49

50

Section

S-100

SIGNAL

NC

ADSB/

HOLD

NC

PHI

(1.78

PHLDA

PWR

NC

RESET

PDBIN

A5
NC

NC

A0

A4

A1

D01

A3

A15

A12

A9

A2
A6
A7
A8

4.7.3

Bus

DOSB

MHz)

Interface

Board and the

i.1.2.2

',

'>

",-

r

7,

Cx.

-

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U

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J

*.

j

1-**

1.5

16

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^

2
3

4

5

-6

7

S

9

TO

n

12

13

14

15

16

17

IB

19

20

34-pin

PCS

Solder-to-board

SIGNAL

A10

A14

DO0

A13

D05 22

D02 23

004

;

An

012

007

006 28

003

0J5 30
013
014 32
016

017

these signals

tS&scriiption

»"&e

of

for

the

component

S-100

layout

SIGNAL

-sSV

T6V

3C

WO

Vlit

VI2

W3

W4

VIS
VIS

W

SMI

1C

NC

N£

MC

TC

SDSB/CDSB

SOSB/CDSB

ewD

Connector

PIN SIGNAL

18

19

20 NC

21 NC

24

25 DI1

26

27

29

31

33

34

refers

to

Bus Connector

diagram)

ACTIVE

LEVEL

LO/C >

LO/C

LO/C

LO/C

LO/C
LO/C
LO/C

LO/C

LO/C

LO/C

)

NC
NC

NC

DI0

SOUT

SM1

SMEMR

SINTA

SINP

'

SWO

POC

MHz

2

CLOCK

SHLTA

GND

Section 4.7.3

on

the

Mother

DESCRIPTION

semi-regulated,
semi-regulated,

vectored interrupt

Non-maskable interrupt

Status

signals

Board

max
max

line

and control signals disable

2A

500mA

—

line

7

27

PIN

SIGNAL

ACTIVE

LEVEL

DESCRIPTION

21

22

23

24
25

26

27

28
29

30

31

32
33
34

35
36

37

38

39

40

41

42
43

44

45
46

47

48

49

50

51

52

53

54

55
56

57

58

59

60

61

62
63

64

65
66

67

68

69

70

71

72

REFSH

ADSB/DOSB
ADSB/DOSB

NC

PHLDA

NC
NC

A5

A4
A3

A15 H
A12

A9

D01

DO0

A10

D04

D05

D06

DI2

DI3

DI7

SMI H

SOUT

SINP

SMEMR

SHLTA H

CLOCK

GND

+8V

-16V

GND

NC

NC
NC
NC
NC
NC
NC

NC
NC

NC

NC

MREQ

NC

PHANTOM

MWRT

NC

GND

NC

NC

L

LO/C

H

H
H

H

H

H

H

H

H

LO/C

H

Dynamic Ram

Address lines and data

Master

Processor HOLD acknowledge

Address

Address line 4

Address
Address
Address line
Address

Data out bit 1
Data out

Address

Data
Data
Data out bit
Data
Data
Data in

Op-code

I/O out control signal
I/O in control signal

clock,

out

out

in

in

bit
bit
bit

Memory

Process

2 MHz,

Semi

halt

50% duty

-regulated,

Memory

Phantom

Memory write

refreshing signal

MHz

1.7

line

5

line

3

line

15
12

line

9

bit

line

10

4

bit

bit

5
6

2
3

7

fetch

cycle

read cycle

acknowledge

cycle

max

request cycle

enable for

control signal

output

100mA

bootstrapping

disable

28

PIN

73

74
75

76

77

78

79

80

81

82

83
84
85

86

87

88

89

90

91

92
93
94
95

96

97

98

99

100

SIGNAL

INT

HOLD

RESET

NC

PWR

PDBIN

A0

A1

A2

A6
A7

A8

A13

A14

A11

D02

D03

D07

DI4
DI5

DI6

DI1

DI0

SINTA

SWO

NC

POC

GND

ACTIVE

LEVEL

LO/C
LO/C
LO/C

L

H

H

H

H

H

H
H
H
H
H

H

H
H

H

H

H
H

H
H

DESCRIPTION

Primary

Bus

Reset

Processor

Processor

Address line

Address line
Address

Address line

Address
Address line
Address line
Address

Address

Data

Data

Data
Data
Data in
Data in

Data

Data

Interrupt

Processor

Power

interrupt

hold

control

control

write

read

line

line

line
line

out

bit

out bit
out

bit

in

bit

bit
bit

in

bit

in

bit

acknowledge

write

on

clear

4

5
6

3

7

1

signal

control

1

2

6

7

8

13
14

11

2

cycle

signal

request

signal

control

signal

signal

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42

APPENDIX

Connections

Pin

PIN

1

3
5

7

9

11

13

15

17

19

21

23

25

27
29

31

33

35
37
39

41

43

45

47

49

between the

SIGNAL

GND

A7

A5

A1

A2

D5

NC

DO

D7

+5V

A15

A14

NC

A13

A12

PINT

NC

PHANTOM

PWAIT

PHOLD

RD

MREQ

M1

RFSH

GND

Expander

and

the

PIN.

2

4

6
8

10

12

14

16

18

20

22

24
26

28
30
32
34
36

38
40

42

44

46

48

50

Video

System.

Genie

SIGNAL

GND

A6

A4

A3

AO

D2

D1

D3

D6

D4

A8

-

A9

A10

A11

PHI

NC

PHLDAorBA

HALT

IORQ

WR

CCDBS/STADBS

DODBS/ADDBS

RESET

NMI

GND

Note:

For

the

pin

positions,

refer

to

the

component

layout

diagram.

43

EACA INTERNATIONAL

1

3 Chong Yip Street

Eaca

Industrial

Kwun Tong,

54035

Telex:

:

Cable

"ECHUNG"

3-

Tels :

Building

Kowloon, HONG

ECHK HX

896323 (8

KONG

H.K.

Lines)

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1981