AT84AS003-EB Evaluation Board
..............................................................................................
User Guide
Table of Contents
Section 1
Introduction ........................................................................................... 1-1
1.1 Scope........................................................................................................1-1
1.2 Description ................................................................................................1-1
Section 2
Hardware Description ........................................................................... 2-1
2.1 Board Structure .........................................................................................2-1
2.2 Analog Inputs/Clock Inputs .......................................................................2-2
2.3 Digital Outputs ..........................................................................................2-3
Section 3
Operating Characteristics ..................................................................... 3-1
3.1 Introduction ...............................................................................................3-1
3.2 Operating Procedure.................................................................................3-1
Section 4
Application Information .........................................................................4-1
4.1 Introduction ...............................................................................................4-1
4.2 Analog Inputs ............................................................................................4-1
4.3 Clock Inputs ..............................................................................................4-1
4.4 Digital Outputs ..........................................................................................4-1
4.5 ADC Functions ..........................................................................................4-2
4.6 DMUX Function.........................................................................................4-4
4.7 Diode for Die Junction Temperature Monitoring .......................................4-7
4.8 Test Bench Description ...........................................................................4-10
Section 5
Package Information............................................................................. 5-1
5.1 Thermal Characteristics ............................................................................5-1
Section 6
Ordering Information............................................................................. 6-1
Section 7
Appendix............................................................................................... 7-1
7.1 AT84AS003-EB Electrical Schematics .....................................................7-1
AT84AS003-EB Evaluation Board User Guide i
0905C–BDC–09/07
ii AT84AS003-EB Evaluation Board User Guide
0905C–BDC–09/07
Section 1
Introduction
1.1 Scope
1.2 Description
The AT84AS003-EB Evaluation Kit is designed to facilitate the evaluation and characterization of the AT84AS003 10-bit 1.5 Gsps ADC with 1:2/4 DMUX up to its 3 GHz full
power input bandwidth and up to 1.5 Gsps.
The AT84AS003-EB Evaluation Kit includes:
The 10-bit 1.5 Gsps ADC with 1:2/4 DMUX Evaluation board including the
AT84AS003 device soldered and a heat sink screwed on the board
10 SMA caps for CLK, CLKN, VIN, VINN, DAI, DAIN, DAO, DAON, DRRB and
AsyncRST signals
12 jumpers for ADC and DMUX function settings (SDAEN, B/GB, PGEB, RS, BIST,
CLKTYPE, DRTYPE, SLEEP, STAGG, DAEN)
The user guide uses the AT84AS003-EB Evaluation Kit as an evaluation and demonstration platform and provides guidelines for its proper use.
The AT83AS003-EB evaluation board is very straightforward as it only implements the
AT84AS003 10-bit 1.5 Gsps ADC/DMUX device, SMA connectors for the sampling
clock, analog inputs and reset inputs accesses and 2.54 mm pitch connectors compatible with high-speed acquisition system probes.
To achieve optimal performance, the AT84AS003-EB evaluation board was designed in
a 8-metal-layer board with RO4003 200 µm and FR4 HTG epoxy dielectric materials.
The board implements the following devices:
The 10-bit 1.5 Gsps ADC with 1:2/4 DMUX evaluation board with the AT84AS003
ADC soldered and a heat sink screwed on the board
10 SMA caps for CLK, CLKN, VIN, VINN, DAI, DAIN, DAO, DAON, DRRB and
AsyncRST signals
12 jumpers for ADC and DMUX function settings (SDAEN, B/GB, PGEB, RS, BIST,
CLKTYPE, DRTYPE, SLEEP, STAGG, DAEN)
2.54 mm pitch connectors for the digital outputs, compatible with high speed
acquisition system probes
Banana jacks for the power supply accesses and the die junction temperature
monitoring functions (2 mm)
AT84AS0003-EB Evaluation Kit User Guide 1-1
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Introduction
Potentiometers for the ADC and DMUX functions
The board is comprised of 8 metal layers for signal traces, ground and power supply layers, and 7 dielectric layers featuring low insertion loss and enhanced thermal
characteristics for operation in the high frequency domain.
The board dimensions are 220 mm × 240 mm.
The board comes fully assembled and tested, with the AT84AS003 installed and with a
heat sink.
Figure 1-1. Simplified Schematics of the AT84AS003-EB Evaluation Board
VIN
3.3V
DMUX functions
DDRB
CLKN
CLK
-5V
GND
VINN
DAO/DAON
AT84AS003
DAI/DAIN
Port D
Port C
DR
G
N
D
DACTRL
CLKDACTRL
GA
SDAEN
G
V
N
E
D
E
PIN 1
ADC functions
V
M
N
U
D
G
I
N
D
S
G
V
N
C
D
C
A
G
V
C
C
D
V
N
+
D
ASYNCRST
D
Diode
As shown in Figure 1-1, different power supplies are required:
V
= -5V analog negative power supply
EE
V
V
V
V
= -2.2V digital negative power supply
MINUSD
= 3.3V analog positive power supply
CCA
= 3.3V digital positive power supply
CCD
= 2.5V digital output power supply
PLUSD
3.3V and -5V power supplies for the board functions
Port B
Port A
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Section 2
Hardware Description
2.1 Board Structure
In order to achieve optimum full-speed operation of the AT84AS003 10-bit 1.5 Gsps
ADC with 1:2/4 DMUX, a multi-layer board structure was retained for the evaluation
board. Eight copper layers are used, respectively dedicated to the signal traces, ground
planes, power supply planes and DC signals traces.
The board is made in RO4003 200 µm and FR4 HTG epoxy dielectric materials.
The following table gives a detailed description of the board's structure.
Table 2-1. Board Layer Thickness Profile
Layer Characteristics
Copper thickness = 40 µm
Layer 1
Copper layer
Layer 2
RO4003 dielectric layer
(Hydrocarbon/wovenglass)
Layer 3
Copper layer
AC signals traces = 50Ω microstrip lines
DC signals traces (B/GB, GA, ADC Diode,
SDA)
Layer thickness = 200 µm
Dielectric constant = 3.4 at 10 GHz
-0.044 dB/inch insertion loss at 2.5 GHz
-0.318 dB/inch insertion loss at 18 GHz
Copper thickness = 35 µm
Upper ground plane = reference plane 50Ω
microstrip return
Layer 4
FR4 HTG/dielectric layer
Layer 5
Copper layer
Layer 6
FR4 HTG/dielectric layer
Layer 7
Copper layer
Layer 8
FR4 HTG/dielectric layer
AT84AS003-EB Evaluation Kit User Guide 2-1
Layer thickness = 170 µm
Copper thickness = 35 µm
Power planes = V
Layer thickness = 200 µm
Copper thickness = 35 µm
Power planes = VEE and 3.3V
Layer thickness = 170 µm
CCA
and V
CCD
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Hardware Description
Table 2-1. Board Layer Thickness Profile (Continued)
Layer Characteristics
Layer 9
Copper layer
Layer 10
FR4 HTG/dielectric layer
Layer 11
Copper layer
Layer 12
FR4 HTG/dielectric layer
Layer 13
Copper layer
Layer 14FR4 HTG/dielectric layer Layer thickness = 200 µm
Layer 15
Copper layer
Copper thickness = 35 µm
Power planes = V
Layer thickness = 200 µm
Copper thickness = 35 µm
Power planes = VMINUSD, -5V
Layer thickness = 170 µm
Copper thickness = 35 µm
Ground plane = reference plane (identical to
layer 3)
Copper thickness = 40 µm
DC signals traces (B/GB, GA, Diode, SDA)
Ground plane
PLUSD
The board is 1.6 mm thick.
2.2 Analog Inputs/Clock Inputs
The clock, analog input, reset and digital data output signals occupy the top metal layer
while the ADC and DMUX functions are located on both the top layer and the 15th layer.
The ground planes occupy layer 3, 13 and 15 (partly).
Layer 5, 7, 9 and 11 are dedicated to the power supplies.
The differential active inputs (clock, analog, DAI/DAIN, DRRB and ASYNCRST) are provided by SMA connectors.
Reference: VITELEC 142-0701-8511
Special care was taken for the routing of the analog input, clock input and DAI/DAIN signals for optimum performance in the high frequency domain:
50Ω lines matched to ±0.1 mm (in length) between VIN and VINN
50 mm max line length
1.27 mm pitch between the differential traces
400 µm line width
40 µm thickness
850 µm diameter hole in the ground layer below the VIN and VINN ball footprints
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Hardware Description
Figure 2-1. Board Layout for the Differential Analog, Clock and DAI/DAIN Inputs
400 µm
e = 40 µm
µm
870
400
µm
2.3 Digital Outputs
RO4003
Ground plane
1270 µm
200 µ m
Note: The analog inputs are reverse terminated with 50Ω to ground very close to the
device (same line length used for both reverse termination).
Figure 2-2. Differential Analog Inputs Implementation
50Ω
VIN (V25)
GND
VIN
VIN (W24)
AT84AS003
VINN
50Ω
GND
VINN
(W23)
VINN (V22)
The digital output lines were designed with the following recommendations:
50Ω lines matched to ± 0.5 mm (in length) between signal of the same differential pair
80 mm max line length
±1 mm line length difference between signals of two ports
±1.5 mm max line length difference between all signals
770 µm pitch between the differential traces
370 µm line width
40 µm thickness
Figure 2-3. Board Layout for the Differential Digital Outputs
370
µm
e = 40 µm
µm
400
RO4003
Ground plane
µm
770
370
µm
200 µ m
The digital outputs are compatible with LVDS standard. They are on-board 100Ω differentially terminated as shown in Figure 2-4 on page 2-4.
AT84AS003-EB Evaluation Kit User Guide 2-3
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Hardware Description
Figure 2-4. Differential Digital Outputs Implementation
50Ω
Line
Di
10
50
Ω Line
0Ω
DiN
Ω Line
50
DRN
100Ω
50
Ω Line
DR
Double row 2.54 mm pitch connectors are used for the digital output data. The upper
row is connected to the signal while the lower row is connected to Ground, as illustrated
in Figure 2-5
Figure 2-5. Differential Digital Clock Outputs 2.54 mm Pitch Connector
(Example Port A)
Signal
A0N A0 AORN
…
A
/DR
GND A0N A0
GND GND GND GND GND GND GND GND
AOR
N
/DRA
A1N AORN AOR GND B0
Ground
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Section 3
Operating Characteristics
3.1 Introduction
3.2 Operating Procedure
This section describes a typical configuration for operating the evaluation board of the
AT84AS003 10-bit 1.5 Gsps ADC with 1:2/4 DMUX.
The analog input signal and the sampling clock signal can be accessed either in differential or single-ended fashion.
The single-ended configuration is the most straightforward but it is recommended to
work in differential mode (especially for the clock signal) for frequencies above 1 GHz.
In the case of use in differential mode, the AT84AS003 clock inputs have to be fed with
balanced signals (use a balun or Hybrid junction to convert a single signal to a differential signal).
In the case of use in single-ended mode, the inverted analog input V
CLKN should be terminated properly with 50Ω to ground (50Ω caps can be used to terminate the SMA connectors).
The RF sources can then be connected directly to the ADC's in-phase analog and clock
inputs.
1. Connect the power supplies and ground accesses through the dedicated banana
jacks.V
and -5V
V
CCD
reunited via a short-circuit available on the top metal layer.
2. Connect the clock input signals. In single-ended mode, terminate the inverted
phase signal (CLKN) to a 50Ω termination to ground (50Ω cap).Use a low-phase
noise High Frequency generator.The clock input level is typically 0 dBm and
should not exceed 4 dBm (into 50Ω).The clock frequency can range from 150
MHz up to 1.5 GHz.
3. Connect the analog input signal. In single-ended mode, VINN should be terminated by 50Ω to ground (50Ω cap).Use a low-phase noise High Frequency
generator. The analog input full-scale is 500 mV peak-to-peak around
0V (± 250 mV). It is recommended to use the ADC with an input signal of -1
dBFS max (to avoid saturation of the ADC). The analog input frequency can
range from DC up to 1.8 GHz. At 3 GHz, the ADC attenuates the input signal by
3 dB.
4. Connect the high-speed acquisition system probes to the output connectors.
= -5V, V
EE
= 3.3V and 3.3V and VEE = -5V and -5V have separated planes but can be
MINUSD
= -2.2V, V
= 3.3V, V
CCA
= 3.3V, V
CCD
PLUSD
and clock input
INN
= 2.5V, 3.3V
AT84AS003-EB Evaluation Kit User Guide 3-1
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Operating Characteristics
The digital data are differentially terminated on-board (100Ω) however, they can be
probed either in differential or in single-ended mode.
5. Connect the ADC and DMUX function jumpers.
All instrumentation and connectors are now connected.
6. Switch on the power supplies (recommended power up sequence: simultaneous
or in the following order: V
V
= 3.3V, V
CCA
= 3.3V, 3.3V and V
CCD
= -5V and -5V, then V
EE
PLUSD
= 2.5V).
= -2.2V, and finally
MINUSD
7. Switch on the RF clock generator.
8. Switch on the RF signal generator.
9. Perform an asynchronous reset (ASYNCRST push button) on the device.
The AT84AS003-EB evaluation board is now ready for operation
Table 3-1. Absolute Maximum Ratings
Parameter Symbol Value Unit
Analog positive supply voltage V
Digital positive supply voltage V
Analog negative supply voltage V
Digital positive supply voltage V
Digital negative supply voltage V
CCA
CCD
EE
PLUSD
MINUSD
Maximum difference between
V
and V
PLUSD
MINUSD
Analog input voltages V
V
PLUSD
IN
- V
or V
MINUSD
INN
Maximum difference between
and V
V
IN
INN
Clock input voltage V
VIN or V
or V
CLK
INN
CLKN
Maximum difference between
and V
V
CLK
CLKN
V
- V
CLK
CLKN
Control input voltage GA, SDAEN -5 to 0.8 V
Digital input voltage SDAEN, B/GB, PGEB, DECB -5 to 0.8 V
GND to 6 V
GND to 3.6 V
GND to -5.5 V
GND to 3 V
GND to -3 V
5V
-1.5 to 1.5 V
-1.5 to 1.5
-1 to 1 V
-1 to 1 Vpp
ADC reset voltage DRRB -5 to 0.8 V
DMUX function input voltage
DMUX Asynchronous Reset ASYNCRST -0.3 to V
DMUX input Voltage DAI, DAIN -0.3 to V
DMUX control Voltage CLKDACTRL, DACTRL -0.3 to V
RS, CLKTYPE, DRTYPE, SLEEP,
STAGG, BIST, DAEN -0.3 to V
+ 0.3 V
CCD
+ 0.3
CCD
+ 0.3 V
CCD
+ 0.3 V
CCD
Maximum input voltage on DIODE DIODE ADC 700 mV
Maximum input current on DIODE DIODE ADC 1 mA
Junction temperature T
J
135 °C
Note: 1. Absolute maximum ratings are short term limiting values (referenced to GND = 0 V), to be applied individually, while other
parameters are within specified operating conditions. Long exposure to maximum ratings may affect device reliability.
2. All integrated circuits have to be handled with appropriate care to avoid damage due to ESD. Damage caused by inappropriate handling or storage could range from performance degradation to complete failure
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Operating Characteristics
Table 3-2. Operating Characteristics Ambient Temperature (V
V
PLUSD
= 2.5V; V
INN
- V
INN
= 1 dBFS, P
= 0 dBm Differential
CLK
CCA
= V
= 3.3V, VEE = -5V, V
CCD
MINUSD
= -2.2V;
Parameter Symbol Min Typ Max Unit
Resolution 10 Bit
Power Requirements
Positive supply voltage
- Analog
- Digital
- Output V
CCD
V
V
V
PLUSD
CCA
CCD
3.15
3.15
2.4
3.3
3.3
2.5
3.45
3.45
2.6
Positive supply current
- Analog
- Digital V
- Digital V
- Output V
VCCA
CCD
CCD
CCD
1:2 DMUX
1:4 DMUX
I
I
I
I
VPLUSD
Negative supply voltage V
Negative supply current I
Negative supply voltage V
Negative supply current V
MINUSD
MINUSD
VCCA
VCCD
VCCD
EE
VEE
-5.25 -5 -4.75 V
-2.3 -2.2 -2.1 V
80
535
565
450
100
590
620
470
620 660 mA
190 200 mA
Power Dissipation (1:2 DMUX) PD 6.5 7.1 W
V
V
V
mA
mA
mA
mA
Analog Inputs
Full-scale input voltage range (differential
mode)
(0V common mode voltage)
Full-scale input voltage range (singleended input option) (0V common mode
V
VIN, V
voltage)
Analog input power level
(50Ω single-ended)
Analog input capacitance (die) C
Input leakage current I
Input resistance
- Single-ended
- Differential
Clock Inputs
Logic common mode
compatibility for clock inputs
V
IN
INN
INN
P
IN
IN
IN
R
IN
R
IN
-125
-125
-250 0 250 mV
-2 dBm
0.3 pF
10 µA
49
98
50
100
125
125
51
102
mV
mV
Ω
Ω
Differential ECL to LVDS
(AC coupling)
AT84AS003-EB Evaluation Kit User Guide 3-3
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Operating Characteristics
Table 3-2. Operating Characteristics Ambient Temperature (V
V
PLUSD
= 2.5V; V
INN
- V
INN
= 1 dBFS, P
= 0 dBm Differential (Continued)
CLK
CCA
= V
= 3.3V, VEE = -5V, V
CCD
Parameter Symbol Min Typ Max Unit
Clock input common voltage range
(V
CLK
or V
CLKN
)
V
CM
-1.2 0 3.3 V
(DC coupled clock input)
Clock input power level (low-phase noise
sinewave input) 50Ω single-ended or
P
CLK
-4 0 4 dBm
100Ω differential
Clock input swing (single ended; with
CLKN = 50Ω to GND)
Clock input swing (differential voltage) on
each clock input
Clock input capacitance (die) C
Clock input resistance
- Single-ended
- Differential ended
V
CLK
, V
V
CLK
CLKN
LK
R
CLK
R
CLK
±200 ±320 ±500 mV
±141 ±226 ±354 mV
0.3 pF
45
90
50
100
Digital Data Outputs
Logic compatibility LVDS
50Ω transmission lines, 100Ω (2 × 50Ω
differential termination)
- Logic low
- Logic high
- Differential output
V
V
V
V
OL
OH
ODIFF
OCM
–
1.25
250
1.125
1.075
1.425
350
1.25
- Common mode
Control Function Inputs
DRRB and ASYNCRST
- Logic low
- Logic high
- Common
V
IL
V
IH
V
ICM
0
1.6
1.4
MINUSD
55
110
1.25
–
450
1.375
1
3.3
= -2.2V;
Ω
Ω
V
V
mV
V
V
V
V
RS, DRTYPE, SLEEP, STAGG, BIST,
DAEN
- Logic low
- Logic high
R
IL
R
IH
0
10 K
10
Infinite
Ω
Ω
SDAEN, PGEB, B/GB
- Logic low
- Logic high -2
DAI, DAIN
Differential Input
common mode
V
IDIFF
V
ICM
100
1
V
EE
0
1.25
350
-3
0
1.6
–
V
V
V
mV
GA, SDA -0.5 0.5 V
CLKDACTRL, DACTRL 1/3 × V
CCD
1/3 × V
CCD
2/3 × V
CCD
V
3-4 AT84AS003-EB Evaluation Kit User Guide
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Section 4
Application Information
4.1 Introduction
4.2 Analog Inputs
4.3 Clock Inputs
4.4 Digital Outputs
For this section, refer also to the product “Main features” section of the AT84AS003
datasheet ref 0808.
The analog inputs can be entered in differential or in single-ended mode but a differential mode is recommended using a balun or hybrid junction.
In single-ended mode, the unused input signal SMA connector should be terminated
with a 50Ω cap to provide proper termination of the differential pair.
It is recommended that a filter be used to optimize the dynamic performance and the
spectral response of the ADC.
The clock inputs can be entered in differential or in single-ended mode without any high
speed performance degradation for a clock frequency up to 1 GHz. At higher rates, it is
recommended to drive the clock inputs differentially using a balun or hybrid junction.
In single-ended mode, the unused clock input signal SMA connector should be terminated with a 50Ω cap to provide proper termination of the differential pair.
The clock can be supplied with a sinewave signal centered on 0V common mode.
The digital outputs (data and Data Ready) are LVDS compatible. 100Ω differential termination is provided on-board.
AT84AS003-EB Evaluation Kit User Guide 4-1
0905C–BDC–09/07
Application Information
Figure 4-1. Differential Digital Outputs Implementation
50Ω Line
Di
50Ω Line
100Ω
DiN
50Ω Line
DRN
50Ω Line
100Ω
DR
4.5 ADC Functions
4.5.1 Data Ready Reset The Data Ready reset signal is accessed via an SMA connector.
DRRB is CMOS/LVCMOS compatible:
VIL = 0 (typical)
VIH = V
This signal acts as an internal reset of the device. It is not mandatory for proper operation of the device. It is only used to determine exactly the first data to be sampled.
When applied, the clock outputs are reset. The reset pulse should last at least 1 ns.
An asynchronous reset (ASYNCRST push button) should be applied while DRRB is
active (low) in order to reset properly the whole device.
CCA
(typical)
4.5.2 Binary or Gray Output Coding
In most cases (single channel application, no need to know which data will be the first
one to be sampled), this reset can be left unused.
One jumper is used to set the ADC output coding mode in either Binary or Gray:
Binary coding: connect the jumper to ground
Gray coding: connect the jumper to the upper position (see Figure 4-2)
Figure 4-2. Binary or Gray coding Jumper Position
B/GB
GND
Binary
Coding
B/GB
GND
Gray
Coding
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Application Information
j
t
n
4.5.3 Gain Adjust The ADC gain can be adjusted by the means of the GA potentiometer (varying from -
0.5V to 0.5V around 0V nominal value). A GA jumper is available to allow or disable this
function.
When connected to ground, the Gain adjustment is disabled. In the other position, the
user can tune the ADC gain by varying the GA potentiometer.
The GA potentiometer allows you to tune the Gain from approximately 0.85 to 1.15.
Figure 4-3. ADC Gain Adjust Jumper Settings
GA
GND
Allowed
GND
No Gain
Ad
ustment
GA
Gain Adjustmen
Figure 4-4. The ADC Gain Adjust Function is given in Figure 4.4
1,30
1,20
1,10
1,00
0,90
ADC Gai
0,80
0,70
0,60
0,50
-0,5 -0,4 -0,3 -0,2 -0,1 0 0,1 0,2 0,3 0,4 0,5
V
Gain Adjust Voltage (V)
GA
typical
min
4.5.4 Sampling Delay Adjust
The SDA function (Sampling delay adjust) allows to fine tune the sampling ADC aperture delay TA around its nominal value (160 ps). This functionality is enabled thanks to
the SDAEN signal, which is inactive when its associated jumper is connected to GND, or
active in the other position
AT84AS003-EB Evaluation Kit User Guide 4-3
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Application Information
Figure 4-5. DC SDAEN Jumper Settings
The variation of the delay around its nominal value as function of SDA voltage is shown
in Figure 4-6 on page 4-4.
The typical tuning range is ±120 ps for an applied control voltage varying between
-0.5 V to 0.5 V on SDA potentiometer. The variation of the delay in function of the temperature is negligible.
Figure 4-6. SDA Transfer Functions
300p
SDAEN
GND
SDA Disabled
Delay in the variable cell at 60C
SDAEN
GND
SDA Allowed
200p
100p
-500m
-400m
-300m
-200m
-100m
-0.00
100m
200m
300m
400m
500m
sda
4.5.5 Pattern Generator The AT84AS003 is able to generate by itself (no need of analog input signal) a series of
patterns made of 10-bit transitioning from 0 to 1 or 1 to 0.
At the AT84AS003 output, all bits of each port are all 1 or all 0 and do not transition
every cycle (all bits of all ports remain the same: that is, if port A = 1010101010, then at
next cycle, port A = 1010101010). Ports A and C output the same data, ports B and D
output the inverted data compared to ports A and D.
This pattern generator can be used to test the ADC part of the device (a BIST is available for the testing of the DMUX part of the device).
One jumper is used to set the ADC in this Test mode:
Pattern Generator inactive: connect the jumper to ground
Pattern Generator active: connect the jumper to the upper position (see Figure 4-3 on
page 4-3)
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Figure 4-7. Pattern Generator Enable Jumper Position
Application Information
PGEB
GND
Pattern Generator
Inactive
Pattern Generator
PGEB
GND
Active
4.6 DMUX Function
4.6.1 ASYNCRST The asynchronous reset is mandatory to start the device properly. It must be applied
after power up of the device.
A push button is provided to perform this reset and pull-up and pull-down resistors allow
to keep the ASYNCRST signal inactive.
Figure 4-8. Reset Function
3.3V
15K
3.3V
AT84AS003
4.7K
GND
If the DRRB reset is also used, it is recommended to apply the asynchronous reset while
the DRRB reset is active.
The first data is available at the device output after TOD + 7.5 cycles.
4.6.2 CLKDACTRL A delay cell is provided to allow you to tune the delay between the clock and data at the
DMUX input. The delay is controlled via the CLKDACTRL potentiometer.
This cell allows you to delay by ±250 ps (around 250 ps) the internal DMUX clock via the
CLKDACTRL potentiometer (varying from V
/3 to (2 × V
CCD
CCD
)/3).
AT84AS003-EB Evaluation Kit User Guide 4-5
0905C–BDC–09/07
Application Information
Figure 4-9. CLKDACTRL Function
3.3V
10 KΩ
10 KΩ
AT84AS003
10 KΩ
GND
4.6.3 DACTRL A standalone delay cell is available (Input = DAI/DAIN, output DAO/DAON, control =
DACTRL, Enable = DAEN).
This cell allows you to delay by ±250 ps (around 250 ps) the incoming signal DAI/DAIN
via the DACTRL potentiometer (varying from V
/3 to (2 × V
CCD
CCD
)/3).
Figure 4-10. DACTRL Funtion
3.3V
10 KΩ
10 KΩ
AT84AS003
10 KΩ
GND
4.6.4 RS, DRTYPE, DAEN,
BIST, CLKTYPE,
Seven Jumpers are provided for the RS, DRTYPE, DAEN, BIST, CLKTYPE, SLEEP
and STAGG functions.
SLEEP, STAGG
4-6 AT84AS003-EB Evaluation Kit User Guide
0905C–BDC–09/07
Figure 4-11. SMUX Functions and Description
Function Description Jumper Settings
Built-In Self Test:
BIST
CLKTYPE JUMPER OUT (ALWAYS)
DAEN
DRTYPE
RS
SLEEP
- Active: checker-board pattern available at the device’s
output
- Inactive: normal mode
Standalone Delay Cell Enable
- DAEN active: DAI/DAIN delay can be controlled via
- DACTRL and output in DAO/DAON
- DAEN inactive: the standalone delay cell cannot be
used
Output clock mode:
- DR/2 = data valid on both rising and falling edges of
the DR/DRN signal
- DR = data valid on each rising edge of the DR/DRN
signal
Ratio selection:
- 1:2
- 1:4
Sleep mode:
- Active: the device is in a partial standby mode
- SLEEP inactive: normal mode
BIST: jumper ON
No BIST: jumper OUT
DAEN active: jumper ON
DAEN inactive: jumper OUT
DR/2: jumper ON
DR: jumper OUT
1:2: Jumper ON
1:4: Jumper OUT
SLEEP: jumper ON
SLEEP: inactive: jumper OUT
Application Information
STAGG
Simultaneous or staggered output mode:
- STAGG active: staggered output data
- STAGG inactive: simultaneous output data
Figure 4-12. DMUX Functions Jumper Positions
Jumper ON
Note: The BIST is made of a 10-bit sequence available on all 4 ports of the device (set the
AT84AS003 in 1:4 mode).
The sequence is as follows:
RS
DRTYPE
DAEN
BIST
CLKTYPE
SLEEP
STAGG
STAGG: jumper ON
STAGG: inactive: jumper OUT
RS
DRTYPE
DAEN
BIST
CLKTYPE
SLEEP
STAGG
Jumper OUT
Cycle 0:
Port A = 1010101010
AT84AS003-EB Evaluation Kit User Guide 4-7
0905C–BDC–09/07
Application Information
Port B = 1010101010
Port C = 0101010101
Port D = 1010101010
Cycle 1:
Port B = 0101010101
Port A = 0101010101
Port C = 1010101010
Port D = 0101010101
4.6.5 Additional OR bits In simultaneous mode, the out of range signal of the ADC is demultiplexed by the DMUX and output on all ports as the (AOR/DRAN, AORN/DRA), (BOR/DRBN, BORN/DRB), (COR/DRCN, CORN/DRC) and (DOR/DRDN, DORN/DRD) signals.
These signals can be used to detect if the input of the ADC is above the full-scale.
In staggered mode, these signals correspond to the output clock for each port:
DRA, DRAN for Port A (pins A6, B6)
DRB, DRBN for Port B (pins J2, H1)
4.7 Diode for Die
Junction
Temperature
Monitoring
DRC, DRCN for Port C (pins W5, V5)
DRD, DRDN for Port D (pins W17, V17)
One diode for die junction temperature measurement is available, for maximum junction
temperature monitoring (hot point measurement) of the ADC.
The measurement method consists in forcing a 1 mA current into a diode mounted
transistor.
The measurement setup is shown in Figure 4-7 on page 4-7.
Figure 4-13. ADC DIODE Measurement Setup
IGND
1 mA
Idiode
V
Note: The 1 mA current can be supplied by a multimeter set in this specific current
source mode, in this case, the voltage measured between the diode pin and
ground is displayed on the multimeter.
The Diode characteristic of the ADC is given in Figure 4-14 on page 4-9.
4-8 AT84AS003-EB Evaluation Kit User Guide
0905C–BDC–09/07
Figure 4-14. ADC DIODE Characteristics (1 = 1 mA)
Junction Temperature Versus Diode Voltage for I =1 mA
950
940
930
920
910
900
890
880
870
860
850
Diode Voltage (mV)
840
830
820
810
800
79 0
- 10 0 10 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 110
Application Information
Junction Temperature (˚C)
AT84AS003-EB Evaluation Kit User Guide 4-9
0905C–BDC–09/07
Application Information
4.8 Test Bench Description
Figure 4-15. Test Bench Schematics
HP86665B sinewave
signal source --> Fin
Signal generator is
phase-locked with the
clock generator
HP8665 sinewave
clock source --> Fs
Acquisition Board
D0 --> D9
8 channel
BPF
MACOM - H9
180
AT84AS003
ADC 10BIT 1.5 Gsps
DEMUX
A
B
Balun
o
C
0oC
Fs = ADC sampling data
Power supplies
GW PPT
Power supplies
GW PPT
D
C
Clock
HP16500C
GPIB bus
analysis logic
4-10 AT84AS003-EB Evaluation Kit User Guide
0905C–BDC–09/07
5.1 Thermal Characteristics
Section 5
Package Information
Table 5-1. Thermal Resistance
Thermal Resistance ADC Alone DMUX Alone
RTHj-top-of-case
RTHj-bottom-of-balls
RTHj-board
RTHj-ambiant
An external heat sink must be placed on top of package.
It is advised to use an external heat sink with intrinsic thermal resistance better than
4°C/Watt when using air at room temperature 20~25°C.
Use an external heat sink with intrinsic thermal resistance better than 3°C/Watt when
using air at 60°C.
Notes: 1. No air, pure conduction, no radiation
2. Jedec condition, still air, horizontal air (board sign = 1.6 mm)
(1)
(1)
(1)
(2)
4.11°C/Watt 1.48°C/Watt
6.94°C/Watt 3.89°C/Watt
7.98°C/Watt 4.88°C/Watt
17.13°C/Watt 13.88°C/Watt
AT84AS003-EB Evaluation Kit User Guide 5-1
0905C–BDC–09/07
Package Information
5-2 AT84AS003-EB Evaluation Kit User Guide
0905C–BDC–09/07
Ordering Information
Table 6-1.
Part Number Package Temperature Range Screening Comments
Prototype version
AT84XAS003TP EBGA 317 Ambient Prototype
Please contact your local sales
office
Section 6
AT84AS003CTP EBGA 317
AT84AS003VTP EBGA 317
AT84XAS003TPY
AT84AS003CTPY
AT84AS003VTPY
AT84AS003TP-EB EBGA 317 Ambient Prototype Evaluation kit
EBGA 317
RoHS
EBGA 317
RoHS
EBGA 317
RoHS
Commercial “C”
0°C < T
Industrial “V” grade
-20°C < T
Ambient Prototype
Commercial "C" grade
0°C < T
Industrial "V" grade
-20°C < T
; TJ < 90°C
C
; TJ < 110°C
C
; TJ < 90°C
C
; TJ < 110°C
C
Standard
Standard
Please contact your local Sales
office
Standard
Standard
AT84AS003-EB Evaluation Kit User Guide 6-1
0905C–BDC–09/07
Ordering Information
6-2 AT84AS003-EB Evaluation Kit User Guide
0905C–BDC–09/07
7.1 AT84AS003-EB Electrical Schematics
Figure 7-1. Power Supplies Decoupling
Section 7
Appendix
DECOUPLING
DECOUPLING
DECOUPLING
DECOUPLING
DECOUPLING
DECOUPLING
AT84AS003-EB Evaluation Kit User Guide 7-1
0905C–BDC–09/07
Appendix
Figure 7-2. Power Supplies Connection
Figure 7-3. Power Supplies bypassing
7-2 AT84AS003-EB Evaluation Kit User Guide
0905C–BDC–09/07
Figure 7-4. AT84AS003-EB Electrical Schematic
Appendix
AT84AS003-EB Evaluation Kit User Guide 7-3
0905C–BDC–09/07
Appendix
7.2 AT84AS003-EB Board Layers
Figure 7-5. Top Layer
Figure 7-6. Bottom Layer
7-4 AT84AS003-EB Evaluation Kit User Guide
0905C–BDC–09/07
Figure 7-7. Equipped Board (Top)
Appendix
Figure 7-8. Equipped Board (Bottom)
AT84AS003-EB Evaluation Kit User Guide 7-5
0905C–BDC–09/07
Appendix
7-6 AT84AS003-EB Evaluation Kit User Guide
0905C–BDC–09/07
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0905C–BDC–09/07
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