DYNEX MAS9264T95LD, MAS9264T95LC, MAS9264T95LB, MAS9264T95FS, MAS9264T95FE Datasheet

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DYNEX MAS9264T95LD, MAS9264T95LC, MAS9264T95LB, MAS9264T95FS, MAS9264T95FE, MAS9264T95FD, MAS9264T95FC, MAS9264T95FB, MAS9264T95NL, MAS9264T95NE, MAS9264T95ND, MAS9264T95NC, MAS9264T95LS, MAS9264T95LL, MAS9264C70FD, MAS9264C70FC, MAS9264C70FB, MAS9264C70CS, MAS9264C70CE, MAS9264C70CD, MAS9264C70CC, MAS9264C70CB, MAS9264T95CS, MAS9264T95CL, MAS9264T95CE, MAS9264T95CD, MAS9264T95CB, MAS9264T70NS, MAS9264T70NL, MAS9264T70NE, MAS9264C95LC, MAS9264C95LB, MAS9264C95FS, MAS9264C95FL, MAS9264C95FD, MAS9264C95FC, MAS9264C95FB, MAS9264C95CS, MAS9264T70NB, MAS9264T70LS, MAS9264T70LL, MAS9264T70LE, MAS9264T70LC, MAS9264T70LB, MAS9264T70FS, MAS9264T70FL, MAS9264C95CD, MAS9264C95CC, MAS9264C95CB, MAS9264C70NS, MAS9264C70NE, MAS9264C70ND, MAS9264C95NS, MAS9264C95NL, MAS9264C95NC, MAS9264C95NB, MAS9264C95LS, MAS9264C95LL, MAS9264T70FE, MAS9264T70FD, MAS9264T70FC, MAS9264T70FB, MAS9264T70CE, MAS9264T70CD, MAS9264T70CC, MAS9264T70CB, MAS9264C70NB, MAS9264C70LS, MAS9264C70LE, MAS9264C70LD, MAS9264C70LB, MAS9264C70FS, MAS9264C70FL, MAS9264C70FE, MAR9264T70CB, MAR9264C95NL, MAR9264C95NE, MAR9264C95ND, MAR9264C95NC, MAR9264C95LS, MAR9264C95LL, MAR9264C95LE, MAR9264T95LE, MAR9264T95LC, MAR9264T95LB, MAR9264T95FS, MAR9264T95FL, MAR9264T95FD, MAR9264T95FC, MAR9264T95FB, MAR9264T70FE, MAR9264T70FC, MAR9264T70FB, MAR9264T70CS, MAR9264T70CL, MAR9264T70CD, MAR9264T70CC, MAR9264T95CS, MAR9264T95CL, MAR9264T95CD, MAR9264T95CC, MAR9264T95CB, MAR9264T70NS, MAR9264T70NE, MAR9264T70ND, MAR9264T95NS, MAR9264T95NE, MAR9264T95ND, MAR9264T95NC, MAR9264T95NB, MAR9264T95LS, MAR9264T95LL, MAR9264C95LD, MAR9264C95LC, MAR9264C95LB, MAR9264C95FL, MAR9264C95FE, MAR9264C95FD, MAR9264C95FC, MAR9264C95FB, MAR9264C95CL, MAR9264C95CE, MAR9264C95CD, MAR9264C95CC, MAR9264C95CB, MAR9264C70NL, MAR9264C70NE, MAR9264C70ND, MAR9264C70NC, MAR9264T70NC, MAR9264T70NB, MAR9264T70LS, MAR9264T70LE, MAR9264T70LD, MAR9264T70LC, MAR9264T70LB, MAR9264T70FS, MAR9264C70FC, MAR9264C70FB, MAR9264C70NB, MAR9264C70LS, MAR9264C70LL, MAR9264C70LD, MAR9264C70LC, MAR9264C70LB, MAR9264C70FS, MAR9264C70FL, MAQ9264T95CE, MAQ9264T95CC, MAQ9264T95CB, MAQ9264T70NS, MAQ9264T70NL, MAQ9264T70ND, MAQ9264T70NC, MAQ9264T70NB, MAQ9264T95NS, MAQ9264T95NE, MAQ9264T95ND, MAQ9264T95NC, MAQ9264T95NB, MAQ9264T95LL, MAQ9264T95LE, MAQ9264T95LD, MAQ9264C95NL, MAQ9264C95ND, MAQ9264C95NC, MAQ9264C95NB, MAQ9264C95LS, MAQ9264C95LE, MAQ9264C95LD, MAQ9264C95LC, MAQ9264T70LS, MAQ9264T70LE, MAQ9264T70LD, MAQ9264T70LC, MAQ9264T70LB, MAQ9264T70FL, MAQ9264T70FE, MAQ9264T70FD, MAQ9264C95LB, MAQ9264C95FL, MAQ9264C95FE, MAQ9264C95FD, MAQ9264C95FC, MAQ9264C95CS, MAQ9264C95CL, MAQ9264C95CE, MAQ9264T70FC, MAQ9264T70CS, MAQ9264T70CL, MAQ9264T70CE, MAQ9264T70CD, MAQ9264T70CB, MAQ9264C95NS, MAQ9264C95NR, MAQ9264T95LC, MAQ9264T95FL, MAQ9264T95FE, MAQ9264T95FD, MAQ9264T95FC, MAQ9264T95CL, MAQ9264C95CD, MAQ9264C95CC, MAQ9264C95CB, MAQ9264C70NS, MAQ9264C70NE, MAQ9264C70ND, MAQ9264C70NC, MAQ9264C70NB, MAQ9264C70LL, MAQ9264C70LE, MAQ9264C70LD, MAQ9264C70LC, MAQ9264C70FS, MAQ9264C70FL, MAQ9264C70FE, MAQ9264C70FD, MAQ9264C70FB, MAQ9264C70CS, MAQ9264C70CL, MAQ9264C70CE, MAQ9264C70CC, MAQ9264C70CB, MAS9264T95LE, MAS9264T95FL, MAS9264T95NS, MAS9264T95NB, MAS9264C70CL, MAS9264T95CC, MAS9264C95LD, MAS9264C95FE, MAS9264T70NC, MAS9264T70LD, MAS9264C95CL, MAS9264C95CE, MAS9264C70NL, MAS9264C70NG, MAS9264C95NE, MAS9264C95ND, MAS9264C95LG, MAS9264C95LE, MAS9264T70CS, MAS9264T70CL, MAS9264C70NC, MAS9264C70LC, MAR9264C95NS, MAR9264C95NB, MAR9264T95LD, MAR9264T95FE, MAR9264T70FD, MAR9264T70CE, MAR9264T95CE, MAR9264T70NL, MAQ9264T95CD, MAQ9264T70NE, MAQ9264T95NL, MAQ9264T95LS, MAQ9264C95NE, MAQ9264C95LL, MAQ9264T70LL, MAQ9264T70FS, MAQ9264C95FS, MAQ9264C95FB, MAQ9264T70FB, MAQ9264T70CC, MAQ9264T95LB, MAQ9264T95FS, MAQ9264T95FB, MAQ9264T95CS, MAQ9264C70NL, MAQ9264C70LS, MAQ9264C70LB, MAQ9264C70FC, MAR9264T95NL, MAR9264T95LR, MAR9264C95FS, MAR9264C95CS, MAR9264C70NS, MAR9264T70LL, MAR9264T70FL, MAR9264C70FD, MAR9264C70LE, MAR9264C70FE, MAQ9264C70CD Datasheet

MA9264

1/15

The MA9264 64k Static RAM is configured as 8192x8 bits and

manufactured using CMOS-SOS high performance, radiation hard,

1.5µm technology. The design uses a 6 transistor cell and has full static operation with

no clock or timing strobe required. Address input buffers are deselected when chip select is in the HIGH state.

See Application Note “Overview of the Dynex Semiconductor

Radiation Hard 1.5µm CMOS/SOS SRAM Range”.

FEATURES

■ 1.5µm CMOS-SOS Technology

■ Latch-up Free

■ Fast Access Time 70ns Typical

■ Total Dose 10

Rad(Si)

■ Transient Upset >10

Rad(Si)/sec

■ SEU 4.3 x 10

-11

Errors/bitday

■ Single 5V Supply

■ Three State Output

■ Low Standby Current 100µA Typical

■ -55°C to +125°C Operation

■ All Inputs and Outputs Fully TTL or CMOS

Compatible

■ Fully Static Operation

Operation Mode CS CE OE WE I/O Power

Read L H L H D OUT Write L H X L D IN ISB1

Output Disable L H H H High Z

Standby H X X X High Z ISB2

XLXX X

Figure 1: Truth Table

Figure 2: Block Diagram

A12

A9 A8

A4 A3

A6 A5

A D D R E S S

B U F F E R

R O W

D E C O D E R

A10 A0 A1 A2 A11

MA9264

Radiation Hard 8192x8 Bit Static RAM

Replaces June 1999 version, DS3692-6.0 DS3692-7.0 January 2000

MA9264

2/15

SIGNAL DEFINITIONS

A0-12

Address input pins which select a particular eight bit word within the memory array.

D0-7

Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write operation.

Chip Select, which, at low level, activates a read or write operation. When at a high level it defaults the SRAM to a prechargencondition and holds the data output drivers in a high impedance state.

Write Enable which when at a low level enables a write and holds data output drivers in a high impedance state. When at a high level, it enables a read.

Output Enable which when at a high level holds the data output drivers in a high impedance state. When at a low level, data output driver state is defined by CS, WE and CE. If this signal is not used it must be connected to VSS.

Chip Enable which when at a high level allows normal operation. When at a low level it defaults the SRAM to a precharge condition, disables the input circuits on all input pins and holds the data output drivers in a high impedance state. If this signal is not used it must be connected to VDD.

MA9264

3/15

CHARACTERISTICS AND RATINGS

Symbol Parameter Min. Max. Units

Supply Voltage -0.5 7.0 V

Input Voltage -0.3 VDD+0.3 V

Operating Temperature -55 125 °C

Storage Temperature -65 150 °C

Figure 3: Absolute Maximum Ratings

Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functlonal operation of the device at these condltions, or at any other condition above those indicated in the operations section of this specification, is not Implied Exposure to absolute maxlmum rating conditions for extended perlods may affect device reliability.

Notes for Tables 4 and 5: Characteristics apply to pre radiation at T

= -55°C to +125°C with VDD = 5V ±10% and to post 100k Rad(Si) total dose radiation at TA = 25°C with VDD = 5V ±10% (characteristics at higher radiation levels available on request). GROUP A SUBGROUPS 1, 2, 3.

Symbol Parameter Conditions (Option) Min. Typ. Max. Units

Supply voltage - 4.5 5.0 5.5 V

Logical ‘1’ Input Voltage - (TTL) VDD/2 - V

(CMOS) 0.8 V

-VDDV

Logical ‘0’ Input Voltage - (TTL) V

- 0.8 V

(CMOS) V

- 0.2 V

OH1

Logical ‘1’ Output Voltage I

OH1

= -2mA 2.4 - - V

OH2

Logical ‘1’ Output Voltage I

OH2

= -1mA V

-0.5 - - V

Logical ‘0’ Output Voltage IOL = 4mA - - 0.4 V

Input Leakage Current VIN = VDD or VSS All inputs - - ±10 µA

Output Leakage Current Chip disabled, V

OUT

= VDD or V

--±10 µA

SB1

Selected Static Current (CMOS) All inputs = V

-0.2V - 0.1 10 mA

except CS = V

+0.2V

Dynamic Operating Current fRC = 1MHz, all inputs - 6 18 mA (CMOS) switching, VIH = V

-0.2V

SB2

Standby Supply Current CS = V

-0.2V - 0.1 10 mA

CE = V

+0.2V

Figure 4: Electrical Characteristics

Symbol Parameter Conditions (Option) Min. Typ. Max. Units

VCC for Data Retention CS = V

DR,

CE = V

2.0 - - V

DDR

Data Retention Current CS = VDR, VDR = 2.0V - 0.05 4 mA

CE = V

Figure 5: Data Retention Characteristics

MA9264

4/15

AC CHARACTERISTICS

Conditions of Test for Tables 5 and 6:

1. Input pulse = VSS to 3.0V (TTL) and VSS to 4.0V (CMOS).

2. Times measurement reference level = 1.5V.

3. Input Rise and Fall times ≤5ns.

4. Output load 1TTL gate and CL = 60pF.

5. Transition is measured at ±500mV from steady state.

6. This parameter is sampled and not 100% tested. Notes for Tables 6 and 7:

Characteristics apply to pre-radiation at TA = -55°C to +125°C with V

= 5V±10% and to post 100k Rad(Si) total dose radiation

at TA = 25°C with VDD = 5V ±10%. GROUP A SUBGROUPS 9, 10, 11.

MAX9264X70 MAX9264X95

Symbol Parameter Min Max Min Max Units

AVAVR

Read Cycle Time 70 - 95 - ns

AVQV

Address Access Time - 65 - 90 ns

EHQV

Chip Select Access Time - 70 - 95 ns

SLQV

Chip Enable Access Time - 70 - 95 ns

EHQX

(5,6) Chip Selection to Output in Low Z 15 - 15 - ns

SLQX

(5,6) Chip Enable to Output in Low Z 15 - 15 - ns

ELQZ

(5,6) Chip Deselection to Output in High Z 0 20 0 20 ns

SHQZ

(5,6) Chip Disable to Output in High Z 0 20 0 20 ns

AXQX

Output Hold from Address Change 30 - 40 - ns

GLQV

Output Enable Access Time - 25 - 30 ns

GLQX

(5,6) Output Enable to Output in Low Z 15 - 15 - ns

GHQZ

(5,6) Output Enable to Output in High Z 0 20 0 20 ns

Figure 6: Read Cycle AC Electrical Characteristics

MAX9264X70 MAX9264X95

Symbol Parameter Min Max Min Max Units

AVAVW

Write Cycle Tlme 55 - 60 - ns

EHWH

Chip Selection to End of Write 50 - 60 - ns

SLWH

Chip Enable to End of Write 50 - 60 - ns

AVWH

Address Valid to End of Write 50 - 55 - ns

AVWL

Address Set Up Time 0 - 0 - ns

WLWH

Write Pulse Width 40 - 45 - ns

WHAV

Write Recovery Time 0 - 0 - ns

WLQZ

(5,6) Wnte to Output in High Z 0 20 0 20 ns

DVWH

Data to Write Time Overlap 25 - 30 - ns

WHDX

Data Hold from Write 0 - 0 - ns

WHQX

(5,6) Output Active from End to Write 0 20 0 20 ns

Figure 7: Write Cycle AC Electrical Characteristics

MA9264

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Symbol Parameter Conditions Min. Typ. Max. Units

Input Capacitance Vl = 0V - 3 5 pF

OUT

Output Capacitance V

I/O

= 0V - 5 7 pF

Note: T

= 25°C and f = 1MHz. Data obtained by characterisation or analysis; not routinely measured.

Figure 8: Capacitance

Symbol Parameter Conditions

Basic Functionality VDD = 4.5V - 5.5V, FREQ = 1MHz

VIL = VSS, VIH = VDD, VOL ≤ 1.5V, VOH ≥ 1.5V TEMP = -55°C to +125°C, GPS PATTERN SET GROUP A SUBGROUPS 7, 8A, 8B

Figure 9: Functionality

Subgroup Definition

1 Static characteristics specified in Tables 4 and 5 at +25°C 2 Static characteristics specified in Tables 4 and 5 at +125°C 3 Static characteristics specified in Tables 4 and 5 at -55°C

7 Functional characteristics specified in Table 9 at +25°C 8A Functional characteristics specified in Table 9 at +125°C 8B Functional characteristics specified in Table 9 at -55°C

9 Switching characteristics specified in Tables 6 and 7 at +25°C 10 Switching characteristics specified in Tables 6 and 7 at +125°C 11 Switching characteristics specified in Tables 6 and 7 at -55°C

Figure 10: Definition of Subgroups

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DYNEX MAS9264T95LD, MAS9264T95LC, MAS9264T95LB, MAS9264T95FS, MAS9264T95FE Datasheet

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