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USER MANUAL
CPU-111-10 (VPQ)
Intel Xeon Quad-Core 6U VPX
Single Board Computer
CPU-111-10_User_Manual_d0.1.doc Updated 25mar2013
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CPU-111-10 User’s Manual Rev. Draft 0.1
March 25, 2013
Dynatem
23263 Madero, Suite C
Mission Viejo, CA 92691
Phone: (949) 855-3235
Fax: (949) 770-3481
www.dynatem.com
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Table of Contents
1. FEATURES ......................................................................................................................................................... 1
2. RELATED DOCUMENTS ..................................................................................................................................... 3
2.1 Standards .............................................................................................................................................. 3
2.2 Product Specifications, Component Data Sheets, and Design Guides ..................................................... 3
3. HARDWARE DESCRIPTION ................................................................................................................................ 4
3.1 OVERVIEW AND SPECIFICATIONS ....................................................................................................................... 4
3.2 PROCESSING ARCHITECTURE ............................................................................................................................. 6
3.2.1 Processor ........................................................................................................................................... 6
3.2.2 Memory Controller Hub and DDR2 SDRAM ........................................................................................ 6
3.2.3 I/O Controller Hub ............................................................................................................................. 6
3.3 PCI EXPRESS ARCHITECTURE ............................................................................................................................ 8
3.3.1 Dual XMC Sites .................................................................................................................................. 8
3.3.2 PLX PEX8624 PCIe Switch ................................................................................................................... 8
3.3.2 IDT Tsi384 PCIe to PCI-X Bridges for PMC Support .............................................................................. 9
3.3.3 Intel 82599 Dual 10Gb Ethernet Controller ........................................................................................ 9
3.3.4 Intel 82571 Dual 1Gb Ethernet Controller .......................................................................................... 9
3.3.5 Silicon Motion SM750 Graphics Controller ......................................................................................... 9
3.4 10 GIGABIT ETHERNET ARCHITECTURE ............................................................................................................. 10
3.4.1 Fulcrum FM3224 Switch .................................................................................................................. 10
3.4.2 Intel 82599 Dual 10GB Ethernet ....................................................................................................... 11
3.4.3 SFP+ Interface (AEL2009) ................................................................................................................. 12
3.4.4 VPX 10Gb Ethernet I/O .................................................................................................................... 12
3.4.5 XMC 10GbE I/O ................................................................................................................................ 13
3.5 VPX GENERAL PURPOSE I/O .......................................................................................................................... 13
3.6 CLOCKING .................................................................................................................................................. 13
3.7 RESET STRUCTURE ....................................................................................................................................... 14
3.8 SMBUS ARCHITECTURE................................................................................................................................. 15
3.9 BOARD POWER ........................................................................................................................................... 16
3.10 REAR TRANSITION MODULE ....................................................................................................................... 17
4. INSTALLATION ................................................................................................................................................ 18
4.1 SELECTABLE OPTIONS ................................................................................................................................... 18
4.2 PCI MEZZANINE CARD (PMC) INSTALLATION .................................................................................................... 20
4.3 FRONT PANEL CONNECTORS AND RESET SWITCH ................................................................................................ 20
A. CONNECTOR PIN-OUTS .................................................................................................................................. 21
A.1 VPX BACKPLANE CONNECTORS ....................................................................................................................... 21
A.2 PCI-X MEZZANINE CARD CONNECTORS ............................................................................................................ 24
A.3 XMC CONNECTORS ...................................................................................................................................... 25
A.4 SFP+ PIN-OUT ............................................................................................................................................ 25
A.5 FRONT PANEL USB PIN-OUT .......................................................................................................................... 26
B. BIOS & SETUP *** NEED INPUT FROM HUNG *** .................................................................................... 27
B.1 REDIRECTING TO A SERIAL PORT ...................................................................................................................... 27
B.2 SETUP MENUS ............................................................................................................................................ 28
B.3 NAVIGATING SETUP MENUS AND FIELDS ........................................................................................................... 28
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B.4 MAIN SETUP MENU ..................................................................................................................................... 29
B.5 EXIT SETUP MENU ....................................................................................................................................... 30
B.6 BOOT SETUP MENU ..................................................................................................................................... 31
B.7 POST SETUP MENU ..................................................................................................................................... 33
B.8 PNP SETUP MENU ....................................................................................................................................... 36
B.9 SUPER I/O (SIO) SETUP MENU ...................................................................................................................... 37
B.10 FEATURES SETUP MENU ............................................................................................................................ 38
B.11 FIRMBASE SETUP MENU ............................................................................................................................ 39
B.12 MISCELLANEOUS SETUP MENU ................................................................................................................... 41
C. POWER AND ENVIRONMENTAL REQUIREMENTS ........................................................................................... 43
D. RTM REAR PLUG-IN I/O EXPANSION MODULE FOR THE CPU-111-10 ............................................................. 44
D.1 RTM VPX PIN-OUTS .................................................................................................................................... 44
D.2 CPU-111-10 REAR TRANSITION MODULE PIN-OUTS .......................................................................................... 46
D.3 REAR PANEL CONNECTOR PIN-OUTS ................................................................................................................ 46
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List of Figures
FIGURE 1: CPU-111-10 BLOCK DIAGRAM 4
FIGURE 2: PCI EXPRESS STRUCTURE 8
FIGURE 3: 10GB ETHERNET ARCHITECTURE 10
FIGURE 4: 10GB SWITCH BLOCK DIAGRAM 11
FIGURE 5: 82599 BLOCK DIAGRAM 11
FIGURE 6: VPX 10GBE I/O 12
FIGURE 7: CLOCKS 13
FIGURE 8: RESET STRUCTURE 14
FIGURE 9: SMBUS ARCHITECTURE 15
FIGURE 10: POWER GENERATION & DISTRIBUTION 16
FIGURE 11: REAR TRANSITION MODULE 17
FIGURE 12: CPU-111-10 CONNECTORS AND HEADERS 19
FIGURE 13: FRONT PANEL CONNECTORS AND INDICATORS 20
List of Tables
TABLE 1: VPX P0 CONNECTOR PIN-OUTS 21
TABLE 2: VPX P1 CONNECTOR PIN-OUTS 21
TABLE 3: VPX P2 CONNECTOR PIN-OUTS 22
TABLE 4: VPX P3 CONNECTOR PIN-OUTS 22
TABLE 5: VPX P4 CONNECTOR PIN-OUTS 23
TABLE 6: VPX P5 CONNECTOR PIN-OUTS 23
TABLE 7: VPX P6 CONNECTOR PIN-OUTS 24
TABLE 8: PCI-X MEZZANINE CARD CONNECTOR PIN-OUTS 24
TABLE 9: XMC CONNECTOR PIN-OUTS 25
TABLE 10: SFP+ CONNECTOR PIN-OUTS 25
TABLE 11: USB CONNECTOR PIN-OUT 26
TABLE 12: ENVIRONMENTAL REQUIREMENTS 43
TABLE 13: POWER REQUIREMENTS 43
TABLE 14: RTM VPX RP0 PIN-OUTS 44
TABLE 15: RTM VPX RP4 PIN-OUTS 44
TABLE 16: RTM VPX RP3 PIN-OUTS 45
TABLE 17: RTM VPX RP6 PIN-OUTS 45
TABLE 18: PMC I/O HEADER PIN-OUTS 46
TABLE 19: RTM REAR PANEL CONNECTOR PIN-OUTS 46
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Chapter 1 – Features
1. Features
The CPU-111-10 is a rugged, high-performance 6U VPX (VITA 46) Single Board Computer (SBC) featuring a
quad-core Intel L5408 Xeon processor and integrated 10 Gigabit Ethernet switch to support full-mesh backplane data
layer interconnectivity for up to eight SBCs integrated into a single chassis. Available in air cooled or conduction
cooled formats, the CPU-111-10 conforms to the OpenVPX (VITA 65) payload module profile MOD6-PAY-4F2T-
12.2.2.4 with four fat pipes (10 GBase-BX4) and two thin pipes (1000Base-T).
Providing unparalleled data processing capabilities in a single-slot 6U VPX form factor card with built-in 10 Gigabit
Ethernet fabric switching, the CPU-111-10 serves as an ideal open-architecture building-block for next-generation
Command, Control, Communications, Computers, Intelligence, Surveillance and Reconnaissance (C4ISR)
applications onboard (un)manned air / ground vehicles and shipboard platforms. Standard onboard I/O resources
includes up to 8x 10 Gigabit Ethernet, 2x 1 Gigabit Ethernet, 4x SATA, 2x USB 2.0, 1x RS-232/485, and 1x VGA
video ports. Dual XMC / PMC expansion module sites enable additional I/O expansion, including 10G XAUI lanes
from each XMC card to the 10G switched fabric.
Features of the CPU-111-10 include:
OPENVPX COMPATIBLE:
Rugged Single-Slot 6U Single Board Computer compatible with VITA 65 OpenVPX Payload Module Profile
MOD6-PAY-4F2T-12.2.2.4 (4x 10GBase-BX4 Fat Pipes and 2x 1000Base-T Thin Pipes)
HIGH PERFORMANCE x86 CPU:
4-Core Intel Xeon L5408 Processor @ 2.13 GHz with 4GB of DDR2 RAM
Linux, VxWorks, Windows, LynxOS, QNX, x86 RTOS Compatible
16 GB Bootable Solid State Flash Disk
10 GIGABIT SWITCH:
Integrated 10 Gigabit Ethernet Packet Processor Provides Full-Mesh Data Layer Switch Fabric for Up to 8 SBCs
without Use of Additional Switch Board (7 XAUI Ports to VPX Backplane, 1 SPF+ Port)
10 Gigabit XAUI Fabric Interfaces to Dual XMC Expansion Modules
Front Panel SFP+ 10 Gigabit Port Supporting CX4 Copper and Fiber Applications for Chassis-to-Chassis and
Rack-to-Rack Communications
I/O & EXPANSION:
Network: Up to 8x 10 Gigabit Ethernet, 2x 1 Gigabit Ethernet
Peripherals: 4x SATA, 2x USB 2.0, 1x RS-232/485, and 1x VGA Video
Dual XMC / PMC Mezzanine Expansion Sites
RUGGED DESIGN:
Designed to Meet MIL-STD-810 Environmental Conditions (Thermal, Shock, Vibration, Humidity, Altitude) and
Stresses of VPX Chassis Injection/Ejection
Air and Conduction Cooled Variants; Conductively Cooled Version Integrate Board Stiffeners and Wedge Locks
for High Shock and Vibration Immunity/Efficient Thermal Transfer.
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Chapter 2 – Related Documents
2. Related Documents
Listed below are documents that describe applicable standards, the processor and chipset, and the peripheral
components used on the CPU-111-10. Either download from the Internet or contact your local distributor for copies
of these documents. Many of the documents are confidential and may require execution of a non-disclosure
agreement between the supplier and CPU-110-10 user.
2.1 Standards
VITA 20-2001 - Conduction Cooled PMC, R1.1, February 2005
VITA 32-2003 - Processor PMC, R1.0, July 2003
VITA 42.0-2005 - XMC Switched Mezzanine Card Baseline Standard, D0.29, September 2005
VITA 42.3-2006 - XMC PCI Express Protocol Layer Standard, R1.0, June 2006
VITA 42.6-200x - XMC 10 Gigabit Ethernet 4-Lane Protocol Layer Standard, R0.911, January 2009
VITA 46.0-2007 - VPX Baseline Standard, R1.2, April 2008
VITA 46.4-2008 - PCI Express on VPX Fabric Connector, R6.00, March 2008
VITA 46.7-2008 - Ethernet on VPX Fabric Connector, R0.05, October 2008
VITA 46.9-2005 - PMC/XMC Pinout Mapping, R0.1, May 2005
VITA 46.21-2009 - Distributed Switching on VPX, R0.01, February 2009
IEEE P1386 - Common Mezzanine Card Family (CMC), D2.4a, March 2001
IEEE P1386.1 - CMC Physical and Environmental Layers, D2.4, January 2001
JEDEC 4.20.10 - PC2-6400/5300/4200/3200 Registered DIMM Design Specification, R3.98, January 2009
2.2 Product Specifications, Component Data Sheets, and Design Guides
CPU-111-10 Data Sheet, October 3, 2011
CPU-111-10 Schematic Diagram, R0.1, June 2009
CPU-111-10 Bill of Materials, R0.1, June 2009
Quad-Core Intel® Xeon® Processor 5400 Series Datasheet, Doc. No. 318589-005, August 2008
Quad-Core Intel® Xeon® Processor L5408 Series in Embedded Applications Thermal/Mechanical Design Guidelines, Doc.
No. 319133-001, April 2008
Intel® 5100 Memory Controller Hub Chipset Datasheet, Doc. No. 318378-003U, July 2008
Intel® 5100 Memory Controller Hub Chipset for Communications, Embedded, and Storage Applications
Thermal/Mechanical Design Guide, Doc. No. 318676-003US, July 2008
Intel® Xeon® Processor 5000 Sequence with Intel® 5100 Memory Controller Hub Chipset for Communications,
Embedded, and Storage Applications Platform Design Guide, Doc. No. 352108-2.3, April 2009
Intel® I/O Controller Hub 9 (ICH9) Family Datasheet, Doc. No. 316972-004, August 2008
Debug Port Design Guide for UP/DP Systems, Doc. No. 313373-001, June 2006
Intel® 82599 10 Gigabit Ethernet Controller Datasheet, R0.6, October 2008
Intel® 82571 & 82572 Gigabit Ethernet Controller Datasheet, R2.0, December 2006
82571EB/82572EI Gigabit Ethernet Controller Design Guide, Doc. No. 315337-002, February 2008
Micron MT47H256M8 DDR2 SDRAM Data Sheet, Doc. No. 09005aef824f87b6, Rev. B, September 2008
PLX Technology ExpressLane PEX 8624-AA 24-Lane/6-Port PCI Express Gen 2 Switch Data Book, Version 0.80,
November 2007
Tundra Tsi384 PCIe-to-PCI/X Bridge User Manual, Doc. No. 80E1000_MA001_08, July 2008
Tundra Tsi384 Board Design Guidelines, Doc. No. 80E1000_AN004_04, July 2008
Fulcrum Microsystems FocalPoint FM4000 24-Port 10G Ethernet Switch Datasheet, R2.1, May 2009
Fulcrum Microsystems FocalPoint FM4212/FM3212 12-Port 10G Ethernet Switch Datasheet Addendum, R1.1, March 2008
Netlogic Puma AEL2005 10Gbps SFP+ Transceiver Data Sheet, R1.2, December 2007
Silicon Motion SM750 LynxExpress Mobile Multimedia Companion Chip Data Sheet, R0.1, June 12, 2009
Silicon Motion SM2240 Serial ATA to IDE Bridge Data Sheet, R0.3, November 26, 2008
Silego SLG505YC264B Clock Synthesizer Data Sheet, Doc. No. 000-0084505B-10, R1.0, April 2008
IDT ICS9DB403D Quad Differential Clock Buffer Data Sheet, Rev. J, February 2009
Intersil ISL6313B Two-Phase Buck PWM DCDC Controller Data Sheet, Doc. No. FN6809.0, November 2008
Linear Technology LTM4616 Dual 8A Low-Vin DC/DC Module Data Sheet, Doc. No. LT 1108, Rev. A, 2008
Lattice Semiconductor ispPAC-POWR1220AT8 Power Supply Monitor/Sequencer/Controller Data Sheet, Doc. No.
DS1015, June 2008
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Chapter 3 – Hardware Description
SATA x1
Intel
L5408
Quad-Core
Xeon
Processor
Intel
5100
MCH
2GB
DDR2
SDRAM
2GB
DDR2
SDRAM
DDR2 - 1066
DDR2 - 1066
1066/1333MHz
FSB
Intel
ICH9R
ESI
PCIe x8
SATA x
4
USB 2.0 x2
16Mbit
FWH
RS232/RS485 Console
IDP-XDP
ispPOWR
1220A
Power Monitor
and
Sequencer
CK505
Clock
Generator
PCIe x8
PCIe x
8
16Mbit
SPI
SPI Bus
Link Port “A”
Link Port “B”
Link Port “C”
XMC
J15
XMC
J25
PLX
PEX8624
Gen2
6-Port
PCIe
Switch
Tsi384
PCIe-PCIX
Bridge
PCIe x4
PCIe x4
Tsi384
PCIe-PCIX
Bridge
PMC
J11-J13
PCI-X
PCI-X
PMC
J21-J23
Link Port “D”
Link Port “E”
64-Bit/133MHz
64-Bit/133MHz
Fulcrum Micro
FM3224
24-Port
10GigE
Switch
PMC
J14
PMC
J24
Single Ended x64
Single Ended x64
Differential Signaling x12
Link Port “F”
VPX
P4
VPX
P3
VPX
P6
VPX
P1
FABRIC
VITA46.21
(Legacy PCI/PCI-X)
VPX I/O
2GB/Sec
2GB/Sec
4GB/Sec
4GB/Sec
8GB/Sec
(Legacy PCI/PCI-X)
Link Port “G”
MDI x2
4GB/Sec
300MB/Sec x4
1.06GB/Sec
1.06GB/Sec
8.5GB/Sec
5.3GB/Sec
5.3GB/Sec
2GB/Sec
2.5MB/Sec
60MB/Sec x4
XAUI[6]
Intel 82599EB
Dual 10GigE
(Niantic)
XAUI[9]
XAUI[10]
10GigE x2
XAUI[0]
XAUI[8]
10GigE x1
1GigE x2
Dual PMC/XMC Sites
2GB/Sec
SFP+
FRONT PANEL
COPPER/FIBER
INTERFACE
1.25GB/Sec x2
125MB/Sec x2
1.25GB/Sec x1
10GigE x1
1.25GB/Sec x1
XAUI[11]SFI
Gen2 PCIe x8
P[0:5]
P[0:4]
STN[0] P[0]
STN[1] P[5] STN[2] P[9] STN[2] P[8]
PE6
PE7
PE4
PE5
PE2
PE3
PE0
P[0]P[1]
P[19]
P[13]
P[7]
P[20]
P[14]
XAUI[1]
XAUI[2]
XAUI[3]
10GigE x4 1.25GB/Sec x4
P[12]
P[8]
P[4]
P[23]
RX[0:3]/TX[0:3]
125MB/Sec x2
1GigE x2
SMBus
MDIO
XMC
J16
XMC
J26
XAUI[4]
P[11]
10GigE x4 1.25GB/Sec x4
Intel
82571EB
Dual 1GigE
1000BASE-KX x2
Serial
EEP
Netlogic
AEL2005
XAUI to SFI
PHY
LPC BUS
CP2103 USB
To UART Cntlr
60MB/Sec
P[5]
USB 2.0 x1
SM2240
SATA to Flash
Controller
FLASH BUS
20MB/Sec
300MB/Sec x1
Differential Signaling x12
3.125Gbit/Sec x12 Pairs
RX[0:3]/TX[0:3]
RX[0:3]/TX[0:3]
RX[0:3]/TX[0:3]
RX[0:3]/TX[0:3]
RX[0:3]/TX[0:3]
RX[0:3]/TX[0:3]
RX[0:3]/TX[0:3]
RX[0:3]/TX[0:3]
MDIO
I2C BUS
Serial
EEP
VPX
P2
XAUI[5] RX[0:3]/TX[0:3]
VPX
P5
XAUI[7] RX[0:3]/TX[0:3]
P[24]
3.125Gbit/Sec x12 Pairs
P[3]
IDP-XDP
SM750 VGA
Controller
VGAPCIe x1
500MB/Sec
Link Port “F”
PCIe x4
16GByte
NAND
Flash
Dual GigE
Magnetics
1000BASE-T x2
1GigE x2
125MB/Sec x2
OpenVPX
MOD6-PAY-4F2T-12.2.2-4
10GBASE-BX4
10GBASE-BX4
10GBASE-BX4
10GBASE-BX4
10GBASE-BX4
10GBASE-BX4
10GBASE-BX4
3. Hardware Description
3.1 Overview and Specifications
The block diagram of the CPU-111-10 is shown below. The sections that follow describe the major functional blocks
of the CPU-111-10.
Figure 1: CPU-111-10 Block Diagram
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Chapter 3 – Hardware Description
Specifications
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Chapter 3 – Hardware Description
3.2 Processing Architecture
3.2.1 Processor
The CPU-111-10 supports a 2.13GHz 4-Core Xeon L5408 Processor with 32KB data and 32KB of instruction
cache per core and 12MB of L2 shared cache. Processor features include:
One Intel quad-core L5408 Xeon Processor running at 2.13 GHz
32KB L1 Instruction and 32KB L1 Data Cache per core
12MB L2 Cache (shared)
1066/1333 MHz Front Side Bus supporting 8.5 GByte/Sec
transfer rates
3.2.2 Memory Controller Hub and DDR2 SDRAM
The Intel® 5100 Memory Controller Hub (MCH) provides dual memory controllers and 24 lanes of PCI Express
expansion (all of which are implemented on the CPU-111-10) for high-speed connectivity to dual XMC sites (8 lanes
each) and a PLX PEX8624PCIe Switch (8 lanes) for further PCI Express distribution. The MCH supports up to 4
GBytes of DDR2 SDRAM running at up to 1066 MHz double data rate speeds. MCH features include:
Intel 5100 MCH with 1066/1333 MHz Front Side Bus
4GB DDR2 ECC SDRAM at 533/667 MHz (1066 MHz DDR)
Two x8 PCI Express Ports to XMC Sites
One x8 PCI Express Port to PEX8624 Gen 2 PCIe Switch
ESI Bus to ICH9R I/O Controller Hub
3.2.3 I/O Controller Hub
The Intel® ICH9R I/O Controller Hub (ICH) chipset provides basic I/O, and standard PC system resources including
graphics, the real time clock, NV-RAM, timers, thermal management, and interrupt management. Features include:
Four Serial ATA Ports to VPX P4 Connector
Four USB Ports to VPX P4 Connector
LPC Bus to 16Mbit Firmware Hub
16Mbit SPI Flash
RS232/RS485 Serial Communications to VPX P4 Connector
x1 PCIe Interface supports SM750 VGA Controller
Real-time clock with 256 bytes of battery-backed RAM
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Chapter 3 – Hardware Description
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Chapter 3 – Hardware Description
Intel 5100
MCH
Intel ICH9R
IOH
PLX
PEX8624
PCIe
Switch
XMC
J15
XMC
J25
IDT
Tsi384
IDT
Tsi384
Intel
82599
Intel
82571
Silicon Motion
SM750 VGA
PE0 - x8 PCIe
PE1 - x8 PCIe
PE2 - x8 PCIe
PE3 – x4 PCIe
PE4 – x4 PCIe
PE5 - x8 PCIe
PE6 – x4 PCIe
PE7 – x1 PCIe
ESI
Bus
3.3 PCI Express Architecture
The PCI Express (PCIe) structure is shown below. All PCIe links operate at Gen1 speeds. The CPU-111-10 does
not support XMC based root complexes, only end-points.
The MCH provides 24 lanes of Gen1 PCIe and acts as the root complex. This is divided into three x8 ports. Two x8
ports connect to the XMC sites. The third x8 port connects to a PLX PEX8624 24-port Switch. This switch "fans
out" the MCH PCIe further as two x4 PCIe links to two IDT Tsi384 PCIe to PCI-X Bridges, providing a PCI-X
interface for each PMC site. The switch also supports a x8 link to an Intel 82599 Dual 10Gb Ethernet Controller,
providing a high-speed connection in the on-board 10GB Ethernet switch fabric.
The ICH9R has two PCIe ports. One x4 port is connected to an Intel 82571 Dual 1Gb Ethernet Controller to
support 1000BASE-T backplane control plane I/O. The remaining x1 PCIe port connects to a Silicon Motion
SM750 Graphics Controller.
3.3.1 Dual XMC Sites
Each XMC Site can support a x8 Gen1 PCIe endpoint per VITA42.3 using connectors J15 and J25. XMC based
root complexes are not supported on the CPU-111-10.
3.3.2 PLX PEX8624 PCIe Switch
The PEX8624 is a 6-port, 24-lane PCI Express switch configured as four ports. It has integrated low power SerDes
on all lanes and supports a fully non-blocking switch architecture. Its cut-thru packet latency is less than 160nSec
between symmetric ports (x8 and x8). The maximum data payload size is 2048 bytes.
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC – User’s Manual 8
Figure 2: PCI Express Structure
Page 14
Chapter 3 – Hardware Description
3.3.2 IDT Tsi384 PCIe to PCI-X Bridges for PMC Support
The IDT Tsi384 is a high-performance bus bridge that efficiently connects the x4 PCIe link from the PEX8624 to a
64-bit 133MHz PCI-X bus. One Tsi384 is used per PMC site to maximize PCI-X transfer rates. The Tsi384's only
support 3.3V PCI-X I/O signaling.
3.3.3 Intel 82599 Dual 10Gb Ethernet Controller
The Intel 82599 10 Gigabit Ethernet Controller is a single component with two fully integrated 10Gbit Ethernet MAC
and XAUI ports. Each port can support KX4/KX (802.3ap*) interfaces and contains a SerDes for backward
compatibility with gigabit backplanes. The architecture is designed for low-latency data handling and provides
superior DMA transfer-rate performance. The 82599 also supports the IEEE 1588 precision time protocol (PTP) by
time stamping in-coming and out-going data packets.
3.3.4 Intel 82571 Dual 1Gb Ethernet Controller
The Intel 82571 Gigabit Ethernet Controller is a single component containing two fully integrated Gigabit Ethernet
Media Access Controllers and physical layer ports. Both ports contain a SerDes to support Gigabit backplane
applications. The 82571 provides high performance and low memory latency using a x4 PCI Express link to the
ICH9R I/O Hub.
Complies with 1Gb/Sec Ethernet/802.3ap
x4 PCI Express interface to ICH9R
MDII or SERDES interface to backplane
4-Wire SPI EEPROM Interface
3.3.5 Silicon Motion SM750 Graphics Controller
The SM750 is a PCI Express 2D multimedia mobile display controller device, packaged in a 265-pin BGA. Designed
to complement needs for the embedded industry, it provides video and 2D capability. It supports a wide variety of
I/O, including an analog RGB, two Zoom Video interfaces, and Pulse Width Modulation (PWM).
The 2D engine includes a front-end color space conversion with 4:1 and 1:8 scaling support. The video engine
supports two different video outputs (Dual Monitor), at 8-bit, 16-bit, or 32-bit per pixel and a 3-color hardware
cursor per video output.
Connects to ICH9R via x1 PCI Express Interface
16MByte Internal DDR SDRAM Video Memory
2D Graphics Accelerator
DMA Controller
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Page 15
Chapter 3 – Hardware Description
FULCRUM
FM3224
10GigE
24-Port
Switch
XMC
J16
XMC
J26
82599
NETLOGIC
AEL2005
VPX
P1
VPX
P2
VPX
P5
VPX
P4
SFP+
Port 1
Port 2
Port 3
Port 4
Port 7
Port 8
Port 11
Port 12
Port 13
Port 14
Port 20
Port 23
Port 24
Port 19
XA0
XA1
XA2
XA3
XA4
XA5
XA6
XA7
XA8
XA9
XA10
XA11
XA12
XA13
CROSSOVER
3.4 10 Gigabit Ethernet Architecture
The CPU-111-10 utilizes 10Gb Ethernet (10GbE) to provide high-speed interconnection paths between the CPU,
both XMC sites, the backplane, and a front panel SFP+ module. The 10GbE architecture is shown below.
3.4.1 Fulcrum FM3224 Switch
The FM3224 10GbE Switch is the heart of the CPU-111-10 SBC. Using 10Gb Ethernet, it connects the backplane to
the CPU, XMC Modules, and front panel SFP+ Fiber Optic I/O modules (not included with the CPU-111-10).
The FM3224 is a fully integrated single-chip wire-speed 10G Ethernet switch. In addition to enhanced layer-2
functionality, the FM3224 layer-3 capabilities include advanced classification, extensive congestion management, and
improved switch management flexibility.
Features of the FM3224 include:
300nS Latency
Advanced Policy Engine
Switch Virtualization and Scaling
Port and MAC Based Security
In-band Switch Management
Provides Full-Mesh connectivity between up to eight VPQ Node Boards
Support for Front Panel SFP+ Connector for Copper or Fiber Optic cables (Configuration
dependent)
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC – User’s Manual 10
Figure 3: 10Gb Ethernet Architecture
Page 16
Chapter 3 – Hardware Description
Figure 4: 10Gb Switch Block Diagram
3.4.2 Intel 82599 Dual 10GB Ethernet
The 82599 provides a high-speed CPU path into the switch fabric for both data and switch management . The
interface to the switch consists of dual-channel XAUI (IEEE 802.3ae). The 82599 connects via x8 Gen2 PCIe to the
PEX8624 PCIe switch and from there to the CPU. As previously mentioned, the 82599 also supports IEEE 1588
precision time protocol (PTP) by time stamping in-coming and out-going data packets.
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC – User’s Manual 11
Figure 5: 82599 Block Diagram
Page 17
10GbE Port 23
KEY
KEY
SE
P0/J0
S
E
Data Plane
4 Fat Pipes
(4) 10GBASE-KX4
P2
OpenVPX Profile
MOD6-PAY-4F2T-12.2.2-5
Control Plane
Two Thin Pipes
(2) 1000BASE-T
10GbE Port 12
10GbE Port 8
S
E
KEY
S
E
P3
S
E
P4
S
E
P5
S
E
P6
User Defined
User Defined
User Defined
User Defined
User Defined
Color
Code
10GbE Port 14
10GbE Port 20
P1
Control Plane
Utility Plane
OpenVPX
Data Plane
User Defined
User Defined
Data Plane
PMC/XMC I/O
10GbE Port 4
10GbE Port 24
Chapter 3 – Hardware Description
3.4.3 SFP+ Interface (AEL2009)
The AEL2005 is a bidirectional single-channel 10 Gigabit Ethernet transceiver containing integrated EDC (Electronic
Dispersion Compensation) circuits targeted for 10GBASE-LRM optical modules and 10Gbps SFP+ applications.
The SFP+ connector is located on the CPU-111-10 front panel.
3.4.4 VPX 10Gb Ethernet I/O
Seven ports from the FM3224 10GbE switch are connected to the VPX backplane. The CPU-111-10 complies with
the VITA 46 OpenVPX standard for profile MOD6-PAY-4F2T-12.2.2-5. This profile covers the four 10GbE
channels on VPX connector P1. The remaining three 10GbE channels connect to P2, P4, and P5.
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC – User’s Manual 12
Figure 6: VPX 10GbE I/O
Page 18
Chapter 3 – Hardware Description
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
CK505
CLOCK
GENERATOR
CPU_ITP
MCH_ITP
DB400
PEX8624
Tsi384 #1
Tsi384 #2
82599
XMC #1
XMC #2
SM750
ICH9R
LPC HDR
FWH
FM3224
XPD0
CPU0
MCH
CLK
BFR
DDR REG
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
CLK
BFR
DDR REG
312.5
MHZ
OSC
125
MHZ
OSC
CLK
BFR
CLK
BFR
FM3224
SRC8
CPU_0
CPU_1
100MHz
100MHz
100MHz
100MHz
100MHz
100MHz
100MHz
100MHz
100MHz
100MHz
100MHz
100MHz
100MHz
48MHz
33MHz
14MHz
33MHz
33MHz
33MHz
33MHz
33MHz
100MHz
100MHz
125MHz
312.5MHz
SRC0
SRC1
SRC3
SRC4
SRC6
SRC7
SRC5
SRC9
SRC11
SRC2
82571
100MHz
SRC10
USB
PCI0
REF0
PCI1
PCI2
PCI3
PCI4
PCI5
3.4.5 XMC 10GbE I/O
Each XMC site supports one 10GbE channel to provide a high-speed data path into the 10GbE switch fabric.
3.5 VPX General Purpose I/O
The CPU-111-10 provides general purpose I/O via VPX connector P4. This I/O can be connected to a rear transition
module or can be terminated on the backplane. The I/O consists of (4) SATA ports, (4) USB ports, (1) LPC bus, (1)
RS232/RS485 Serial Communications Port, (2) 1GbE SERDES channels, and (2) 1000BASE-T 1GbE ports.
3.6 Clocking
An IDT ICS9LPR501 CK505 Clock Synthesizer generates the majority of clocks used on the CPU-111-10. It
generates 100MHz differential clocks used by the CPU and PCIe peripherals. It also generates 48MHz, 33MHz, and
14MHz clocks used throughout the CPU-111-10. Clocks for DDR SDRAM are generated by the MCH. Separate
312.5MHz and 125MHz oscillators provide clocks to the FM3224 10GbE Switch.
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC – User’s Manual 13
Figure 7: Clocks
Page 19
Chapter 3 – Hardware Description
PEX8624
Tsi384 #1
Tsi384 #2
82599
XMC #1
XMC #2
SM750
CPU
LPC HDR
FWH
FM3224
AEL2005
82571
SSD
DDR REG
MCH_ITP
CPU_ITP
DDR REG
MCH
PMC #1
PMC #2
ICH9R
ispPOWR
1220A
CPU CORE
SUPPLY
VPX P1
VPX P0
DUAL
DBNCR
FET
SWITCH
SYSCON#
BP_SYSRST#
RESET
SWITCH
VRM_PWRGD
BP_SYSRST#
PB_SYSRST#
ICH_CPU_PWRGD
PLTRST#
PLTRST1#
PLTRST2#
RSMRST#
SYS_PWRGD
SYS_PWRGD_3V3
CPU_PWRGD
ICH_PWRBTN#
PLTRST#
CPURST#
PCI_RST1#
PCI_RST2#
3.7 Reset Structure
A block diagram of the CPU-111-10 reset structure is shown below. The ispPOWR1220A provides reset glue logic
for the board. The backplane system reset (BP_SYSRST#) is an input when the CPU-111-10 is installed in a
peripheral slot and an output when installed in the system controller slot.
When all non-core supplies are up and stable, the ICH9R release the platform reset, or PLTRST#. The 1220A
buffers this reset and distributes it throughout the board as PLTRST1# and PLTRST2#. When PLTRST# is released
and the CPU core supply is stable, the CPU reset is released and the board boots up.
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC – User’s Manual 14
Figure 8: Reset Structure
Page 20
Chapter 3 – Hardware Description
PEX8624
PECI MON
DUAL T.S.
82599
XMC #1
XMC #2
ispPOWR1220A
I2C BUS
MULTIPLEXER
VPX RTM
CK505 CLK
x4 MAX7500 T.S.
DB400
82571
SFP+
I2C BUS EXP
XDP
DEBUG
ICH9R
FM3224
MCH
DDR2 SPD
DDR2 SPD
ICH_SMB
SMB_B
SMB_A
DDR2_SMB
FM_SMB
3.8 SMBus Architecture
The CPU-111-10 utilizes an SMBus to support inter-chip communications. This can range from management
functionality, e.g. reading temperature sensors, to setting up application specific operational conditions in the various
peripheral components. The SMBus runs at a maximum speed of 100KHz.
The ICH9R SMBus connects to the MCH and an I2C Bus Multiplexer, where the bus is then distributed around the
board. A separate SMBus connects the ICH9R to the FM3224 10GbE Switch to support initialization and out-ofband switch management.
SMB_A is connected to the CK505 Clock Generator, the DB400 Clock Buffer, the ispPOWR1220A power
monitor/sequencer, various Temperature monitoring devices, and an I2C bus expander.
Figure 9: SMBus Architecture
The I2C bus expander provides GPIO for reading the board geographic address, system controller status, and the
VPX backplane non-volatile memory read-only (NVMRO) status.
SMB_B is connected to the PEX8624 PCIe switch, the 82599 Dual 10GbE controller, 82571 dual 1GbE controller,
both XMC sites, the front panel SFP+ connector, and to a rear transition module via the VPX backplane.
The MCH provides one SMBus port which connects to two serial presence detect (SPD) EEPROM's containing
memory initialization parameters.
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC – User’s Manual 15
Page 21
Chapter 3 – Hardware Description
VPX
P0
LTM4616
LTM4616
LTM4616
LTM4616
LTM4616
LTM4616
½ LTM4616
½ LTM4616
ispPOWR
1220A
POWER
MONITOR
AND
SEQUENCER
ISL6314
FET SWITCH
FET SWITCH
LTC3693
V3_3_EP
V1_8
V1_5
V1_2
P_VTT
V1_05
V0_9
VCORE
V5_0
V3_3
V12_N
V12_P
V12_P
V5_0_EP
V1_8
V1_5
V1_2
P_VTT
V1_05
V0_9
VCORE
V3_3
V5_0_EP
V5_0
V12_P
V1_8_EN
V1_5_EN
V1_2_EN
V1_1_EN
V1_05_EN
V0_9_EN
VCORE_EN
V3_3_EP
V5_0_EN
V3_3_EN
VS1, VS2
VS3
3.9 Board Power
There are 11 major supply rails on the CPU-111-10. A block diagram of the power supply architecture is shown
below. The VPX backplane provides +12V and +5V supplies. The majority of the on-board supply rails are
generated by Linear Technology LTM4616 16A MicroModules. A discrete DC-DC converter controlled by an
Intersil ISL6314 provides the CPU core supply. Two switching FET's control backend 3.3 and 5V power. -12V is
generated by an LTC3693 1A regulator and is only used by the dual PMC sites. Power monitoring and sequencing is
performed by a programmable Lattice ispPOWR1220A.
For input power requirements please refer to Appendix C.
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC – User’s Manual 16
Figure 10: Power Generation & Distribution
Page 22
Chapter 3 – Hardware Description
SFP+
CX4 COPPER/FIBER
INTERFACE
Netlogic
AEL2005
XAUI to SFI
PHY
POL
USB1
USB0
ETH1ETH0
SFP+
eSATA1
eSATA2
eSATA3
eSATA4
RS232/RS485
VGA
POL
CPU-111-10 RTM
RS485 ENABLED
RP0RP3RP4RP6
SIO
VGA
RJ45 RJ45
PS2
RS232/485
U
S
B
U
S
B
Dual
eSATA
Dual
eSATA
PS2
J1
J3
J2
J4
J6
3.10 Rear Transition Module
The CPU-111-10 Rear Transition Module (RTM) provides I/O support for the CPU-111-10 SBC. This "Module
Specific I/O" capability of the CPU-111-10 provides rear chassis I/O for a SFP+ CX4 Copper/Fiber interface port,
Four External SATA (eSATA) ports, Two USB ports, dual 1Gb Ethernet ports, a RS232/485 Console port, and a
VGA port.
Four 2mm headers are provided to support CPU-111-10 PMC Module I/O. J1 and J3 terminate the signals derived
from PMC J14 and J2 and J4 terminate signals from J24. Please refer to Appendix D for RTM pin assignments.
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC – User’s Manual 17
Figure 11: Rear Transition Module
Page 23
Chapter 4 - Installation
4. Installation
*** UNDER CONSTRUCTION ***
The following sections cover the steps necessary to configure the CPU-111-10 and install it into a 6U VPX system
for single-slot operation. This chapter should be read in its entirety before proceeding with the installation.
4.1 Selectable Options
This section explains how to set up user configurable jumpers.
The CPU-111-10 is shipped in an antistatic bag. Be sure to observe proper handling procedures during the
configuration and installation process, to avoid damage due to electrostatic discharge (ESD).
The CPU-111-10 contains x jumpers...
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC – User’s Manual 18
Page 24
Chapter 4 - Installation
Figure 12: CPU-111-10 Connectors and Headers
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC – User’s Manual 19
Page 25
Chapter 4 - Installation
CPD-111-10
SFP+
PMC/XMC SITE 2PMC/XMC SITE 1
PWRONCPU
ERR
SSD
ACT
SYS
CON
RESET
USB
4.2 PCI Mezzanine Card (PMC) Installation
4.3 Front Panel Connectors and Reset Switch
The CPU-111-10 supports two PMC/XMC sites, an SFP+ connector, and an optional USB port. Front panel
indicators consist of a green power on LED, a red CPU Error LED, a yellow System Controller LED, and a yellow
solid state drive activity LED. A small hole is provided for access to recessed reset switch.
Figure 13: Front Panel Connectors and Indicators
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC – User’s Manual 20
Page 26
Appendix A - Connector Pinouts
Wafer Type Row G Row F Row E Row D Row C Row B Row A
Power Vs1 (12V) No Pad Vs2 (12V)1
Power No Pad2
Power Vs3 (5V) No Pad3
Single-ended GND GND SYSRESET# NVMRO4
Single-ended GAP# GA4# GND GND5
Single-ended GA3# GA2# GND GND GA1# GA0#6
Differential GND GND7
Differential GND GND GND8
Vs1 (12V)
Vs1 (12V)
Vs1 (12V)
Vs1 (12V)
Vs1 (12V)
Vs3 (5V) Vs3 (5V) Vs3 (5V) Vs3 (5V) Vs3 (5V)
Vs2 (12V)
Vs2 (12V)
Vs2 (12V)
Vs2 (12V)
Vs2 (12V)
VITA 46.0
Wafer Type Row G Row F Row E Row D Row C Row B Row A
1
2
3
4
5
6
Differential7
Differential8
9
10
11
12
13
14
Differential15
Differential16
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
GND
GND GND
SYS_CON# GND
GND GND
GND
GND GND
GND
GND
GND
GND
GND GND
GND
GND GND
GND
GND GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
XAIU2_RX0+
XAIU2_RX2+
XAIU2_RX0XAIU2_RX1+
XAIU2_RX2XAIU2_RX3+XAIU2_RX3-
XAIU2_RX1-
XAIU2_TX0+
XAIU2_TX2+
XAIU2_TX3+
XAIU2_TX0-
XAIU2_TX1+
XAIU2_TX2-
XAIU2_TX3-
XAIU2_TX1-
XAUI0_RX0+XAUI0_RX0-XAUI0_TX0+XAUI0_TX0-
XAUI0_RX1+XAUI0_RX1-XAUI0_TX1+XAUI0_TX1-
XAUI0_RX2+XAUI0_RX2-XAUI0_TX2+XAUI0_TX2-
XAUI0_RX3+XAUI0_RX3-XAUI0_TX3+XAUI0_TX3-
XAUI1_RX0+XAUI1_RX0-XAUI1_TX0+XAUI1_TX0-
XAUI1_RX1+XAIU1_RX1-XAIU1_TX1+XAIU1_TX1-
XAIU1_RX2+XAIU1_RX2-XAIU1_TX2+XAIU1_TX2-
XAIU1_RX3+XAIU1_RX3-XAIU1_TX3+XAIU1_TX3-
XAIU3_TX3-
XAIU3_TX1-
XAIU3_TX3+
XAIU3_TX0-
XAIU3_TX1+
XAIU3_TX2-
XAIU3_TX0+
XAIU3_TX2+
XAIU3_RX3-
XAIU3_RX1-
XAIU3_RX0XAIU3_RX1+
XAIU3_RX2XAIU3_RX3+
XAIU3_RX0+
XAIU3_RX2+
OpenVPX
MOD6-PAY-4F2T-12.2.2-4
Data Plane 1
(Fat Pipe)
10GBASE-BX4
Data Plane 2
(Fat Pipe)
10GBASE-BX4
Data Plane 3
(Fat Pipe)
10GBASE-BX4
Data Plane 4
(Fat Pipe)
10GBASE-BX4
VITA 46.7 r0.05
A. Connector Pin-outs
A.1 VPX Backplane Connectors
Table 1: VPX P0 Connector Pin-outs
Table 2: VPX P1 Connector Pin-outs
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC – User’s Manual 21
Page 27
Appendix A - Connector Pinouts
XAIU5_TX2- XAIU5_RX2-XAIU5_TX2+ XAIU5_RX2+
Wafer Type Row G Row F Row E Row D Row C Row B Row A
1
2
3
4
5
6
Differential7
Differential8
9
10
11
12
13
14
Differential15
Differential16
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
GND
J16-B5 (DP04-)
GND GND
GND
J16-B9 (DP08-)
GND GND
GND
GND GND
GND
GND
GND
J16-B17 (DP16-)
GND
GND
GND
GND
GND
GND
J16-D5 (DP05+)
J16-E7 (DP07-)
J16-D9 (DP09+)
J16-E15 (DP15-5)
J16-D17 (DP17+)
J16-E19 (DP19-)
GND
J16-E5 (DP05-)
GND
J16-E9 (DP09-)
GND
GND
J16-E17 (DP17-)
GND
J16-D7 (DP07+)
GND
GND
J16-D15 (DP15+)
GND
GND
GND
J16-D19 (DP19+)
J16-A7 (DP06+)
J16-A15 (DP14+)
J16-A19 (DP18+)
J16-A5 (DP04+)
J16-A9 (DP08+)
J16-A17 (DP16+)
J16-B7 (DP06-)
J16-B15 (DP14-)
J16-B19 (DP18-)
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
XAIU5_TX1- XAIU5_TX1+
XAIU5_TX0- XAIU5_TX0+
XAIU5_RX1-
XAIU5_RX0XAIU5_RX1+
XAIU5_RX0+
XAIU5_TX3- XAIU5_RX3-XAIU5_TX3+ XAIU5_RX3+
User Defined Data Plane 5
(Fat Pipe)
10GBASE-BX4
VITA 46.9 r0.23
XMC Site 1
X12d Pattern Map
Wafer Type Row G Row F Row E Row D Row C Row B Row A
J14-11
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
J14-3
J14-7
J14-11
J14-15
J14-5
J14-9
J14-13
J14-23
J14-27
J14-31
J14-21
J14-25
J14-29
J14-33 J14-35
J14-39
J14-43
J14-47
J14-37
J14-41
J14-45
J14-49 J14-51
J14-55
J14-59
J14-63
J14-53
J14-57
J14-61
RTM_MDIO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
RTM_MDC
SMB_B_DAT
SMB_B_CLK
RTM_PWREN
RTM_PWRGD
RTM_PBRST#
J14-2
J14-6
J14-10
J14-14
J14-18
J14-22
J14-26
J14-30
J14-34
J14-38
J14-42
J14-46
J14-50
J14-54
J14-58
J14-62
J14-4
J14-8
J14-12
J14-16
J14-20
J14-24
J14-28
J14-32
J14-36
J14-40
J14-44
J14-48
J14-52
J14-56
J14-60
J14-64
RS485_EN
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
J14-17 J14-19
PMC Site 1
VITA 46.9 r0.23
P64s Pattern Map
Table 3: VPX P2 Connector Pin-outs
Table 4: VPX P3 Connector Pin-outs
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC – User’s Manual 22
Page 28
Appendix A - Connector Pinouts
Wafer Type Row G Row F Row E Row D Row C Row B Row A
XAUI8_TX0+1
GND2
XAUI8_TX2+3
GND XAUI8_TX3- XAUI8_TX3+ GND4
VGA_SCL GND5
GND GND6
Differential GND7
Differential GND GND8
GND
GND
XAUI8_TX1-
XAUI8_TX0-
XAUI8_TX1+
GND XAUI8_TX2-
9
GND10
11
GND GND12
GND13
GND GND14
Differential GND15
Differential GND GND16
GND
GND
GND
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
XAUI8_RX0XAUI8_RX1+
XAUI8_RX2XAUI8_RX3+
XAUI8_RX0+
GND
XAUI8_RX2+
GND
GND
GND
GND
GND
GND
GND
XAUI8_RX3-
GND
GND
GND
XAUI8_RX1-
GND
GND
GND
GND
GNDVGA_R
VGA_B
VGA_G
VGA_HS
VGA_VS
MDXA_0- MDXA_0+MDXA_1+MDXA_1-
MDXA_2- MDXA_2+MDXA_3- MDXA_3+
SERDES0_TX+
SERDES1_TX-
SERDES0_TX-
SERDES1_TX+
SERDES0_RX-
SERDES1_RX+
SERDES0_RX+
SERDES1_RX-
SATA1_TX+SATA1_TX- SATA1_RX- SATA1_RX+
SATA2_TX- SATA2_TX+ SATA2_RX+SATA2_RX-
SATA3_TX- SATA3_TX+ SATA3_RX- SATA3_RX+
SATA4_RX- SATA4_RX+SATA4_TX- SATA4_TX+
USB0- USB0+
RS232_TX or
RS485_TX-
RS232_RTS or
RS485_TX+
USB1+USB1-
RS232_RX or
RS485_RX+
RS232_CTS or
RS485_RX-
MDXB_0- MDXB_0+MDXB_1+MDXB_1-
MDXB_2- MDXB_2+MDXB_3- MDXB_3+
VGA_SDA
Control Plane 1
(Thin Pipe)
1000
BASE-T
Control Plane 2
(Thin Pipe)
1000
BASE-T
OpenVPX
MOD6-PAY-4F2T-12.2.2-4
User Defined Data Plane 6
(Fat Pipe)
10GBASE-BX4
User Defined
User Defined
User Defined
(4) Serial ATA
(2) USB, Serial Comm
(2) Ultra Thin-Pipes
XAIU7_TX2- XAIU7_RX2-XAIU7_TX2+ XAIU7_RX2+
Wafer Type Row G Row F Row E Row D Row C Row B Row A
1
2
3
4
5
6
Differential7
Differential8
9
10
11
12
13
14
Differential15
Differential16
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
GND
J26-B5 (DP04-)
GND GND
GND
J26-B9 (DP08-)
GND GND
GND
GND GND
GND
GND
GND
J26-B17 (DP16-)
GND
GND
GND
GND
GND
GND
J26-D5 (DP05+)
J26-E7 (DP07-)
J26-D9 (DP09+)
J26-E15 (DP15-)
J26-D17 (DP17+)
J26-E19 (DP19-)
GND
J26-E5 (DP05-)
GND
J26-E9 (DP09-)
GND
GND
J26-E17 (DP17-)
GND
J26-D7 (DP07+)
GND
GND
J26-D15 (DP15+)
GND
GND
GND
J26-D19 (DP19+)
J26-A7 (DP06+)
J26-A15 (DP14+)
J26-A19 (DP18+)
J26-A5 (DP04+)
J26-A9 (DP08+)
J26-A17 (DP16+)
J26-B7 (DP06-)
J26-B15 (DP14-)
J26-B19 (DP18-)
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
XAIU7_TX1- XAIU7_TX1+
XAIU7_TX0- XAIU7_TX0+
XAIU7_RX1-
XAIU7_RX0XAIU7_RX1+
XAIU7_RX0+
XAIU7_TX3- XAIU7_RX3-XAIU7_TX3+ XAIU7_RX3+
XMC Site 2
VITA 46.9 r0.23
X12d Pattern Map
User Defined Data Plane 7
(Fat Pipe)
10GBASE-BX4
Table 5: VPX P4 Connector Pin-outs
Table 6: VPX P5 Connector Pin-outs
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC – User’s Manual 23
Page 29
Appendix A - Connector Pinouts
Wafer Type Row G Row F Row E Row D Row C Row B Row A
J24-11
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
J24-3
J24-7
J24-11
J24-15
J24-5
J24-9
J24-13
J24-23
J24-27
J24-31
J24-21
J24-25
J24-29
J24-33 J24-35
J24-39
J24-43
J24-47
J24-37
J24-41
J24-45
J24-49 J24-51
J24-55
J24-59
J24-63
J24-53
J24-57
J24-61
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
J24-2
J24-6
J24-10
J24-14
J24-18
J24-22
J24-26
J24-30
J24-34
J24-38
J24-42
J24-46
J24-50
J24-54
J24-58
J24-62
J24-4
J24-8
J24-12
J24-16
J24-20
J24-24
J24-28
J24-32
J24-36
J24-40
J24-44
J24-48
J24-52
J24-56
J24-60
J24-64
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
J24-17 J24-19
EEP_WP
PMC Site 2
VITA 46.9 r0.23
P64s Pattern Map
J11/J21
GND
INTB#
Pin
1 2
3 4
5 6
7 8
Pin
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
V12_N
INTA#
INTC#
INTD#
GND
CLK
V5_0
V3_3_AUX
GND
GND
REQ#
VIO
AD[28]
GNT#
V5_0
AD[31]
AD[27]
AD[25]
GND
AD[22]
AD[19]
GND
C/BE[3]#
AD[21]
V5_0
VIO
FRAME#
GND
DEVSEL#
AD[17]
GND
IRDY#
V5_0
GND
PAR
VIO
LOCK#
GND
AD[15]
AD[12]
AD[9]
GND
AD[6]
AD[11]
V5_0
C/BE[0]#
AD[5]
AD[4]
VIO
AD[2]
AD[0]
GND
AD[3]
AD[1]
V5_0
GND REQ64#
V12_P
Pin
1 2
3 4
5 6
7 8
Pin
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
J12/J22
GND
GND
RESET#
V3_3
V3_3
PME#
AD[30]
GND
GND
AD[29]
AD[26]
AD[24]
IDSEL
V3_3
AD[18]
V3_3
AD[23]
AD[20]
GND
AD[16]
GND
TRDY#
GND
C/BE[2]#
V3_3
STOP#
PERR#
V3_3
C/BE[1]#
AD[14]
GND
SERR#
GND
AD[13]
M66EN
AD[8]
AD[7]
V3_3
AD[10]
V3_3
GND
ACK64#
GND
V3_3
GND
J13/J23
GND
C/BE[6]#
Pin
1 2
3 4
5 6
7 8
Pin
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
GND
C/BE[7]#
C/BE[5]#
C/BE[4]#
VIO
AD[63]
AD[61]
GND
PAR64
AD[62]
GND
GND
AD[59]
AD[57]
VIO
AD[60]
AD[58]
GND
AD[56]
AD[55]
AD[53]
GND
AD[51]
AD[54]
GND
AD[52]
AD[50]
AD[49]
GND
AD[47]
AD[45]
GND
AD[48]
AD[46]
GND
VIO
AD[43]
AD[41]
GND
AD[44]
AD[42]
GND
AD[40]
AD[39]
AD[37]
GND
AD[35]
AD[38]
GND
AD[36]
AD[34]
AD[33]
VIO
GND
AD[32]
GND
GND
Px4_1
Px4_3
Px4_5
Pin
1 2
3 4
5 6
7 8
Pin
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
J14 (x=1) / J24 (x=2)
Px4_2
Px4_4
Px4_6
Px4_7
Px4_9
Px4_11
Px4_13
Px4_8
Px4_10
Px4_12
Px4_14
Px4_15 Px4_16
Px4_17
Px4_19
Px4_21
Px4_18
Px4_20
Px4_22
Px4_23
Px4_25
Px4_27
Px4_29
Px4_24
Px4_26
Px4_28
Px4_30
Px4_31 Px4_32
Px4_33
Px4_35
Px4_37
Px4_34
Px4_36
Px4_38
Px4_39
Px4_41
Px4_43
Px4_45
Px4_40
Px4_42
Px4_44
Px4_46
Px4_47 Px4_48
Px4_49
Px4_51
Px4_53
Px4_50
Px4_52
Px4_54
Px4_55
Px4_57
Px4_59
Px4_61
Px4_56
Px4_58
Px4_60
Px4_62
Px4_63 Px4_64
J11, J12, J21, J22 PMC CONNECTORS J13, J14, J23, J24 PMC CONNECTORS
Table 7: VPX P6 Connector Pin-outs
A.2 PCI-X Mezzanine Card Connectors
Table 8: PCI-X Mezzanine Card Connector Pin-outs
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC – User’s Manual 24
Page 30
Appendix A - Connector Pinouts
Row F Row E Row D Row C Row B Row A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PE0_TX1p
GND
PE0_TX3p
GND
PE0_TX5p
GND
PE0_TX7p
GND
GND
PE0_RX1p
GND
PE0_RX3p
GND
PE0_RX5p
GND
J15 – Primary Site 1 XMC Connector per VITA 42.3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PE0_TX0p
GND
PE0_TX2p
GND
PE0_TX4p
GND
PE0_TX6p
GND
GND
PE0_RX0p
GND
PE0_RX2p
GND
PE0_RX4p
GND
PE0_TX0n
GND
PE0_TX2n
GND
PE0_TX4n
GND
PE0_TX6n
GND
GND
PE0_RX0n
GND
PE0_RX2n
GND
PE0_RX4n
GND
PE0_TX1n
GND
PE0_TX3n
GND
PE0_TX5n
GND
PE0_TX7n
GND
GND
PE0_RX1n
GND
PE0_RX3n
GND
PE0_RX5n
GND
VPWR
RESET#
VPWR
VPWR
V12_P
VPWR
V12_N
VPWR
GA0 (‘b0)
VPWR
VPWR
SMB_B_DAT
VPWR
SMB_B_CLK
17
18
19
PE0_RX7p
GND
WAKE#
17
18
19
PE0_RX6p
GND
REFCLKp
PE0_RX6n
GND
REFCLKn
PE0_RX7n
GND
V3_3
V3_3
V3_3
V3_3
GA1 (‘b0)
V3_3
GA2 (‘b0)
NVMRO
Row F Row E Row D Row C Row B Row A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PE1_TX1p
GND
PE1_TX3p
GND
PE1_TX5p
GND
PE1_TX7p
GND
GND
PE1_RX1p
GND
PE1_RX3p
GND
PE1_RX5p
GND
J25 – Primary Site 2 XMC Connector per VITA 42.3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PE1_TX0p
GND
PE1_TX2p
GND
PE1_TX4p
GND
PE1_TX6p
GND
GND
PE1_RX0p
GND
PE1_RX2p
GND
PE1_RX4p
GND
PE1_TX0n
GND
PE1_TX2n
GND
PE1_TX4n
GND
PE1_TX6n
GND
GND
PE1_RX0n
GND
PE1_RX2n
GND
PE1_RX4n
GND
PE1_TX1n
GND
PE1_TX3n
GND
PE1_TX5n
GND
PE1_TX7n
GND
GND
PE1_RX1n
GND
PE1_RX3n
GND
PE1_RX5n
GND
VPWR
RESET#
VPWR
VPWR
V12_P
VPWR
V12_N
VPWR
GA0 (‘b1)
VPWR
VPWR
SMB_B_DAT
VPWR
SMB_B_CLK
17
18
19
PE1_RX7p
GND
WAKE#
17
18
19
PE1_RX6p
GND
REFCLKp
PE1_RX6n
GND
REFCLKn
PE1_RX7n
GND
V3_3
V3_3
V3_3
V3_3
GA1 (‘b0)
V3_3
GA2 (‘b0)
NVMRO
Row F Row E Row D Row C Row B Row A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
XA6_TX1p
GND
XA6_TX3p
GND
P26_DP05p
GND
P26_DP07p
GND
P26_DP09p
GND
XA6_RX1p
GND
XA6_RX3p
GND
P26_DP15p
GND
J26 – Secondary Site 2 XMC Connector
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
XA6_TX0p
GND
XA6_TX2p
GND
P26_DP04p
GND
P26_DP06p
GND
P26_DP08p
GND
XA6_RX0p
GND
XA6_RX2p
GND
P26_DP14p
GND
XA6_TX0n
GND
XA6_TX2n
GND
P26_DP04n
GND
P26_DP06n
GND
P26_DP08n
GND
XA6_RX0n
GND
XA6_RX2n
GND
P26_DP14n
GND
XA6_TX1n
GND
XA6_TX3n
GND
P26_DP05n
GND
P26_DP07n
GND
P26_DP09n
GND
XA6_RX1n
GND
XA6_RX3n
GND
P26_DP15n
GND
17
18
19
P26_DP17p
GND
P26_DP19p
17
18
19
P26_DP16p
GND
P26_DP18p
P26_DP16n
GND
P26_DP18n
P26_DP17n
GND
P26_DP19n
Row F Row E Row D Row C Row B Row A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
XA4_TX1p
GND
XA4_TX3p
GND
P16_DP05p
GND
P16_DP07p
GND
P16_DP09p
GND
XA4_RX1p
GND
XA4_RX3p
GND
P16_DP15p
GND
J16 – Secondary Site 1 XMC Connector
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
XA4_TX0p
GND
XA4_TX2p
GND
P16_DP04p
GND
P16_DP06p
GND
P16_DP08p
GND
XA4_RX0p
GND
XA4_RX2p
GND
P16_DP14p
GND
XA4_TX0n
GND
XA4_TX2n
GND
P16_DP04n
GND
P16_DP06n
GND
P16_DP08n
GND
XA4_RX0n
GND
XA4_RX2n
GND
P16_DP14n
GND
XA4_TX1n
GND
XA4_TX3n
GND
P16_DP05n
GND
P16_DP07n
GND
P16_DP09n
GND
XA4_RX1n
GND
XA4_RX3n
GND
P16_DP15n
GND
17
18
19
P16_DP17p
GND
P16_DP19p
17
18
19
P16_DP16p
GND
P16_DP18p
P16_DP16n
GND
P16_DP18n
P16_DP17n
GND
P16_DP19n
SignalPin
GND1
TX_FAULT2
TX_DISABLE3
SDA4
SCL5
MOD_DETECT6
7
RX_LOS8
SFP+ Connector
9
10 GND
SignalPin
GND
20
RD-
11
RD+
12
GND
13
3.3V
14
3.3V
15
GND
16
TD+
17
18
19 TD-
GND
1 10
1120
A.3 XMC connectors
Table 9: XMC Connector Pin-outs
A.4 SFP+ Pin-out
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC – User’s Manual 25
Table 10: SFP+ Connector Pin-outs
Page 31
Appendix A - Connector Pinouts
SignalPin
5V1
USB-2
USB+3
GND4
USB Connectors
14
A.5 Front Panel USB Pin-out
Table 11: USB Connector Pin-out
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC – User’s Manual 26
Page 32
Appendix B – BIOS & Setup
B. BIOS & Setup *** NEED INPUT FROM HUNG ***
The CPU-111-10 uses General Software’s Embedded BIOS with StrongFrame™ Technology, Rev 6.The BIOS is
configured with the System Setup Utility, accessible from the Preboot Menu. This photo shows the initial splash
screen that is displayed after powering up the system as the BIOS runs through the Power On Self Test (POST).
When your system is powered on, Embedded BIOS tests and initializes the hardware and programs the chipset and
other peripheral components.
To enter the Setup mode, please press the delete <Del> key on your keyboard after powering up your system, during
POST.
B.1 Redirecting to a Serial Port
Setup may be run from the main keyboard and video display or from a terminal emulator program running on a host
computer connected to the system through a serial cable. To use a serial port, connect a dumb terminal or a PC
running a terminal emulation utility like Hyperterminal to COM1 via a null modem. Next, set the communications
parameters of the host’s terminal program to 115Kbaud. Other parameters are 8-bit, no parity, and one stop bit. Do
not enable XON/XOFF or hardware flow control.
With this link set up, power on the system. Press ^C a few times on your dumb terminal or your PC as the system
boots. POST will redirect to the serial console, and after it has completed its early stages, it will start the preboot
menu.
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC – User’s Manual 27
Page 33
Appendix B – BIOS & Setup
Main
Display main system components and allow editing of date and time.
Exit
Save changes and exit, discard changes and exit, or restore factory default settings.
Boot
Configure boot actions and boot devices.
POST
Configure POST.
PnP
Configure Plug-n-Play for non-ACPI OSes.
SIO
Configure Super I/O devices such as serial ports and parallel ports.
Features
Enable and disable system BIOS features like ACPI, APM, PnP, MP, quick boot, and
the splash screen.
Firmbase
Configure Firmbase Technology and the features that use it, such as USB keyboard
and mouse support (commonly, USB HID), boot from USB (commonly, USB Boot),
and applications such as high availability, boot security (not user security, but chain-oftrust security), and network-based remote access.
Misc
Configure miscellaneous BIOS settings that do not fall into any other category.
Shadowing
Configure chipset shadow RAM regions.
Security
Configure which BIOS features require user authentication before they perform their
functions
CUI
Configure the layout and coloring of the Common User Interface (CUI) display engine
that supports preboot applications.
Chipset
Configure any chipset-specific parameters, such as memory, CPU, and bus timing, and
availability of chipset-specific features such as TFT support. Highly platform-specific
and entirely up to the OEM’s implementation.
UP key (also ^E)
Move the cursor to the line above, scrolling the window as necessary.
DOWN key (also ^X)
Move the cursor to the line below, scrolling the window as necessary.
LEFT key
Go back to the menu to the left of the currently-displayed menu in the menu bar.
RIGHT key
Go forward to the menu to the right of the currently-displayed menu in the menu bar.
PGUP key
Move the cursor up several lines (a full window’s worth), scrolling the window as
necessary.
PGDN key
Move the cursor down several lines (a full window’s worth), scrolling the window as
necessary.
HOME key
Move the cursor to the first configurable field in the current menu, scrolling the
window as necessary.
END key
Move the cursor to the last configurable field in the current menu, scrolling the
window as necessary.
ESC key
Exit the Setup system, discarding all changes(except date/time changes, which take
place on-the-fly.)
TAB key
Move the cursor down to the next configurable field.
Shift-TAB key (backtab)
Move the cursor up to the last configurable field.
+ key
Toggle an Enable/Disable field, or increase a numeric field’s value.
- key
Toggle an Enable/Disable field, or decrease a numeric field’s value.
SPACE key
Toggle an Enable/Disable field.
B.2 Setup Menus
The standard Embedded BIOS setup menus are described below in the order they generally appear in the menuing
system (Dynatem cannot vouch for support for all BIOS functions described in the subsequent sections):
B.3 Navigating Setup Menus and Fields
Navigation (moving your cursor around, selecting items, and changing them) is easy in theSetup system. The
following chart is a helpful user reference:
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC – User’s Manual 28
Page 34
Appendix B – BIOS & Setup
BKSP key
Reset an Enable/Disable or multiple-choice field, or back-up in numeric or string
fields.
Digits (0-9)
Used to enter numeric parameters.
Alphabetic (A-Z, a-z)
Used to enter text data on ASCII fields such as email addresses.
Special symbols
(!@#$%^&*_-+={}[], etc.)
Used to enter special text on ASCII fields that permit these characters.
BIOS Version
Indicates the major and minor core architecture versions (6.x, where x is a number from
0 to 999.)
The basic idea when using the Setup system is to navigate to the menus containing fields you want to review, and
change those fields as desired. When your settings are complete, navigate to the EXIT menu, and select “Save
Settings and Restart”. This causes the settings to be stored in nonvolatile memory in the system, and the system will
reboot so that POST can configure itself with the new settings.
After rebooting it may be desirable to reenter the Setup system as necessary to adjust settings as necessary.
Once the system boots, the Setup system cannot be entered; this is because the memory used by the BIOS
configuration manager is deallocated by the system BIOS, so that it can be used by the OS when it boots. To reenter
the Setup system after boot, simply reset the system or power off and power back on.
B.4 Main Setup Menu
The first menu always showing in the Setup system is the Main menu (unless disabled by the
OEM.) This menu is shown in Figure 3.1 below.
The Main menu provides a system summary about the BIOS, processor, system memory, date and time, and any
other items configured by the OEM. The BIOS information is obtained by Setup from the internal system BIOS build
itself; this information is useful when obtaining support for your system.
PLEASE CALL Dynatem at (800)543-2830 FOR BIOS SUPPORT; DO NOT CALL GENERAL SOFTWARE
DIRECTLY.
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Appendix B – BIOS & Setup
BIOS Build Date
Date in MM/DD/YY format on which Dynatem built the system BIOS binary file.
System BIOS Size
Size of BIOS exposed in low memory below the 1MB boundary. Commonly, 128KB
would mean that the BIOS is visible in the address space from E000:0000 to
F000:FFFF.
CPM/CSPM/BPM
Modules
Indicates the names of the key architectural modules used to create the system BIOS
binary file. The CPM module provides the CPU family support; the CSPM module
provides the northbridge support; and the BPM module provides the board-level
support.
The CPU information is normally obtained by querying the Processor Brand String in the CPU’s MSRs; the method
used to achieve this is beyond the scope of this document.
The system memory information does not describe physical RAM; rather it describes the RAM as configured,
subtracting RAM used for System Management Mode, Shadowing, Video buffers, and other uses. This provides
realistic values about how much memory is actually available to operating systems and applications.
The Real Time Clock fields are editable with keystrokes. To navigate through the MM/DD/YYYY and HH:MM:SS
fields, use the TAB and BACKTAB keys. The hours are normally specified in military time; thus 13 means 1pm, or
one hour after noon, whereas 01 means 1am, or one hour after midnight. When the cursor leaves RTC fields, they
either affect the battery-backed RTC right away, allowing the system to continue with your new settings, or
they revert back to old values if the new values are not valid entries.
B.5 Exit Setup Menu
The Exit menu provides methods for saving changes made in other menus, discarding changes,
or reloading the standard system settings. This menu is shown in Figure 3.2 below.
To select any of these options, position the cursor over the option and press the ENTER key.
Pressing the ESC key at any time within the Setup system is equivalent to requesting “Exit Setup
Without Saving Changes.”
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Appendix B – BIOS & Setup
“drive name” – The system BIOS may list the drive’s
name in a generic sense (i.e., “USB Hard Drive”) if
the drive has not been detected yet, or the drive’s
full manufacturing name and serial number (if
Boot from the MBR/PBR of the named BIOSaware IPL drive
(BAID). The drive may be Legacy Floppy, PATA, SATA,
Compact Flash, or a USB drive.
B.6 Boot Setup Menu
The Boot menu allows the system’s boot actions and boot devices to be configured. This menu is shown here:
The BBS portion of this menu lists the devices and activities to be performed in the order in which they appear in the
list. When the BIOS completes POST, it follows this list, attempting to process each item. Some items are drives,
such as an ATA/IDE drive, or a USB hard disk, or CDROM.
The ordering of the drives in the BBS list controls the BIOS in several ways. First, it is the list of drives that is
scanned and assigned BIOS unit numbers for DOS (for example 80h, 81h, 83h, and so on for hard drives). If a drive
on the list is not plugged in or working properly, the BIOS moves on to the next drive, skipping the inoperative one.
Second, once the drives in the list have been verified, POST attempts to boot from them in that order as well. Drives
without bootable partitions might be configured, but skipped over in the boot phase, so that other drives on the list
become candidates for booting the OS.
The BBS list also contains other boot actions, such as boot from network cards and PCI slots, as well as special
BIOS boot actions like “Boot EFI”, “Boot Windows CE”, or even “Boot Debugger”. When deciding what boot
action to do first and then next in succession, POST first scans all the drives in the list to verify they are present and
operating properly (as described earlier in this section) and then goes down the list and tries to perform the actions in
order. During this boot phase, if the list item is a drive, an attempt is made to boot from the boot record of that drive.
If the list item is a device like a network card or PCI slot, an attempt is made to boot from that device. If the list item
is a software item like “Boot Debugger”, then it performs that action, and when that action completes, it moves on to
the next item in the BBS list.
The table that follows lists the set of standard boot action items:
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Appendix B – BIOS & Setup
detected.)
IDE0/Primary Master Primary
Master PATA drive or SATA mapping by the chipset, routed
to the backplane via J5.
IDE1/Primary Slave
Primary Slave PATA drive or SATA mapping by the chipset,
routed to the backplane via J5.
IDE2/Secondary Master
Secondary Master PATA drive or SATA mapping by the
chipset, routed to on-baord CompactFlash
IDE CDROM
First detected IDE CDROM.
USB Floppy Drive
First detected USB floppy drive.
USB Hard Drive
First detected USB hard drive.
USB CDROM Drive
First detected USB CDROM.
Enter Board Information Browser
Invoke HTML Browser on 0.HTM in ROM.
Enter BIOS Setup Screen
Invoke System Setup Utility in ROM.
Enter BIOS Debugger
Invoke BIOS debugger in ROM.
Reboot System
Restart system.
Power Off System
Invoke S5 state, powering off system.
PCI Slot [n]
Boot from device in PCI Slot ‘n’.
Network
Boot from any network adapter.
SCSI
Boot from external SCSI device (on PMC/XMC card).
Boot EFI Binary
Boot EFI kernel from ROM or disk, depending on the EFI
source setting in the Features menu. If disk is selected, then
the BIOS searches all the configured disks in the system in the
order they appear in the BBS list, attempting to load
EFILDR.BIN from the root directory in the FAT file system
located on those drives.
Boot Windows CE Image
Boot Windows CE kernel from disk. The BIOS searches all
the configured disks in the system in the order they appear in
the BBS list, attempting to load NK.BIN from the root
directory in the FAT file system located on those drives.
Boot Graphical Desktop
Boot Firmbase GUI supporting graphical Firmbase
applications as well as booting DOS in a graphical window.
For applications requiring instant-on functionality even when
the OS is not available or is still loading.
The photograph above shows a common setup of the BBS list for desktop applications. In this example, the first boot
device is theWestern Digital IDE hard drive (WDC WD800JB-00JJC0) connected to the target as a Primary Master
IDE drive. The second boot device is the Secondary Master and this is the on-board CompactFlash. The third device
is a USB Hard Drive. A fourth boot device, “None”, is a placeholder that is simply used to add more entries in the
setup screen; “None” is not actually executed by POST as a boot action item.
In addition to the BBS boot device list, there are two more sections in the BOOT menu; namely, the Floppy Drive
Configuration and IDE Drive Configuration sections. Both of these sections tell the BIOS what kind of equipment is
connected to the motherboard but the floppy drive interface has not been implemented so please ignore this and leave
it as “Not Installed”. Similarly, the IDE Drive Configuration section describes the type of hard drive equipment that
is connected to the motherboard, including the cable type. IDE drives, or actually more properly Parallel ATA
(PATA) drives, are connected to the motherboard with a flat cable with either 40 or 80 wires running in parallel
(hence, Parallel ATA, as opposed to Serial ATA.) The 40-pin connector supports speeds up to UDMA2, whereas 80pin cables are needed for higher transfer rates to eliminate noise. The BIOS can be told what type of cable is
available, so that it knows whether higher transfer rates are allowed; or, it can be told to autodetect the cable type, in
which case the drive and the motherboard must both support the hardware protocol used to autodetect the drive’s
cable type.
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Appendix B – BIOS & Setup
Note: PATA cable autodetection sometimes fails with older drives, so 40-pin is the default, to ensure data integrity.
For higher performance, you should change this setting to 80-pin or AUTO if an 80-pin cable is installed.
B.7 POST Setup Menu
The POST menu is used to configure POST. This menu is shown in the following figure (scrolled down more so the
full set of options can be seen.) Be sure to review the Features menu, where additional items can be configured, such
as the Splash Screen and BIOS initiatives.
The figure below shows the same menu, scrolled down so that the remainder of its fields may be
viewed.
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Appendix B – BIOS & Setup
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Appendix B – BIOS & Setup
Low Memory Standard
Test
Enable basic memory confidence test, of memory below 1MB address boundary
(conventional memory, or memory normally used by DOS.)
Low Memory Exhaustive
Test
Enable exhaustive memory confidence test of memory below 1MB address boundary.
High Memory Standard
Test
Enable basic memory confidence test, of memory between 1MB and 4.2GB address
boundaries (extended memory.)
High Memory Exhaustive
Test
Enable exhaustive memory confidence test, of memory between 1MB and 4.2GB
address boundaries.
Huge Memory Standard
Test
Enable basic memory confidence test, of memory above 4.2GB address boundary
(available using PAE technology.)
Huge Memory Exhaustive
Test
Enable exhaustive memory confidence test, of memory above 4.2GB address
boundary.
Click During Memory Test
Enable/disable speaker click when testing each block.
Clear Memory During Test
Enable storing 0’s in all memory locations tested. Only necessary when some legacy
DOS programs are run, as they may rely on cleared memory to operate properly.
Pause on POST Errors
Enable pause when errors are detected during POST, so that the user can view the
error message and enter Setup or continue to boot the OS.
POST Display Messages
Enable display of text messages during POST. When disabled, POST is “quiet.”
POST Operator Prompt
Enable operator prompts if POST is configured to ask interactive questions of the
user about whether to load specific features; i.e., whether or not to load SMM.
POST Display PCI Devices
Enable display of PCI devices.
POST Display PnP Devices
Enable display of ISA PnP devices.
POST Debugger
Breakpoints
Enable processing of INT 3 (breakpoint) instructions embedded into option ROMs.
When enabled, if an INT 3 instruction is encountered, control is transferred to the
BIOS debugger, so that the option ROM can be debugged. When disabled, these
instructions perform no action.
POST Fast Reboot Cycle
Enable early reboot in POST, allowing service technician to verify that the hardware
can technician to verify that the hardware can reboot very quickly many times in
succession. Platform will continue to reboot after every boot until the system’s CMOS
is reset, as there is no way to enter Setup from this early point during POST.
POST Slow Reboot Cycle
Enable late reboot in POST, allowing service technician to cause the system to move
through POST and then reboot, causing POST to be reexecuted, over and over, until
Setup is reentered and this option is disabled. When left unattended, this is a
straightforward way of having POST exercise system memory and peripherals without
requiring a boot to a drive with an operating system installed.
POST Floppy Seek
Enable head seek on each floppy drive configured in the system. Used to recalibrate
the drive in some systems with older DOS operating systems.
POST Hard Disk Seek
Enable head seek on each hard drive configured in the system. This is a way of
extending the standard testing performed on each drive during POST, by requesting
that the drive actually move the head. Not available with all drives.
The following table describes the settings associated with the POST setup menu’s Memory Test section.
The following table describes the settings associated with the POST setup menu’s Error Control section:
The following table describes the settings associated with the POST setup menu’s POST User Interface section:
The following table describes the settings associated with the POST setup menu’s Debugging section:
The following table describes the settings associated with the POST setup menu’s Device Initialization section:
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Appendix B – BIOS & Setup
Plug-n-Play
Enable PnP feature. When disabled, a PnPaware OS will not find any PnP services in
the BIOS, and all other configuration parameters in the menu will be greyed out.
Enable to support legacy OSes like DOS, Windows95, Windows98, and WindowsNT.
Disable for operating systems like WindowsXP or Windows Vista, or for Linux
operating systems with ACPI support.
Plug-n-Play OS
Enable delay of configuration of PnP hardware and option ROMs. When enabled,
BIOS will NOT configure the devices, and instead defer assignment of resources,
such as DMA, I/O, memory, and IRQs, to the PnP OS. When disabled, the BIOS
performs conflict detection and resolution, and assigns resources for the OS. Disable
this parameter when running non-PnP OSes like DOS. Enable this parameter when
running PnP OSes like Windows95, Windows98, and WindowsNT.
IRQ0
Enable exclusive use of IRQ0 by PnP.
IRQ1
Enable exclusive use of IRQ1 by PnP.
IRQ2
Enable exclusive use of IRQ2 by PnP.
IRQ3
Enable exclusive use of IRQ3 by PnP.
IRQ4
Enable exclusive use of IRQ4 by PnP.
IRQ5
Enable exclusive use of IRQ5 by PnP.
IRQ6
Enable exclusive use of IRQ6 by PnP.
IRQ7
Enable exclusive use of IRQ7 by PnP.
IRQ8
Enable exclusive use of IRQ8 by PnP.
IRQ9
Enable exclusive use of IRQ9 by PnP.
B.8 PnP Setup Menu
The PnP menu is used to configure Plug-n-Play, a legacy BIOS initiative used to support operating systems such as
Windows95, Windows98, and WindowsNT. ACPI has largely replaced this feature; however, it is necessary for
platforms to support older operating systems.
The PnP menu consists of two sections; basic configuration that enables Plug-n-Play and identifies if a PnP should
perform configuration or let the OS do it; and then, another section that defines which system IRQs should be
reserved for PnP’s use, so that PCI doesn’t use them. The following table presents the fields in the PnP menu.
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Appendix B – BIOS & Setup
IRQ10
Enable exclusive use of IRQ10 by PnP.
IRQ11
Enable exclusive use of IRQ11 by PnP.
IRQ12
Enable exclusive use of IRQ12 by PnP.
IRQ13
Enable exclusive use of IRQ13 by PnP.
IRQ14
Enable exclusive use of IRQ14 by PnP.
IRQ15
Enable exclusive use of IRQ15 by PnP.
B.9 Super I/O (SIO) Setup Menu
The SIO menu is used to configure the LPC47B27x Super I/O device. The only implemented I/O on this chip are the
PS/2 mouse and keyboard and two 2-wire COM ports (COM3 & COM4). Basically this window is used to configure
COM3 & COM4 (though they are referred to as Serial Ports 1 & 2 in the SIO Setup Menu):
POST reads these settings in the menu shown above and programs the Super I/O part accordingly, enabling and
disabling devices as requested. The disabled devices are not further programmed, since they are actually disabled in
hardware. In the figure above, legacy I/O addresses and IRQs are as follows:
COM3 – I/O 3f8h, IRQ4.
COM4 – I/O 2f8h, IRQ3.
It should be noted that these are not the only possible addresses, but they are the ones that will ensure compatibility
with the most legacy software, especially early DOS programs that do not use BIOS to access the COM ports.
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Appendix B – BIOS & Setup
Quick Boot
Enable time-optimized POST, causing certain preconfigured OEM optimizations to be
made when the system boots. Depending on the system, Quick Boot can reach the
DOS prompt in as little as 85ms (milliseconds.)
Advanced Power
Management (APM)
Enable legacy power management, used by the system when an ACPI-aware operating
system is not running (during POST, such as when the system is running the preboot
environment, or while running DOS, Windows95, Windows98, or Linux kernels below
version 2.6.) Uses the SMM feature (see Firmbase) to operate properly.
ACPI
Enable ACPI system description and power management (ACPI replaces PnP and
APM.) Used with ACPI-aware OSes such as Linux kernels version 2.6 and above,
Windows XP, and Windows Vista. Commonly also uses the SMM feature (see
Firmbase) to operate properly.
POST Memory Manager
(PMM)
Enable memory allocation services for option ROMs, especially network cards running
PXE. Some option ROMs may use this interface incorrectly, causing system crashes.
Other PXE option ROMs may not run if PXE is not supported. Because of the state of
these option ROMs, the setting is provided as an option to the user.
SMBUS API
Enable INT 15h services that permit certain software to access devices on the system’s
SMBUS without having knowledge of the SMBUS controller itself.
System Management BIOS
(SMBIOS)
Enable System Management BIOS interface specification support, exposing
information about the type of hardware, including the chassis, motherboard layout,
type of CPU and DRAM sticks, to applications such as WfM, which runs on PXE in
the preboot environment.
Manufacturing Mode
Enable automatic entry into manufacturing mode when POST encounters a critical
error. Used in closed device settings such as smart phones that need access to docking
stations when they don’t boot. Leave disabled.
B.10 Features Setup Menu
The Features menu is used to configure the system BIOS’ major features, including Quick Boot, APM, ACPI, PMM,
SMBUS, SMBIOS, Manufacturing Mode, Splash Screen, Console Redirection, and others added by the OEM. This
figure shows a typical Features Setup menu.
The following table describes each setting in the Features menu :
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Appendix B – BIOS & Setup
Splash Screen
Enable graphical POST
Console Redirection
Configure the console redirection feature over a serial port. Automatic – causes
POST, the debugger, and the preboot environment to use the system’s first serial port
(COM1) when an RS232 cable is detected with DSR and CTS modem signals active,
indicating a terminal emulation program is likely to be attached to the other end of the
cable. Always – causes the BIOS to always use the serial port as the console, without
testing for the presence of the terminal emulation program. Never – causes the BIOS
to never invoke console redirection, but instead always use the main keyboard and
video display. If there is no keyboard or video display, the system operates headless.
EFI Source
Configure the location (ROM or disk) where the EFI boot action can find the
EFILDR.BIN image. An image may be merged with the system BIOS into the system
ROM, or it may be placed in the root directory of any bootable mass storage device.
Legacy USB
Enables BIOS support for USB keyboards and mice. Up to 8 USB keyboards and 8
USB mice may be supported at a time. Use of PS/2 keyboard and mouse concurrently
with USB devices is discouraged, as the legacy PS/2 keyboard controller cannot easily
separate simultaneous data streams from both device classes.
USB Boot
Enables BIOS support for accessing USB mass storage devices and emulating legacy
floppy, hard drive, and CDROM drive devices with them. Enable this option in order
for USB devices to be supported in the BBS device list(see the BOOT menu.)
EHCI/USB 2.0
Enables EHCI Firmbase Technology driver, allowing USB Boot feature to use high
B.11 Firmbase Setup Menu
The Firmbase menu configures the Firmbase Technology component of the system BIOS, including all of the features
enabled by it; i.e., legacy USB keyboard and mouse, boot from USB devices, and support of Firmbase applications
such as Boot Security, Platform Update Facility, and High Availability Monitor. This menu has several parts, with the
most basic user oriented feature options in the top section, and the more technical tuning parameters located in the
lower sections.
The following table presents the settings that enable high-level features enabled by Firmbase Technology:
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Appendix B – BIOS & Setup
speed transfers on USB 2.0 ports in the system.
Firmbase Disk I/O
Enables Firmbase Technology FAT file system driver, so that Firmbase applications
such as Boot Security, Platform Update Facility, and HA Monitor, as well as the HA
and TCB components of the kerne, have access to files residing on drives containing
FAT file systems. Also turn on this option if you wish to run Firmbase applications
from FAT file systems on either ATA or USB mass storage devices.
Firmware Application Suite
Enables Firmbase applications configured for the system by the OEM. Typically
includes Boot Security, Platform Update Facility, and High Availability Monitor.
Firmbase User Registry
Not used.
Firmbase User Shell
Enables Firmbase Technology command line interpreter, a multi-user command shell
with DOS-like and Unix-like command structure;can be used to start Firmbase
applications written with the Firmbase SDK, a General Software product.
Firmbase Technology
Enables Firmbase Technology as a whole, the industry’s most comprehensive and
fullfeatured System Management Mode (SMM) operating environment. Some
hardware platforms require Firmbase Technology to run, as they may use it to
virtualize hardware such as virtual video and audio PCI devices. Some BIOS features,
such as ACPI and APM, may require Firmbase Technology to operate
Firmbase Debug Log
Specifies the device used by Firmbase Technology components (kernel, drivers, and
programs) to display debugging instrumentation produced with the dprintf and
DPRINTF system functions.
None – Instrumentation disabled.
COM1 – Write text to 1st serial port.
COM2 – Write text to 2nd serial port.
COM3 – Write text to 3rd serial port.
COM4 – Write text to 4th serial port.
Virtual – Write text to virtual console
If enabled, this console can provide diagnostic messages (similar to the types displayed
by Linux when it boots) for Firmbase Technology features such as USB HID and USB
Boot.
Firmbase System Console
Specifies the device used by Firmbase Technology’s system process when it
initializes the kernel and processes the [SYSTEM] registry section, including its Start
and Run commands.
None – System console disabled.
COM1 – Write text to 1st serial port.
COM2 – Write text to 2nd serial port.
COM3 – Write text to 3rd serial port.
COM4 – Write text to 4th serial port.
Virtual – Write text to virtual console
If enabled, this console can provide a list of sign-on banners of all Firmbase
applications loaded during system initialization.
Firmbase Shell on Serial
Port
Specifies a serial port that may be used by Firmbase Technology’s command line
interpreter as an extra user session for systems that do not have a keyboard or monitor
to support virtual consoles.
None – Serial console disabled.
COM1 – Console on 1st serial port.
COM2 – Console on 2nd serial port.
COM3 – Console on 3rd serial port.
COM4 – Console on 4th serial port.
Virtual Console History
Specifies the number of lines of text that Firmbase Technology maintains in its virtual
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Appendix B – BIOS & Setup
console feature, allowing the user to scrollback through lines previously displayed and
scrolled off the screen. OEMs may configure a set of values, such as 20, 50, 100, 200,
and 500 lines.
Quiet Mode
Enables a feature that causes the Firmbase kernel to suppress its standard messages to
the system console.
Strict Mode
Enables a feature that causes the Firmbase kernel to abort any processes in the system
that make software errors in calling system API functions. Examples include blocking
at IRQLs other than IRQL_THREAD, or passing a NULL pointer to a C library
function that requires a non-NULL pointer, etc.
Disabling this feature causes the kernel to skip over the activity that discovered the
programming error in the application, allowing it to continue if at all possible, with
the consequence that the program may not operate correctly.
System Cache
Enables POST’s support for cache in the system. Modern processors virtually require
cache to be enabled to achieve acceptable performance. However, to diagnose certain
problems related to caching in the system, such as multiprocessing systems, it may be
desirable to disable this setting.
Keyboard Numlock LED
Enables the Numlock key when POST initializes the PS/2 keyboard.
Typematic Rate
Specify the rate at which the PS/2 keyboard controller repeats characters when most
keys are pressed down. USB typematic is automatic and does not use this parameter.
Typematic Delay
Specifies the amount of time a repeating key may be pressed on a PS/2 keyboard until
the key repeat feature begins repeating the keystroke. USB typematic is automatic and
does not use this parameter.
B.12 Miscellaneous Setup Menu
The Misc menu provides for configuration of BIOS settings that don’t easily fit in any other category. They include
Cache Control, Keyboard Control, Debugger Settings, and System Monitor Utility Configuration parameters.
The following table presents the settings in the Misc Setup menu:
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Appendix B – BIOS & Setup
Lowercase Hex Displays
Enables the display of hexadecimal numbers in the debugger with lowercase letters
instead of uppercase letters (ie, 2f8ah instead of 2F8AH.)
Proprietary Stimulation
Enables System Monitor’s callout to the OEM’s BPM adaptation code to execute code
that causes stimulation of the SMM environment for measurement purposes.
Hard Disk Read
Stimulation
Enables System Monitor’s read of a preconfigured number of sectors from a location
on the first hard disk in the system in order to stimulate the SMM environment. This is
useful when measuring code path lengths in USB boot, when the first hard drive is
configured in the BBS list as a USB hard drive.
Hard Disk Write
Stimulation
Enables System Monitor’s write of a preconfigured number of sectors to a location on
the first hard disk in the system in order to stimulate the SMM environment. This is
useful when measuring code path lengths in USB boot, when the first hard drive is
configured in the BBS list as a USB hard drive.
Please note that when this parameter is selected, the system automatically enables
reading, so that the stimulation of the system includes reading a range of sectors into a
memory buffer, and writing the same data back to the same range of sectors for safety.
Thus, this feature is theoretically nondestructive.
WARNING: YOU ARE ADVISED THAT THIS FEATURE COULD CAUSE DATA
LOSS AT YOUR SOLE EXPENSE; ACCORDINGLY, IT IS PROVIDED AS-IS
WITHOUT WARRANTY OF ANY KIND. ALWAYS BACKUP YOUR DATA
BEFORE PERFORMING DIAGNOSTICS ON ANY SYSTEM, AS THEY COULD
CAUSE DATA LOSS.
Floppy Disk Read
Stimulation
There is no Floppy Drive interface implemented on the CPU-111-10.
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Appendix C – Power & Environment Requirements
Parameter
Condition
Range
Comment
Temperature
Operating
-10˚C to +50˚C
Clock throttling can be implemented for wider temperature
ranges
Storage
-50˚C to +85˚C
Humidity
Operating
20 to 95% non-condensing
±4% relative humidity, per
MIL-STD-810F
Storage
0 to 100% non-condensing
Altitude
Unlimited
Vibration
Sine
10g peak 15-2 kHz
All levels based on a sweep duration of 10 minutes per axis,
each of three mutually perpendicular axes. Qualification
testing is displacement limited below 44 Hz.
Random
0.1 g2/Hz 15-2 kHz
(14.1 g
rms
)
60 minutes per axis each of three mutually perpendicular
axes.
Shock
40 g peak
Three hits per direction per axis, 1/2 sine + terminal peak
sawtooth, 11mS (total 36 hits).
Supply Rail
Voltage
Current
Power
VS1, VS2
12V
VS3
5.0V
C. Environmental and Power Requirements
The CPU-111-10 power and environmental requirements are shown in the tables below.
The 3 Volt lithium coin cell is a BR1225 with 48 mAhours capacity and it is used to battery-back the Real Time
Clock and the BIOS’s NV-RAM.
Table 12: Environmental Requirements
Table 13: Power Requirements
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Appendix D – XPDDRIO Rear Plug-in I/O Expansion Module for the CPU-111-10
Wafer Type Row G Row F Row E Row D Row C Row B Row A
No Wafer1
Power No Pad2
Power Vs3 (5V) No Pad3
Single-ended GND GND SYSRESET#4
Single-ended RTM_MDIO GND GND5
Single-ended RTM_MDC GND GND6
Differential GND GND7
Differential GND GND GND8
Vs3 (5V) Vs3 (5V) Vs3 (5V) Vs3 (5V) Vs3 (5V)
9
10
11
12
13
14
15
16
No Wafer
No Wafer
No Wafer
No Wafer
No Wafer
No Wafer
No Wafer
No Wafer
RTM_PWREN
Wafer Type Row G Row F Row E Row D Row C Row B Row A
XAUI7-TX0+1
GND2
XAUI7-TX2+3
GND XAUI7-TX3- XAUI7-TX3+ GND4
GND5
GND GND6
Differential GND7
Differential GND GND8
GND
GND
XAUI7-TX1-
XAUI7-TX0-
XAUI7-TX1+
GND XAUI7-TX2-
9
GND10
11
GND GND12
GND13
GND GND14
Differential GND15
Differential GND GND16
GND
GND
GND
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
XAUI7-RX0-
XAUI7-RX1+
XAUI7-RX2-
XAUI7-RX3+
XAUI7-RX0+
GND
XAUI7-RX2+
GND
GND
GND
GND
GND
GND
GND
XAUI7-RX3-
GND
GND
GND
XAUI7-RX1-
GND
GND
GND
GND
GND
COM0-TX
COM0-RX
VGA-R
VGA-B
VGA-G
VGA-HS
VGA-VS
MDX0-A2- MDX0-A2+ MDX0-B2+MDX0-B2-
MDX0-C2- MDX0-C2+ MDX0-D2- MDX0-D2+
SATA0-TX+
SATA1-TX-
SATA0-TX-
SATA1-TX+
SATA0-RX-
SATA1-RX+
SATA0-RX+
SATA1-RX-
SATA2-TX+SATA2-TX- SATA2-RX- SATA2-RX+
SATA3-TX- SATA3-TX+ SATA3-RX+SATA3-RX-
SATA4-TX- SATA4-TX+ SATA4-RX- SATA4-RX+
SATA5-RX- SATA5-RX+SATA5-TX- SATA5-TX+
USB0- USB0+
USB2- USB2+
USB1+USB1-
USB3+USB3-
MDX1-A2- MDX1-A2+ MDX1-B2+MDX1-B2-
MDX1-C2- MDX1-C2+ MDX1-D2- MDX1-D2+
D. RTM Rear Plug-in I/O Expansion Module for the CPU-111-10
Dynatem offers a rear transition module for I/O expansion with the CPU-111-10.
D.1 RTM VPX Pin-outs
Table 14: RTM VPX RP0 Pin-outs
Table 15: RTM VPX RP4 Pin-outs
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC – User’s Manual 44
Page 50
Appendix D – XPDDRIO Rear Plug-in I/O Expansion Module for the CPU-111-10
Wafer Type Row G Row F Row E Row D Row C Row B Row A
J14-11
2
3
GND4
GND5
GND6
GND7
GND8
GND
GND
GND
9
10
11
GND12
GND13
GND14
GND15
GND16
GND
GND
GND
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
J14-3
J14-7
J14-11
J14-15
J14-5
J14-9
J14-13
J14-17 J14-19
J14-23
J14-27
J14-31
J14-21
J14-25
J14-29
J14-33 J14-35
J14-39
J14-43
J14-47
J14-37
J14-41
J14-45
J14-49 J14-51
J14-55
J14-59
J14-63
J14-53
J14-57
J14-61
RTM_MDIO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
RTM_MDC
SMB_B_DAT
SMB_B_CLK
RTM_PWREN
RTM_PWRGD
EEP_WP
RTM_PBRST#
J14-2
J14-6
J14-10
J14-14
J14-18
J14-22
J14-26
J14-30
J14-34
J14-38
J14-42
J14-46
J14-50
J14-54
J14-58
J14-62
J14-4
J14-8
J14-12
J14-16
J14-20
J14-24
J14-28
J14-32
J14-36
J14-40
J14-44
J14-48
J14-52
J14-56
J14-60
J14-64
Wafer Type Row G Row F Row E Row D Row C Row B Row A
J24-11
2
3
GND4
GND5
GND6
GND7
GND8
GND
GND
GND
9
10
11
GND12
GND13
GND14
GND15
GND16
GND
GND
GND
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
J24-3
J24-7
J24-11
J24-15
J24-5
J24-9
J24-13
J24-17 J24-19
J24-23
J24-27
J24-31
J24-21
J24-25
J24-29
J24-33 J24-35
J24-39
J24-43
J24-47
J24-37
J24-41
J24-45
J24-49 J24-51
J24-55
J24-59
J24-63
J24-53
J24-57
J24-61
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
J24-2
J24-6
J24-10
J24-14
J24-18
J24-22
J24-26
J24-30
J24-34
J24-38
J24-42
J24-46
J24-50
J24-54
J24-58
J24-62
J24-4
J24-8
J24-12
J24-16
J24-20
J24-24
J24-28
J24-32
J24-36
J24-40
J24-44
J24-48
J24-52
J24-56
J24-60
J24-64
Table 16: RTM VPX RP3 Pin-outs
Table 17: RTM VPX RP6 Pin-outs
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC – User’s Manual 45
Page 51
Appendix D – XPDDRIO Rear Plug-in I/O Expansion Module for the CPU-111-10
J14-2
J14-6
J14-10
J14-14
J14-18
J14-22
J14-26
J14-30
J14-34
J14-38
J14-42
J14-46
J14-50
J14-54
J14-58
J14-62
J14-4
J14-8
J14-12
J14-16
J14-20
J14-24
J14-28
J14-32
J14-36
J14-40
J14-44
J14-48
J14-52
J14-56
J14-60
J14-64
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
J14-1
J14-3
J14-7
J14-11
J14-15
J14-5
J14-9
J14-13
J14-17
J14-19
J14-23
J14-27
J14-31
J14-21
J14-25
J14-29
J14-33
J14-35
J14-39
J14-43
J14-47
J14-37
J14-41
J14-45
J14-49
J14-51
J14-55
J14-59
J14-63
J14-53
J14-57
J14-61
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17
19
21
23
25
27
29
31
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
J2 J4
J24-2
J24-6
J24-10
J24-14
J24-18
J24-22
J24-26
J24-30
J24-34
J24-38
J24-42
J24-46
J24-50
J24-54
J24-58
J24-62
J24-4
J24-8
J24-12
J24-16
J24-20
J24-24
J24-28
J24-32
J24-36
J24-40
J24-44
J24-48
J24-52
J24-56
J24-60
J24-64
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
J24-1
J24-3
J24-7
J24-11
J24-15
J24-5
J24-9
J24-13
J24-17
J24-19
J24-23
J24-27
J24-31
J24-21
J24-25
J24-29
J24-33
J24-35
J24-39
J24-43
J24-47
J24-37
J24-41
J24-45
J24-49
J24-51
J24-55
J24-59
J24-63
J24-53
J24-57
J24-61
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17
19
21
23
25
27
29
31
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
J1 J3
SignalPin
VGA_RED1
VGA_GREEN2
VGA_BLUE3
4
GND5
GND6
GND7
GND8
VGA Connector
9
10
11
12
13
14
15
5V
GND
VGA_HS
VGA_VS
SignalPin
5V1
USB-2
USB+3
GND4
USB Connectors
SignalPin
GND1
TX+2
TX-3
GND4
RX-5
RX+6
GND7
SATA Connectors
SignalPin
1
RX+2
TX+3
4
GND5
RX-6
7
8
SERIAL PORT
TX-9
SignalPin
MX1+1
MX1-2
MX2+3
MX3+4
MX3-5
MX2-6
MX4+7
MX4-8
Ethernet Connectors
15
610
11
14
17
1 5
6 915 1 8
12
34
56
SignalPin
KYBD_DATA1
M_DATA2
GND3
KYBD_VCC4
KYBD_CLK5
M_CLK6
PS2 Connector
D.2 CPU-111-10 Rear Transition Module PMC I/O Pin-outs
Table 18: PMC I/O Header Pin-outs
D.3 Rear Panel Connector Pin-outs
Table 19: RTM Rear Panel Connector Pin-outs
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC – User’s Manual 46
Page 52
Appendix D – XPDDRIO Rear Plug-in I/O Expansion Module for the CPU-111-10
Dynatem CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC – User’s Manual 47
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