Dynamic Engineering PMC-XM-DIFF User Manual

DYNAMIC ENGINEERING

150 DuBois, Suite C

Santa Cruz, CA 95060

[phone] Fax [phone]

http://www.dyneng.com

[e-mail]

Est. 1988

User Manual

PMC-XM-DIFF

Interface Module with Re-configurable I/O logic

RS-485 or LVDS or mixed

34 Differential Pairs at Bezel

32 Differential Pairs at Pn4

Revision A

Corresponding Hardware: Revision A

10-2007-0201

Corresponding Firmware: Revision A

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PMC-XM-DIFF

PMC based interface module
With plug-in I/O hardware and Re­configurable I/O logic

Dynamic Engineering
150 DuBois, Suite C
Santa Cruz, CA 95060
[phone]
FAX: [phone]

This document contains information of
proprietary interest to Dynamic Engineering. It
has been supplied in confidence and the
recipient, by accepting this material, agrees that
the subject matter will not be copied or
reproduced, in whole or in part, nor its contents
revealed in any manner or to any person except
to meet the purpose for which it was delivered.

Dynamic Engineering has made every effort to
ensure that this manual is accurate and
complete. Still, the company reserves the right to
make improvements or changes in the product
described in this document at any time and
without notice. Furthermore, Dynamic
Engineering assumes no liability arising out of
the application or use of the device described
herein.

The electronic equipment described herein
generates, uses, and can radiate radio
frequency energy. Operation of this equipment
in a residential area is likely to cause radio
interference, in which case the user, at his own
expense, will be required to take whatever
measures may be required to correct the
interference.

Dynamic Engineering’s products are not
authorized for use as critical components in life
support devices or systems without the express
written approval of the president of Dynamic
Engineering.

Connection of incompatible hardware is likely to
cause serious damage.

©2007-2010 by Dynamic Engineering.
Other trademarks and registered trademarks are
owned by their respective manufactures.
Manual Revision A. Revised February 26, 2010

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Table of Contents

PRODUCT DESCRIPTION 6

THEORY OF OPERATION 8

PROGRAMMING 9

ADDRESS MAP SPARTAN3 10

Register Definitions 11

PMC_XM_BASE 11
PMC_XM_USER_SWITCH 13
XM_CHAN0/1_CNTRL 15
XM_CHAN0/1_STATUS 17
XM_CHAN0/1_WR/RD_DMA_PNTR 19
XM_CHAN0/1_FIFO 19
XM_CHAN0/1_TX_AMT_LVL 20
XM_CHAN0/1_RX_AFL_LVL 20
XM_CHAN0/1_TX/RX_FIFO_COUNT 21

ADDRESS MAP: VIRTEX ATP DESIGN 22

Register Definitions 23

XM_VATP_BASE 23
XM_VATP_STATUS 25
XM_VATP_CHAN0/1_CNTRL 26
XM_VATP_CHAN0/1_STATUS 27
XM_VATP_TX0/1_FIFO 28
XM_VATP_RX0/1_FIFO 28
XM_VATP_TX0/1_DCOUNT 29
XM_VATP_RX0/1_DCOUNT 29

VIRTEX PIN OUT 30

TRANSITION MODULE MECHANICAL DRAWING 39

MEZZANINE MODULE CONNECTOR J1 40

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MEZZANINE MODULE CONNECTOR J2 41

APPLICATIONS GUIDE 42

Interfacing 42

Construction and Reliability 43

Thermal Considerations 43

WARRANTY AND REPAIR 44

Service Policy 44

Out of Warranty Repairs 44

For Service Contact: 44

SPECIFICATIONS 45

ORDER INFORMATION 46

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List of Figures

FIGURE 1 PMC-XM BLOCK DIAGRAM 6
FIGURE 2 PMC-XM SPARTAN3 XILINX ADDRESS MAP 10
FIGURE 3 PMC-XM SPARTAN3 BASE CONTROL REGISTER 11
FIGURE 4 PMC-XM SPARTAN3 USER SWITCH PORT 13
FIGURE 5 PMC-XM SPARTAN3 STATUS PORT 14
FIGURE 6 PMC-XM SPARTAN3 CHANNEL CONTROL REGISTER 15
FIGURE 7 PMC-XM SPARTAN3 CHANNEL STATUS PORT 17
FIGURE 8 PMC-XM SPARTAN3 CHANNEL DMA POINTER PORT 19
FIGURE 9 PMC-XM SPARTAN3 CHANNEL FIFO PORT 19
FIGURE 10 PMC-XM SPARTAN3 CHANNEL TX ALMOST EMPTY PORT 20
FIGURE 11 PMC-XM SPARTAN3 CHANNEL RX ALMOST FULL PORT 20
FIGURE 12 PMC-XM SPARTAN3 CHANNEL TX/RX FIFO COUNT PORT 21
FIGURE 13 PMC-XM VIRTEX (ATP) XILINX ADDRESS MAP 22
FIGURE 14 PMC-XM VIRTEX (ATP) BASE CONTROL REGISTER 23
FIGURE 15 PMC-XM VIRTEX (ATP) BASE STATUS PORT 25
FIGURE 16 PMC-XM VIRTEX (ATP) CHANNEL CONTROL REGISTER 26
FIGURE 17 PMC-XM VIRTEX (ATP) CHANNEL STATUS PORT 27
FIGURE 18 PMC-XM VIRTEX (ATP) CHANNEL TX FIFO PORT 28
FIGURE 19 PMC-XM VIRTEX (ATP) CHANNEL RX FIFO PORT 28
FIGURE 20 PMC-XM VIRTEX (ATP) CHANNEL TX FIFO COUNT PORT 29
FIGURE 21 PMC-XM VIRTEX (ATP) CHANNEL RX FIFO COUNT PORT 29
FIGURE 22 PMC-XM MEZZANINE CONNECTOR J1 PINOUT 40
FIGURE 23 PMC-XM MEZZANINE CONNECTOR J2 PINOUT 41

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Product Description

The PMC-XM-DIFF features a Xilinx Spartan3-1500 676 pin FPGA to implement the
PCI interface and two independent I/O channels each with a separate input and output
scatter-gather DMA engine to move data to/from host memory over the local 32-bit 33
MHz PCI bus. A Xilinx Virtex4 668 pin FPGA interfaces between the Spartan3 and the
IO. The IO can be configured with RS-485, LVDS or both.

Each IO has separate direction, and termination controls to allow any combination of
inputs and outputs. Impedance controlled and length matched within the mil [.001”] to
allow for any user requirement.

Other features include on-board PLL, optional RAM (1Mx36-bit QDDRII RAM),
temperature sensor, DIP Switch, Built in DMA, and user LED’s.

PCI IF

Data Flow

Control

FPGA

1M x 36 RAM

DMA

RX TX

4Kx32

FIFO

4Kx32

FIFO

RX TX

4Kx32

FIFO

4Kx32

FIFO

User Virtex

PLL

34 LVDS / RS-485 IO

Programmable Terminations

LEDs(4)

DIPSWITCH

TEMP
SENSOR

FIGURE 1 PMC-XM-DIFF BLOCK DIAGRAM

The engineering kit comes with a basic design for the Virtex consisting of the VHDL
package used to generate the ATP implementation. The design includes decoding,
DMA , two channels, IO loop-back and more. The package can include the Windows®
driver and reference code. The reference software is provided as source and can be

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user modified to do whatever you want. The package includes an auto design detection
feature to automatically load menus corresponding to different designs loaded into the
Virtex. The user can change the design number and use the generic driver to access
new features added to the clients implementation. The Virtex can be loaded from
FLASH and overwritten with software. The reference package includes the Virtex load
utilities, PLL programming software, and Temperature sensor read as well as IO loop­back tests.

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Theory of Operation

The Spartan3 FPGA implements the PCI interface for the PMC-XM. Data is transferred
to/from the PCI bus using single-word accesses for control/status or through the four
scatter-gather DMA engines (two in and two out) for accessing the two I/O channels,
each with a 4K x 32-bit transmit FIFO and a 4K x 32-bit receive FIFO.

A data transfer state-machine controls the bidirectional bursting of data between the
Spartan3 and the Virtex for the two I/O channels. The data is transferred across a 32­bit bidirectional data bus and Virtex control/status registers are addressed by an eight­bit address bus. The transfers are independently enabled from the Channel Control
Registers in the Spartan3. In the Virtex ATP design used by Dynamic Engineering to
test the PMC-XM hardware, there are also four corresponding 4K x 32-bit FIFOs to
buffer the bursted data. Handshaking signals generated by the Virtex let the transfer
state-machine know when to burst data and, when the FIFOs are near their limits, when
to move only single words.

The plug-in Interface Module is accessed through the Virtex by the user-specified
design with which it is configured. A programmable PLL supplies two independent clock
frequencies (maximum 200 MHz) to be used by the user. Digital clock managers
(DCMs) in the Virtex FPGA can be used to further enhance the clock capabilities. A
1Mx36-bit QDDRII RAM is accessible by the Virtex for intermediate processing of I/O
data and a 13-bit digital temperature sensor can be used to read the ambient
temperature of the PMC-XM environment.

Scatter-gather DMA is accomplished by writing a list of memory descriptors to host
memory. Each descriptor consists of three long-words: the physical address of a block
of contiguous user memory, the length of that block and a pointer to the next list entry.
The last word of each descriptor also contains two flag-bits that are replaced with zeros
for the actual memory access. Bit 0 is the end-of-chain bit. When this bit is set, the
current descriptor is the last in the list. Bit 1 is the direction bit. When this bit is set, it
indicates that the transfer is from the module to host memory. When this bit is zero,
data is transferred from host memory to the PMC-XM.

The address of the first list entry is written to the DMA engine to begin DMA processing.
The DMA continues until the list is complete and an interrupt is signaled to clean-up the
transfer and potentially begin another. It is necessary that all memory pages that are to
be accessed be physically resident in memory while the DMA is in progress.
The four DMA engines can all operate simultaneously. PCI bus access is arbitrated on
a round-robin basis with a DMA engine relinquishing the bus at the end of each list entry
transfer or when the corresponding FIFO gets close to full for the transmit or empty for
the receive. The arbiter can also be configured to give priority to a channel that is
approaching the FIFO limit (almost-empty for the transmit or almost-full for the receive).

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Programming

Programming the PMC-XM requires only the ability to read and write data from the host.
The base address is determined during system configuration of the PCI bus. The base
address refers to the first user address for the slot in which the PMC is installed. The
VendorId = 0x10EE. The CardId = 0x0024. Current revision = 0x07

Depending on the software environment it may be necessary to set-up the system
software with the PMC-XM "registration" data. For example in WindowsNT there is a
system registry, which is used to identify the resident hardware.

To use DMA it will be necessary to acquire a block of non-paged memory that is
accessible from the PCI bus in which to store chaining descriptor list entries.

At Dynamic Engineering the PMC-XM-DIFF is tested in a Windows environment and we
use the Dynamic Engineering Drivers to do the hardware accesses and manage the
DMA’s. We use MS Visual C++ in conjunction with the drivers to write our test software.
Please consider purchasing the engineering kit for the PMC-XM; the software kit
includes the drivers and our test suite.

The Spartan3 address space begins at address offset 0, the Virtex address space
begins at offset 0x400.

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Address Map Spartan3

Register Name Offset Description

PMC_XM_BASE 0x0000 // Base control register
PMC_XM_USER_SWITCH 0x0004 // User switch/Xilinx rev. read port
PMC_XM_STATUS 0x0008 // Interrupt status/clear port
XM_CHAN0_CNTRL 0x0010 // Channel 0 Control register offset
XM_CHAN0_STATUS 0x0014 // Channel 0 Status read/latch clear port offset
XM_CHAN0_WR_DMA_PNTR 0x0018 // Channel 0 Write DMA physical address register
XM_CHAN0_RD_DMA_PNTR 0x001C // Channel 0 Read DMA physical address register
XM_CHAN0_FIFO 0x0020 // Channel 0 FIFO offset for single word access
XM_CHAN0_TX_AMT_LVL 0x0024 // Channel 0 TX almost empty level register offset
XM_CHAN0_RX_AFL_LVL 0x0028 // Channel 0 RX almost full level register offset
XM_CHAN0_TX_FIFO_COUNT 0x002C // Channel 0 TX FIFO count read port offset
XM_CHAN0_RX_FIFO_COUNT 0x0030 // Channel 0 RX FIFO count read port offset
XM_CHAN1_CNTRL 0x0040 // Channel 1 Control register offset
XM_CHAN1_STATUS 0x0044 // Channel 1 Status read/latch clear port offset
XM_CHAN1_WR_DMA_PNTR 0x0048 // Channel 1 Write DMA physical address register
XM_CHAN1_RD_DMA_PNTR 0x004C // Channel 1 Read DMA physical address register
XM_CHAN1_FIFO 0x0050 // Channel 1 FIFO offset for single word access
XM_CHAN1_TX_AMT_LVL 0x0054 // Channel 1 TX almost empty level register offset
XM_CHAN1_RX_AFL_LVL 0x0058 // Channel 1 RX almost full level register offset
XM_CHAN1_TX_FIFO_COUNT 0x005C // Channel 1 TX FIFO count read port offset
XM_CHAN1_RX_FIFO_COUNT 0x0060 // Channel 1 RX FIFO count read port offset

FIGURE 2 PMC-XM SPARTAN3 XILINX ADDRESS MAP

The address map provided is for the local decoding performed within the PMC-XM
Spartan3 Xilinx. The addresses are all offsets from a base address. The base address
and interrupt level are provided by the host in which the PMC-XM is installed.

The host system will search the PCI bus to find the assets installed during power-on
initialization. The VendorId = 0x10EE and the CardId = 0x0024 for the PMC-XM.
Interrupts are requested by the configuration space. PCIView and other third party
utilities can be useful to see how your system is configured. Dynamic Engineering
recommends using the Dynamic Engineering Drivers to take care of initialization and
device registration.

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Register Definitions

PMC_XM_BASE

[0x0000] Base Control Register (read/write)

Base Control Register

Data Bit Description

31-17 Spare

16 Load Virtex

15-10 Spare

9 Virtex Init
8 Virtex Reset
7 Virtex Flash Enable
6 Slave Serial Mode Enable
5 Virtex Program Init
4 Virtex Program Select
3 Flash Select
2 Flash Control
1 Force Interrupt
0 Master Interrupt Enable

FIGURE 3 PMC-XM SPARTAN3 BASE CONTROL REGISTER

All bits are active high and default to ‘0’ on reset or power-up.

Master Interrupt Enable: This bit enables the interrupts for the base portion of the XM
design. When this bit is a ‘1’, the interrupt is enabled; and when this bit is a ‘0’ the
interrupt is disabled. Currently the only interrupt source for this portion of the design is
the Force Interrupt bit.

Force Interrupt: When this bit is ‘1’ and the Master Interrupt Enable is ‘1’, an interrupt
will be generated. This bit is useful for software development and debugging.

Flash Control: When this bit is ‘1’, the Flash Select bit controls which Flash Prom is
connected to the JTAG port. When this bit is ‘0’, I/O bit 63 controls the selection. When
I/O bit 63 is grounded, the Virtex Flash is selected; when I/O bit 63 is open, the signal is
pulled high and the Spartan3 Flash is selected.

Flash Select: When Flash Control is set to ‘1’ this bit controls which Flash Prom is
connected to the JTAG port. When Flash Select is ‘0’, the Virtex Flash is selected;
when Flash Select is ‘1’, the Spartan3 Flash is selected. When Flash Control is ‘0’, this
bit has no effect.

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Virtex Program Select: When this bit is ‘1’, the Virtex Flash is controlled by the Virtex
Flash Enable bit. When this bit is ‘0’, the Virtex Flash is controlled by the Virtex done
bit.

Virtex Program Init: When this bit is set to ‘1’ it forces the Virtex to re-configure from the
Flash Prom. When this bit is ‘0’, the Virtex can be re-configured by a bit-file load.

Slave Serial Mode Enable: When this bit is set to ‘1’, slave serial programming mode is
selected on the Virtex. When this bit is ‘0’ master serial mode is selected. Slave serial
mode is used when the Virtex is programmed from a file by the Spartan3 and master
serial mode is used when the Virtex configures from the on-board flash.

Virtex Flash Enable: When this bit is ‘0’ and the Virtex Program Select bit is ‘1’, the
Virtex flash is disabled so that the Spartan3 can program the Virtex from a bit-file.

Virtex Reset: When this bit is ‘1’, all the registers and FIFOs in the Virtex are reset.
When this bit is ‘0’, the Virtex can resume normal operation.

Virtex Init: When set to ‘1’, this bit delays configuration when a configuration cycle has
been initiated. When this bit transitions to ‘0’, the mode bits are sampled and the
configuration can proceed. The bit then becomes a status bit, which is read from the
Status register, a ‘0’ indicating a CRC error.

Load Virtex: when set to ‘1’, begins the process of programming the Virtex device from
a bit-file. The data must be read from the file and loaded into the TX0 FIFO. When the
hardware detects that the load is complete this bit will be automatically cleared.

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PMC_XM_USER_SWITCH

[0x0004] User Switch Port (read only)

Dip-Switch Port

Data Bit Description

31-16 Spare

15-8 Xilinx Design Revision Number

7-0 Sw7-0

FIGURE 4 PMC-XM SPARTAN3 USER SWITCH PORT

Sw7-0: The user switch is read through this read-only port. The bits are read as the
lowest byte. Access the port as a long word and mask off the undefined bits. The dip­switch positions are defined in the silkscreen. For example the switch figure below
indicates a 0x12.

Xilinx design revision number: The value of the second byte of this port is the rev.
number of the Xilinx design (currently 0x05 - rev. E).

1

7 0

0

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PMC_XM_STATUS

[0x0008] Status Register Read / Latch Clear Write

Status Register

Data Bit Description

31 Interrupt Status

30-24 Spare

23 Virtex Status 3
22 Virtex Status 2
21 Virtex Status 1
20 Virtex Status 0

19-10 Spare

9 Virtex Init Status
8 Virtex Configuration Done

7-1 Spare

0 Local Interrupt Active

FIGURE 5 PMC-XM SPARTAN3 STATUS REGISTER

Local Interrupt Active: When read as a ‘1’, a local interrupt condition is active.
Currently, the only such condition is the Force Interrupt bit in the Base Control Register.
A system interrupt will not occur unless the Master Interrupt Enable bit in the Base
Control Register is also set. When read as a ‘0’, no local interrupt conditions are active.

Virtex Configuration Done: When read as a ‘1’, the Virtex FPGA has successfully
configured. When read as a ‘0’, the Virtex configuration was not successful.

Virtex Init Status: When read as a ‘1’ after the Virtex configuration, it indicates that a
CRC error did not occur during the Virtex configuration. When read as a ‘0’ after the
Virtex configuration, it indicates that a CRC error occurred during the previous Virtex
configuration. In this case the Done bit should also be low.

Virtex Status 3-0: These bits are driven by the Virtex to indicate arbitrary status
conditions. In the current Virtex ATP design they are all low, but they can be assigned
for any purpose desired.

Interrupt Status: When read as a ‘1’, an enabled local interrupt condition is active and a
system interrupt should be asserted. When read as a ‘0’, no enabled local interrupt is
active.

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XM_CHAN0/1_CNTRL

[0x0010, 0x0040] Channel Control Register (read/write]

Control Register

Data Bit Description

31-9 Spare

11 DMA Read Arbitration Priority Enable
10 DMA Write Arbitration Priority Enable

9 Virtex Interrupt Enable
8 Receive Enable
7 Transmit Enable
6 Force Interrupt
5 Master Interrupt Enable
4 DMA Read Enable
3 DMA Write Enable
2 FIFO Bypass
1 RX FIFO Reset
0 TX FIFO Reset

FIGURE 6 PMC-XM SPARTAN3 CHANNEL CONTROL REGISTER

TX/RX FIFO Reset: When this bit is ‘1’, the transmit or receive FIFO for the referenced
channel is placed in a reset condition. When this bit is ‘0’, the corresponding FIFO is in
a normal operational state.

FIFO Bypass: When this bit is ‘1’, any data written to the transmit FIFO will be
transferred to the receive FIFO as long as there is room in the receive FIFO. This
facilitates FIFO loop-back testing. When this bit is ‘0’, data written to the transmit FIFO
will remain in the FIFO until read by the data transfer state machine.

DMA Write Enable: When this bit is ‘1’, the write DMA interrupt is enabled for the
referenced channel. When this bit is ‘0’, the write DMA interrupt is disabled.

DMA Read Enable: When this bit is ‘1’, the read DMA interrupt is enabled for the
referenced channel. When this bit is ‘0’, the read DMA interrupt is disabled.

Master Interrupt Enable: This bit enables the local interrupts for the referenced channel.
When this bit is a ‘1’, the interrupt is enabled; and when this bit is a ‘0’ the interrupt is
disabled. Currently the only interrupt source for this portion of the design is the Force
Interrupt bit in this register.

Force Interrupt: When this bit is ‘1’ and the Master Enable is a ‘1’, a system interrupt will

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occur. This bit is useful for software development and debugging.
Transmit Enable: When this bit is ‘1’, the transfer state machine is enabled to move data
from the referenced channel’s transmit FIFO to the corresponding Virtex transmit FIFO.
When this bit is ‘0’, the transmit transfer state machine is disabled.

Receive Enable: When this bit is ‘1’, the transfer state machine is enabled to move data
from the referenced channel’s Virtex receive FIFO to the corresponding local receive
FIFO. When this bit is ‘0’, the receive transfer state machine is disabled.

Virtex Interrupt Enable: When this bit is ‘1’, the corresponding Virtex interrupt (VINT0 for
channel 0 or VINT1 for channel 1) is enabled to cause a system interrupt when active.
When this bit is ‘0’, the Virtex interrupt can not cause a system interrupt.

DMA Write Arbitration Priority Enable: When this bit is ‘1’, the write DMA for the
referenced channel will receive priority if the TX FIFO has become almost empty as
defined by the value stored in the TX_AMT_LVL register. When this bit is ‘0’, the DMA
arbitration will follow round-robin arbitration priority.

DMA Read Arbitration Priority Enable: When this bit is ‘1’, the read DMA for the
referenced channel will receive priority if the RX FIFO has become almost full as
defined by the value stored in the RX_AFL_LVL register. When this bit is ‘0’, the DMA
arbitration will follow round-robin arbitration priority.

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XM_CHAN0/1_STATUS

[0x0014, 0x0044] Channel Status Read / Latch Clear Write

Status Register

Data Bit Description

31 INT_STAT

30-18 Spare

17 Virtex Interrupt Active
16 Local Interrupt Active
15 Read DMA Interrupt Active
14 Write DMA Interrupt Active
13 Read DMA Error
12 Write DMA Error

11-8 Spare

7 Receive FIFO Valid
6 Receive FIFO Full
5 Receive FIFO Almost Full
4 Receive FIFO Empty
3 Spare
2 Transmit FIFO Full
1 Transmit FIFO Almost Empty
0 Transmit FIFO Empty

FIGURE 7 PMC-XM SPARTAN3 CHANNEL STATUS REGISTER

Transmit FIFO Empty: When read as a ‘1’, the corresponding transmit FIFO is empty.
When read as a ‘0’, the FIFO has at least one word in it.

Transmit FIFO Almost Empty: : When read as a ‘1’, the corresponding transmit FIFO is
almost empty as determined by the value entered in the almost empty level register.
When read as a ‘0’, there is more data in the FIFO than specified in the level register.

Transmit FIFO Full: When read as a ‘1’, the corresponding transmit FIFO is full. When
read as a ‘0’, there is room for at least one more word in the FIFO.

Receive FIFO empty: When read as a ‘1’, the corresponding receive FIFO is empty.
When read as a ‘0’, the FIFO has at least one word in it.

Receive FIFO Almost Full: When read as a ‘1’, the corresponding receive FIFO is
almost full as determined by the value entered in the almost full level register. When
read as a ‘0’, there is less data in the FIFO than specified in the level register.

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Receive FIFO Full: When read as a ‘1’, the corresponding receive FIFO is full. When
read as a ‘0’, there is room for at least one more word in the FIFO.

Receive FIFO Valid: When read as a ‘1’, there is valid receive data to read. When read
as a ‘0’, there is no valid receive data. There is a four-deep pipeline on the output of the
RX FIFO that will be filled before data is retained in the FIFO. Therefore even though
the FIFO is empty there may actually be up to four long-words of valid receive data.
This status bit indicates when there is valid data even though the FIFO is empty.

Write DMA Error: When read as a ‘1’, a write DMA error has been detected. This will
occur if there is a target or master abort or if the direction bit in the next pointer of one of
the chaining descriptors is a one. When read as a ‘0’, no error has occurred.

Read DMA Error: When read as a ‘1’, a read DMA error has been detected. This will
occur if there is a target or master abort or if the direction bit in the next pointer of one of
the chaining descriptors is a zero. When read as a ‘0’, no error has occurred.

Write DMA Interrupt Active: When read as a ‘1’, a write DMA interrupt is latched. This
indicates that the scatter-gather list for the current write DMA has completed, but the
associated interrupt has yet to be completely processed. When read as a ‘0’, no write
DMA interrupt is pending.

Read DMA Interrupt Active: When read as a ‘1’, a read DMA interrupt is latched. This
indicates that the scatter-gather list for the current read DMA has completed, but the
associated interrupt has yet to be completely processed. When read as a ‘0’, no read
DMA interrupt is pending

Local Interrupt Active: When read as a ‘1’, a local interrupt condition is active for the
referenced channel. Currently, the only such condition is the Force Interrupt bit in the
Channel Control Register. A system interrupt will not occur unless the Master Interrupt
Enable bit in the Channel Control Register is also set. When read as a ‘0’, no local
interrupt conditions are active.

Virtex Interrupt Active: When read as a ‘1’, the corresponding Virtex interrupt (VINT0 for
channel 0 or VINT1 for channel 1) is active. A system interrupt will not occur unless the
Virtex Interrupt Enable in the Channel Control Register is set. When read as a ‘0’, the
Virtex interrupt is inactive.

INT_STAT: When read as a ‘1’, an enabled channel interrupt condition is active and a
system interrupt should be asserted. When read as a ‘0’, no enabled channel interrupt
is active.

Embedded Solutions Page 19 of 46

XM_CHAN0/1_WR/RD_DMA_PNTR

[0x0018, 0x001C, 0x0048, 0x004C] DMA Address Register (Write only)

DMA Pointer Address Register

Data Bit Description

31-0 First Chaining Descriptor Physical Address

FIGURE 8 PMC-XM SPARTAN3 CHANNEL DMA POINTER REGISTER

These write-only ports are used to initiate scatter-gather DMAs. When the physical
address of the first chaining descriptor is written to one of these ports, the
corresponding DMA engine reads three successive long words beginning at that
address. The first is the address of the first memory block of the DMA buffer, the
second is the length in bytes of that block, and the third is the address of the next
chaining descriptor in the list of buffer memory blocks. This process is continued until a
bit in one of the next pointer values read indicates that it is the end of the chain.

Note: Writing a zero to one of these ports will abort the associated DMA if one is in
progress.

XM_CHAN0/1_FIFO

[0x0020, 0x0050] Write TX/Read RX FIFO Port

TX / RX FIFO Port

Data Bit Description

31-0 FIFO Data 31-0

FIGURE 9 PMC-XM SPARTAN3 CHANNEL FIFO PORT

Data written to this address is written into the transmit FIFO as long as the FIFO is not
full. When this address is read a data-word is read from the receive FIFO. When the
receive FIFO becomes empty, the last data-word that was in the FIFO will be returned.

Embedded Solutions Page 20 of 46

XM_CHAN0/1_TX_AMT_LVL

[0x0024, 0x0054] TX Almost Empty Level Register (read/write)

TX Almost Empty Level Register

Data Bit Description

31-16 Spare

15-0 TX FIFO Almost Empty Level

FIGURE 10 PMC-XM SPARTAN3 CHANNEL TX ALMOST EMPTY REGISTER

This register specifies the level at which the transmit FIFO almost empty level will be
asserted. When the number of data words in the transmit FIFO is less than or equal to
this count the almost empty status will be asserted.

XM_CHAN0/1_RX_AFL_LVL

[0x0028, 0x0058] RX Almost Full Level Register (read/write)

RX Almost Full Level Register

Data Bit Description

31-16 Spare

15-0 RX FIFO Almost Full Level

FIGURE 11 PMC-XM SPARTAN3 CHANNEL RX ALMOST FULL REGISTER

This register specifies the level at which the receive FIFO almost full level will be
asserted. When the number of data words in the receive FIFO is greater than or equal
to this count the almost full status will be asserted.

Embedded Solutions Page 21 of 46

XM_CHAN0/1_TX/RX_FIFO_COUNT

[0x002C, 0x0030, 0x005C, 0x0060] TX/RX FIFO Data Count Port (read only)

FIFO Data Count

Data Bit Description

31-16 Spare

15-0 FIFO Data Words Stored

FIGURE 12 PMC-XM SPARTAN3 CHANNEL TX/RX FIFO COUNT PORT

These read-only register ports report the number of 32-bit data words in the
corresponding transmit/receive FIFO and data pipeline (currently a maximum of 0x1000
for the transmit and 0x1003 for the receive).

Embedded Solutions Page 22 of 46

Address Map: Virtex ATP Design

Register Name Offset Description

XM_VATP_BASE 0x0400 // Base control register
XM_VATP_STATUS 0x0404 // Interrupt status/clear port
XM_VATP_CHAN0_CNTRL 0x0408 // Channel 0 Control register offset
XM_VATP_CHAN0_STATUS 0x040C // Channel 0 Status read/latch clear port offset
XM_VATP_TX0_FIFO 0x0410 // Channel 0 TX FIFO offset for single word access
XM_VATP_RX0_FIFO 0x0414 // Channel 0 RX FIFO offset for single word access
XM_VATP_TX0_DCOUNT 0x0418 // Channel 0 TX FIFO count read port offset
XM_VATP_RX0_DCOUNT 0x041C // Channel 0 RX FIFO count read port offset
XM_VATP_CHAN1_CNTRL 0x0420 // Channel 1 Control register offset
XM_VATP_CHAN1_STATUS 0x0424 // Channel 1 Status read/latch clear port offset
XM_VATP_TX1_FIFO 0x0428 // Channel 1 TX FIFO offset for single word access
XM_VATP_RX1_FIFO 0x042C // Channel 1 RX FIFO offset for single word access
XM_VATP_TX1_DCOUNT 0x0430 // Channel 1 TX FIFO count read port offset
XM_VATP_RX1_DCOUNT 0x0434 // Channel 1 RX FIFO count read port offset

FIGURE 13 PMC-XM VIRTEX (ATP) XILINX ADDRESS MAP

This address map is only valid for the ATP design supplied by Dynamic Engineering.
The addresses are offset from the PCI address assigned to the card by the system PCI
configuration utility.

Embedded Solutions Page 23 of 46

Register Definitions

XM_VATP_BASE

[0x0400] Base Control Register (read/write)

Base Control Register

Data Bit Description

31–20 Spare

19 PLL SDAT Output
18 PLL S2/Suspend
17 PLL SCLK
16 PLL Enable

15–9 Spare

8 Reset DCM
7 Force Interrupt 1
6 Master Interrupt 1 Enable
5 Force Interrupt 0
4 Master Interrupt 0 Enable

3–0 LED 4–1

FIGURE 14 PMC-XM VIRTEX (ATP) BASE CONTROL REGISTER

LED 4–1: When one of these bits is set to a ‘1’, the corresponding LED will be lit. When
the bit is a ‘0’, the LED will not be lit.

Master Interrupt 0/1 Enable: When this bit is ‘1’, the corresponding interrupt is enabled
(VINT0 or VINT1). When this bit is ‘0’, the interrupt is disabled.

Force Interrupt 0/1: When this bit is ‘1’, and the corresponding interrupt enable is set,
that interrupt will be asserted from the Virtex.

Reset DCM: When this bit is ‘1’, the DCM (Digital Clock Manager) will be manually
reset. When this bit is ‘0’, the DCM will operate normally.

PLL Enable: When this bit is ‘1’, the PLL interface circuit is enabled for reading or
programming the PLL. When this bit is ‘0’, the PLL interface circuit is disabled.

PLL SCLK: This bit is used to clock data into and out of the PLL.

PLL S2/Suspend: This bit is used to select alternative pre-programmed clock
frequencies from the PLL. It is normally set to ‘0’.

Embedded Solutions Page 24 of 46

PLL SDAT Output: This is where the PLL data state is specified when data is being
written to the PLL. When the PLL is driving the data line this bit must be set to a ‘1’.

The PMC-XM has a PLL device which is programmed over an I2C bus to produce the
desired frequencies.

The data line has a pull-up on the board. When the PLL is enabled and the I2C data bit
is set to ‘0’ in this register, the external line is driven low. When not enabled or when
the I2C data bit is set to ‘1’ in this register, the external line is tri-stated and pulled-up by
the resistor. For a read operation the data should be set to ‘1’ to allow the PLL to drive
the data line.

The clock line for the PLL to be programmed is toggled along with the data to create a
bit stream with a “software clock”. Set the bit to the next state and toggle the clock line
and repeat.

The upper selection bit can be set in the register and directly driven to the PLL. This
allows the selection of alternative pre-programmed clock frequencies.

To read over the I2C bus a command is first written and then the bus read for the
response. The I2C data input bit in the status register contains the state of the bus
when read. The software will toggle the clock line and when the low-to-high transition is
made, read the data bit then repeat until the entire message is captured.

The engineering kit contains the logic and software required to program the PLL and to
read-back the internal register programming. The software to determine the frequency
command words is available from Cypress Semiconductor. The PLL part number is
CY22393FC. Cypress has a utility available for calculating the frequency command
words for the PLL. http://www.dyneng.com/CyberClocks.zip is the URL for the Cypress
software used to calculate the PLL programming words. The reference frequency is 40
MHz.

Embedded Solutions Page 25 of 46

XM_VATP_STATUS

[0x0404] Status Register (read only)

Base Status Register

Data Bit Description

31-20 Spare

19 PLL SDAT Input
18 Intstat1
17 Intstat0
16 DCM Locked

15-8 Design ID

7-0 Design Rev.

FIGURE 15 PMC-XM VIRTEX (ATP) BASE STATUS REGISTER

Design ID/Rev.: These fields are read to determine which design and revision is
programmed into the Virtex. This is used to determine the control/status register
configuration and which driver to use to communicate with the design.

DCM Locked: When read as a ‘1’, it indicates that the DCM is in a locked state and the
clocks produced are functioning reliably. When read as a ‘0’, it indicates that the DCM
is not locked and therefore the clocking is not reliable.

Intstat0/1: When read as a ‘1’, it indicates that the corresponding interrupt is active.
When read as a ‘0’, the interrupt is not active.

PLL SDAT Input: This is where the PLL data line is read when data is being read from
the PLL. This line is used to read the register contents of the PLL.

Embedded Solutions Page 26 of 46

XM_VATP_CHAN0/1_CNTRL

[0x0408, 0x0420] Channel Control Register (read/write)

Channel Control Register

Data Bit Description

31 Receive FIFO Reset

30 Transmit FIFO Reset
29-28 Spare
27-16 Receive FIFO Almost Full Level

15-4 Transmit FIFO Almost Empty Level

3 Spare
2 Force Interrupt
1 Master Interrupt Enable
0 FIFO Bypass

FIGURE 16 PMC-XM VIRTEX (ATP) CHANNEL CONTROL REGISTER

FIFO Bypass: When this bit is ‘1’, any data written to the transmit FIFO will be
transferred to the receive FIFO as long as there is room in the FIFO. This facilitates
FIFO loop-back testing. When this bit is ‘0’, data written to the transmit FIFO will remain
in the FIFO until explicitly read.

Master Interrupt Enable: When this bit is ‘1’, the corresponding interrupt is enabled
(VINT0 for channel 0 or VINT1 for channel 1). When this bit is ‘0’, the interrupt is
disabled. This bit has a parallel function with the interrupt enable bits in the base
control register.

Force Interrupt: When this bit is ‘1’, and the corresponding interrupt enable is set, that
interrupt will be asserted from the Virtex. This bit has a parallel function with the force
interrupt bits in the base control register.

Transmit FIFO Almost Empty Level: This field specifies the level at which the transmit
FIFO almost empty level will be asserted. When the number of data words in the
transmit FIFO is less than or equal to this count the almost empty status will be
asserted.

Receive FIFO Almost Full Level: This field specifies the level at which the receive FIFO
almost full level will be asserted. When the number of data words in the receive FIFO is
greater than or equal to this count the almost full status will be asserted.

Transmit/Receive FIFO Reset: When this bit is ‘1’, the corresponding FIFO is placed in
a reset state. When this bit is ‘0’, the FIFO will function normally.

Embedded Solutions Page 27 of 46

XM_VATP_CHAN0/1_STATUS

[0x040C, 0x0424] Channel Status Register (read only)

Channel Status Register

Data Bit Description

31-16 Spare

15 INT_STAT

14-8 Spare

7 Receive FIFO Full
6 Receive FIFO Almost Full
5 Receive FIFO Almost Empty
4 Receive FIFO Empty
3 Transmit FIFO Full
2 Transmit FIFO Almost Full
1 Transmit FIFO Almost Empty
0 Transmit FIFO Empty

FIGURE 17 PMC-XM VIRTEX (ATP) CHANNEL STATUS REGISTER

Transmit FIFO Empty: When read as a ‘1’, the corresponding transmit FIFO is empty.
When read as a ‘0’, the FIFO has at least one word in it.

Transmit FIFO Almost Empty: When read as a ‘1’, the corresponding transmit FIFO is
almost empty as determined by the almost empty field in the control register. When
read as a ‘0’, there is more data in the FIFO than specified in the control register.

Transmit FIFO Almost Full: When read as a ‘1’, the corresponding transmit FIFO is
almost full. The almost full level is hard-coded to 4080 words. When read as a ‘0’,
there are less than this number of words in the FIFO.

Transmit FIFO Full: When read as a ‘1’, the corresponding transmit FIFO is full. When
read as a ‘0’, there is room for at least one more word in the FIFO.

Receive FIFO Empty: When read as a ‘1’, the corresponding receive FIFO is empty.
When read as a ‘0’, the FIFO has at least one word in it.

Receive FIFO Almost Empty: When read as a ‘1’, the corresponding receive FIFO is
almost empty. The almost empty level is hard-coded to 16 words. When read as a ‘0’,
there are more than this number of words in the FIFO.

Receive FIFO Almost Full: When read as a ‘1’, the corresponding receive FIFO is
almost full as determined by the almost full field in the control register. When read as a

Embedded Solutions Page 28 of 46

‘0’, there is less data in the FIFO than specified in the control register.
Receive FIFO Full: When read as a ‘1’, the corresponding receive FIFO is full. When
read as a ‘0’, there is room for at least one more word in the FIFO.

INT_STAT: When read as a ‘1’, the corresponding interrupt is active (VINT0 for channel
0 or VINT1 for channel 1). When read as a ‘0’, the interrupt is not active.

XM_VATP_TX0/1_FIFO

[0x0410, 0x0428] TX FIFO Port (read/write)

TX FIFO Port

Data Bit Description

31-0 FIFO Data 31-0

FIGURE 18 PMC-XM VIRTEX (ATP) CHANNEL TX FIFO PORT

Data written to this address is written into the transmit FIFO as long as the FIFO is not
full. When this address is read a data-word is read from the transmit FIFO. When the
FIFO becomes empty, the last data-word that was in the FIFO will be returned.

XM_VATP_RX0/1_FIFO

[0x0414, 0x042C] RX FIFO Port (read/write)

RX FIFO Port

Data Bit Description

31-0 FIFO Data 31-0

FIGURE 19 PMC-XM VIRTEX (ATP) CHANNEL RX FIFO PORT

Data written to this address is written into the receive FIFO as long as the FIFO is not
full. When this address is read a data-word is read from the receive FIFO. When the
FIFO becomes empty, the last data-word that was in the FIFO will be returned.

Embedded Solutions Page 29 of 46

XM_VATP_TX0/1_DCOUNT

[0x0418, 0x0430] TX FIFO Data Count Port (read only)

TX FIFO Data Count

Data Bit Description

31-12 Spare

11-0 FIFO Data Words Stored

FIGURE 20 PMC-XM VIRTEX (ATP) CHANNEL TX FIFO COUNT PORT

These read-only register ports report the number of 32-bit data words in the
corresponding transmit FIFO (currently a maximum of 0xFFF).

XM_VATP_RX0/1_DCOUNT

[0x041C, 0x0434] RX FIFO Data Count Port (read only)

RX FIFO Data Count

Data Bit Description

31-12 Spare

11-0 FIFO Data Words Stored

FIGURE 21 PMC-XM VIRTEX (ATP) CHANNEL RX FIFO COUNT PORT

These read-only register ports report the number of 32-bit data words in the
corresponding receive FIFO (currently a maximum of 0xFFF).

Embedded Solutions Page 30 of 46

Virtex Pin Out

The Virtex FPGA pin definitions are contained in the engineering kit and repeated here
as a reference. The hardwired pins for power and ground are not shown.

Signal Name Pin Direction I/O Standard
OSC C13 Input LVCMOS 3.3 V
VCLK66 A16 Input LVCMOS 3.3 V
CLK66FB C10 Output LVCMOS 3.3 V

VD<0> A3 Bidir LVCMOS 3.3 V
VD<1> B3 Bidir LVCMOS 3.3 V
VD<2> A4 Bidir LVCMOS 3.3 V
VD<3> B4 Bidir LVCMOS 3.3 V
VD<4> A5 Bidir LVCMOS 3.3 V
VD<5> B6 Bidir LVCMOS 3.3 V
VD<6> A6 Bidir LVCMOS 3.3 V
VD<7> B7 Bidir LVCMOS 3.3 V
VD<8> A7 Bidir LVCMOS 3.3 V
VD<9> B9 Bidir LVCMOS 3.3 V
VD<10> A8 Bidir LVCMOS 3.3 V
VD<11> B10 Bidir LVCMOS 3.3 V
VD<12> A9 Bidir LVCMOS 3.3 V
VD<13> B12 Bidir LVCMOS 3.3 V
VD<14> A10 Bidir LVCMOS 3.3 V
VD<15> B13 Bidir LVCMOS 3.3 V
VD<16> A11 Bidir LVCMOS 3.3 V
VD<17> B14 Bidir LVCMOS 3.3 V
VD<18> A12 Bidir LVCMOS 3.3 V
VD<19> B15 Bidir LVCMOS 3.3 V
VD<20> A15 Bidir LVCMOS 3.3 V
VD<21> B17 Bidir LVCMOS 3.3 V
VD<22> A17 Bidir LVCMOS 3.3 V
VD<23> B18 Bidir LVCMOS 3.3 V
VD<24> A18 Bidir LVCMOS 3.3 V
VD<25> B20 Bidir LVCMOS 3.3 V
VD<26> A19 Bidir LVCMOS 3.3 V
VD<27> B21 Bidir LVCMOS 3.3 V
VD<28> A20 Bidir LVCMOS 3.3 V
VD<29> B23 Bidir LVCMOS 3.3 V
VD<30> A21 Bidir LVCMOS 3.3 V
VD<31> B24 Bidir LVCMOS 3.3 V

Embedded Solutions Page 31 of 46

VADD<0> C1 Input LVCMOS 3.3 V
VADD<1> C2 Input LVCMOS 3.3 V
VADD<2> C4 Input LVCMOS 3.3 V
VADD<3> C5 Input LVCMOS 3.3 V
VADD<4> C6 Input LVCMOS 3.3 V
VADD<5> C7 Input LVCMOS 3.3 V
VADD<6> C8 Input LVCMOS 3.3 V
VADD<7> D15 Input LVCMOS 3.3 V

V_W D3 Input LVCMOS 3.3 V
V_R D4 Input LVCMOS 3.3 V
VACK D5 Output LVCMOS 3.3 V
VRST D8 Input LVCMOS 3.3 V

VDMA_W0 C11 Input LVCMOS 3.3 V
VDMA_W1 C12 Input LVCMOS 3.3 V
VDMA_R0 D13 Input LVCMOS 3.3 V
VDMA_R1 C14 Input LVCMOS 3.3 V
VDMA_RDY_W0 C17 Output LVCMOS 3.3 V
VDMA_RDY_W1 C19 Output LVCMOS 3.3 V
VDMA_RDY_R0 C15 Output LVCMOS 3.3 V
VDMA_RDY_R1 C16 Output LVCMOS 3.3 V
VDMA_MT_R0 C20 Output LVCMOS 3.3 V
VDMA_MT_R1 C21 Output LVCMOS 3.3 V

VINT0 D6 Output LVCMOS 3.3 V
VINT1 D7 Output LVCMOS 3.3 V
VSTAT<0> D9 Output LVCMOS 3.3 V
VSTAT<1> D10 Output LVCMOS 3.3 V
VSTAT<2> D11 Output LVCMOS 3.3 V
VSTAT<3> D12 Output LVCMOS 3.3 V

VSPARE<0> D16 Input LVCMOS 3.3 V
VSPARE<1> D17 Input LVCMOS 3.3 V
VSPARE<2> D18 Input LVCMOS 3.3 V
VSPARE<3> D19 Input LVCMOS 3.3 V
VSPARE<4> D20 Input LVCMOS 3.3 V
VSPARE<5> D21 Input LVCMOS 3.3 V
VSPARE<6> D22 Input LVCMOS 3.3 V
VSPARE<7> D23 Input LVCMOS 3.3 V
VSPARE<8> D24 Input LVCMOS 3.3 V

Embedded Solutions Page 32 of 46

LED<0> AE18 Bidir LVCMOS 3.3 V
LED<1> AF18 Bidir LVCMOS 3.3 V
LED<2> AC19 Bidir LVCMOS 3.3 V
LED<3> AF19 Bidir LVCMOS 3.3 V

RX_SW_CTRL<0> T26 Output LVCMOS 2.5 V
RX_SW_CTRL<1> P25 Output LVCMOS 2.5 V
RX_SW_CTRL<2> R26 Output LVCMOS 2.5 V
RX_SW_CTRL<3> U26 Output LVCMOS 2.5 V

MISO K26 Input LVCMOS 2.5 V
MOSI L26 Output LVCMOS 2.5 V
S_CK M26 Output LVCMOS 2.5 V

CS_TEMP Y23 Output LVCMOS 3.3 V
SCK_TEMP Y26 Output LVCMOS 3.3 V
DIN_TEMP AB26 Output LVCMOS 3.3 V
DOUT_TEMP AC26 Input LVCMOS 3.3 V

SS_N N25 Output LVCMOS 2.5 V
RF_RST J26 Output LVCMOS 2.5 V
RF_PWC_PWM K25 Output LVCMOS 2.5 V
RF_AGC_PWM M25 Output LVCMOS 2.5 V

GPIO1 AE24 Input LVCMOS 3.3 V
GPIO2 AF24 Input LVCMOS 3.3 V
GPIO3 W23 Input LVCMOS 3.3 V
GPIO4 AA23 Input LVCMOS 3.3 V

DAC_PDWN W26 Output LVCMOS 3.3 V
DAC_MUXSEL V21 Output LVCMOS 3.3 V

DAC_WRT0 AC23 Output LVCMOS 3.3 V
DAC_CLK0 AB23 Output LVCMOS 3.3 V

DAC_WRT1 AB24 Output LVCMOS 3.3 V
DAC_CLK1 AC24 Output LVCMOS 3.3 V

TX_DAC_I<0> AD23 Output LVCMOS 3.3 V
TX_DAC_I<1> AE23 Output LVCMOS 3.3 V
TX_DAC_I<2> AF23 Output LVCMOS 3.3 V
TX_DAC_I<3> V22 Output LVCMOS 3.3 V
TX_DAC_I<4> W22 Output LVCMOS 3.3 V

Embedded Solutions Page 33 of 46

TX_DAC_I<5> Y22 Output LVCMOS 3.3 V
TX_DAC_I<6> AB22 Output LVCMOS 3.3 V
TX_DAC_I<7> AC22 Output LVCMOS 3.3 V
TX_DAC_I<8> AD22 Output LVCMOS 3.3 V
TX_DAC_I<9> AF22 Output LVCMOS 3.3 V

TX_DAC_Q<0> AA26 Output LVCMOS 3.3 V
TX_DAC_Q<1> AD26 Output LVCMOS 3.3 V
TX_DAC_Q<2> W25 Output LVCMOS 3.3 V
TX_DAC_Q<3> Y25 Output LVCMOS 3.3 V
TX_DAC_Q<4> AB25 Output LVCMOS 3.3 V
TX_DAC_Q<5> AC25 Output LVCMOS 3.3 V
TX_DAC_Q<6> AD25 Output LVCMOS 3.3 V
TX_DAC_Q<7> W24 Output LVCMOS 3.3 V
TX_DAC_Q<8> Y24 Output LVCMOS 3.3 V
TX_DAC_Q<9> AA24 Output LVCMOS 3.3 V

ADC_DCS F20 Output LVCMOS 3.3 V
ADC_DFS G23 Output LVCMOS 3.3 V
ADC_MUXSEL G18 Output LVCMOS 3.3 V
ADC_REFSEL E17 Output LVCMOS 3.3 V

ADC_OTR0 F19 Input LVCMOS 3.3 V
ADC_CLK0 H21 Output LVCMOS 3.3 V
ADC_OEB0 G19 Output LVCMOS 3.3 V
ADC_PDWN0 E18 Output LVCMOS 3.3 V

ADC_OTR1 F18 Input LVCMOS 3.3 V
ADC_CLK1 E21 Output LVCMOS 3.3 V
ADC_OEB1 H20 Output LVCMOS 3.3 V
ADC_PDWN1 G20 Output LVCMOS 3.3 V

RX_ADC_I<0> C25 Input LVCMOS 3.3 V
RX_ADC_I<1> D25 Input LVCMOS 3.3 V
RX_ADC_I<2> E25 Input LVCMOS 3.3 V
RX_ADC_I<3> G25 Input LVCMOS 3.3 V
RX_ADC_I<4> H25 Input LVCMOS 3.3 V
RX_ADC_I<5> C26 Input LVCMOS 3.3 V
RX_ADC_I<6> D26 Input LVCMOS 3.3 V
RX_ADC_I<7> E26 Input LVCMOS 3.3 V
RX_ADC_I<8> F26 Input LVCMOS 3.3 V
RX_ADC_I<9> G26 Input LVCMOS 3.3 V
RX_ADC_I<10> H23 Input LVCMOS 3.3 V

Embedded Solutions Page 34 of 46

RX_ADC_I<11> G24 Input LVCMOS 3.3 V
RX_ADC_I<12> H24 Input LVCMOS 3.3 V
RX_ADC_I<13> H26 Input LVCMOS 3.3 V

RX_ADC_Q<0> G21 Input LVCMOS 3.3 V
RX_ADC_Q<1> A22 Input LVCMOS 3.3 V
RX_ADC_Q<2> C22 Input LVCMOS 3.3 V
RX_ADC_Q<3> E22 Input LVCMOS 3.3 V
RX_ADC_Q<4> G22 Input LVCMOS 3.3 V
RX_ADC_Q<5> H22 Input LVCMOS 3.3 V
RX_ADC_Q<6> A23 Input LVCMOS 3.3 V
RX_ADC_Q<7> C23 Input LVCMOS 3.3 V
RX_ADC_Q<8> E23 Input LVCMOS 3.3 V
RX_ADC_Q<9> F23 Input LVCMOS 3.3 V
RX_ADC_Q<10> A24 Input LVCMOS 3.3 V
RX_ADC_Q<11> C24 Input LVCMOS 3.3 V
RX_ADC_Q<12> E24 Input LVCMOS 3.3 V
RX_ADC_Q<13> F24 Input LVCMOS 3.3 V

QDR_CQ U1 Input HSTL_I_DCI 1.8 V
QDR_K P3 Output HSTL_I 1.8 V
QDR_KN P2 Output HSTL_I 1.8 V
QDR_W L4 Output HSTL_I 1.8 V
QDR_R J7 Output HSTL_I 1.8 V

QDR_BWN<0> K7 Output HSTL_I 1.8 V
QDR_BWN<1> K4 Output HSTL_I 1.8 V
QDR_BWN<2> K6 Output HSTL_I 1.8 V
QDR_BWN<3> N2 Output HSTL_I 1.8 V

QDR_IN<0> AD6 Input HSTL_I_DCI 1.8 V
QDR_IN<1> AB5 Input HSTL_I_DCI 1.8 V
QDR_IN<2> AA8 Input HSTL_I_DCI 1.8 V
QDR_IN<3> Y8 Input HSTL_I_DCI 1.8 V
QDR_IN<4> V6 Input HSTL_I_DCI 1.8 V
QDR_IN<5> T6 Input HSTL_I_DCI 1.8 V
QDR_IN<6> P7 Input HSTL_I_DCI 1.8 V
QDR_IN<7> L7 Input HSTL_I_DCI 1.8 V
QDR_IN<8> P8 Input HSTL_I_DCI 1.8 V
QDR_IN<9> AD3 Input HSTL_I_DCI 1.8 V
QDR_IN<10> AC5 Input HSTL_I_DCI 1.8 V
QDR_IN<11> Y5 Input HSTL_I_DCI 1.8 V
QDR_IN<12> W5 Input HSTL_I_DCI 1.8 V

Embedded Solutions Page 35 of 46

QDR_IN<13> U5 Input HSTL_I_DCI 1.8 V
QDR_IN<14> T7 Input HSTL_I_DCI 1.8 V
QDR_IN<15> R7 Input HSTL_I_DCI 1.8 V
QDR_IN<16> K5 Input HSTL_I_DCI 1.8 V
QDR_IN<17> M7 Input HSTL_I_DCI 1.8 V
QDR_IN<18> K2 Input HSTL_I_DCI 1.8 V
QDR_IN<19> M4 Input HSTL_I_DCI 1.8 V
QDR_IN<20> M1 Input HSTL_I_DCI 1.8 V
QDR_IN<21> P4 Input HSTL_I_DCI 1.8 V
QDR_IN<22> T3 Input HSTL_I_DCI 1.8 V
QDR_IN<23> U3 Input HSTL_I_DCI 1.8 V
QDR_IN<24> V2 Input HSTL_I_DCI 1.8 V
QDR_IN<25> AA3 Input HSTL_I_DCI 1.8 V
QDR_IN<26> AC1 Input HSTL_I_DCI 1.8 V
QDR_IN<27> L8 Input HSTL_I_DCI 1.8 V
QDR_IN<28> J2 Input HSTL_I_DCI 1.8 V
QDR_IN<29> R1 Input HSTL_I_DCI 1.8 V
QDR_IN<30> R8 Input HSTL_I_DCI 1.8 V
QDR_IN<31> U4 Input HSTL_I_DCI 1.8 V
QDR_IN<32> V1 Input HSTL_I_DCI 1.8 V
QDR_IN<33> T8 Input HSTL_I_DCI 1.8 V
QDR_IN<34> W4 Input HSTL_I_DCI 1.8 V
QDR_IN<35> AB1 Input HSTL_I_DCI 1.8 V

QDR_OUT<0> AD4 Output HSTL_I 1.8 V
QDR_OUT<1> AD5 Output HSTL_I 1.8 V
QDR_OUT<2> AB6 Output HSTL_I 1.8 V
QDR_OUT<3> Y6 Output HSTL_I 1.8 V
QDR_OUT<4> V7 Output HSTL_I 1.8 V
QDR_OUT<5> U7 Output HSTL_I 1.8 V
QDR_OUT<6> P6 Output HSTL_I 1.8 V
QDR_OUT<7> N5 Output HSTL_I 1.8 V
QDR_OUT<8> N7 Output HSTL_I 1.8 V
QDR_OUT<9> AC6 Output HSTL_I 1.8 V
QDR_OUT<10> Y4 Output HSTL_I 1.8 V
QDR_OUT<11> W6 Output HSTL_I 1.8 V
QDR_OUT<12> V5 Output HSTL_I 1.8 V
QDR_OUT<13> U6 Output HSTL_I 1.8 V
QDR_OUT<14> P5 Output HSTL_I 1.8 V
QDR_OUT<15> N4 Output HSTL_I 1.8 V
QDR_OUT<16> L6 Output HSTL_I 1.8 V
QDR_OUT<17> J6 Output HSTL_I 1.8 V
QDR_OUT<18> M2 Output HSTL_I 1.8 V

Embedded Solutions Page 36 of 46

QDR_OUT<19> L3 Output HSTL_I 1.8 V
QDR_OUT<20> M8 Output HSTL_I 1.8 V
QDR_OUT<21> R4 Output HSTL_I 1.8 V
QDR_OUT<22> R2 Output HSTL_I 1.8 V
QDR_OUT<23> T4 Output HSTL_I 1.8 V
QDR_OUT<24> Y3 Output HSTL_I 1.8 V
QDR_OUT<25> W2 Output HSTL_I 1.8 V
QDR_OUT<26> Y2 Output HSTL_I 1.8 V
QDR_OUT<27> K1 Output HSTL_I 1.8 V
QDR_OUT<28> L1 Output HSTL_I 1.8 V
QDR_OUT<29> N3 Output HSTL_I 1.8 V
QDR_OUT<30> T1 Output HSTL_I 1.8 V
QDR_OUT<31> V4 Output HSTL_I 1.8 V
QDR_OUT<32> W1 Output HSTL_I 1.8 V
QDR_OUT<33> Y1 Output HSTL_I 1.8 V
QDR_OUT<34> AA1 Output HSTL_I 1.8 V
QDR_OUT<35> AD1 Output HSTL_I 1.8 V

QDR_ADDR<0> M6 Output HSTL_I 1.8 V
QDR_ADDR<1> J4 Output HSTL_I 1.8 V
QDR_ADDR<2> J5 Output HSTL_I 1.8 V
QDR_ADDR<3> K3 Output HSTL_I 1.8 V
QDR_ADDR<4> M5 Output HSTL_I 1.8 V
QDR_ADDR<5> AA4 Output HSTL_I 1.8 V
QDR_ADDR<6> AC2 Output HSTL_I 1.8 V
QDR_ADDR<7> AC3 Output HSTL_I 1.8 V
QDR_ADDR<8> AB3 Output HSTL_I 1.8 V
QDR_ADDR<9> AB4 Output HSTL_I 1.8 V
QDR_ADDR<10> AE4 Output HSTL_I 1.8 V
QDR_ADDR<11> AC4 Output HSTL_I 1.8 V
QDR_ADDR<12> AE3 Output HSTL_I 1.8 V
QDR_ADDR<13> AD2 Output HSTL_I 1.8 V
QDR_ADDR<14> AF3 Output HSTL_I 1.8 V
QDR_ADDR<15> AE6 Output HSTL_I 1.8 V
QDR_ADDR<16> AF4 Output HSTL_I 1.8 V
QDR_ADDR<17> AF6 Output HSTL_I 1.8 V

RD_STB_IN AF8 Input HSTL_I_DCI 1.8 V
RD_STB_OUT AF7 Output HSTL_I 1.8 V

PLL_REF G1 Output LVCMOS 3.3 V
PLL_SCLK F1 Output LVCMOS 3.3 V
PLL_S2 G2 Output LVCMOS 3.3 V

Embedded Solutions Page 37 of 46

PLL_SDAT E1 Bidir LVCMOS 3.3 V

PLL_CLKA D2 Input LVCMOS 3.3 V
PLL_CLKB D1 Input LVCMOS 3.3 V

D7_0 AF20 Output LVCMOS 3.3 V
D7_1 AB20 Output LVCMOS 3.3 V
D7_2 W21 Output LVCMOS 3.3 V

Embedded Solutions Page 38 of 46

D9_0 J25 Output LVCMOS 2.5 V
D9_1 L21 Output LVCMOS 2.5 V
D9_2 M21 Output LVCMOS 2.5 V
D9_3 K24 Output LVCMOS 2.5 V
D9_4 L24 Output LVCMOS 2.5 V
D9_5 M24 Output LVCMOS 2.5 V
D9_6 N24 Output LVCMOS 2.5 V
D9_7 P24 Output LVCMOS 2.5 V
D9_8 J23 Output LVCMOS 2.5 V
D9_9 K23 Output LVCMOS 2.5 V
D9_10 L23 Output LVCMOS 2.5 V
D9_11 M23 Output LVCMOS 2.5 V
D9_12 N23 Output LVCMOS 2.5 V
D9_13 P23 Output LVCMOS 2.5 V
D9_14 V23 Output LVCMOS 2.5 V
D9_15 J22 Output LVCMOS 2.5 V
D9_16 K22 Output LVCMOS 2.5 V
D9_17 M22 Output LVCMOS 2.5 V
D9_18 N22 Output LVCMOS 2.5 V
D9_19 P22 Output LVCMOS 2.5 V
D9_20 J21 Output LVCMOS 2.5 V
D9_21 K21 Output LVCMOS 2.5 V
D9_22 V25 Output LVCMOS 2.5 V
D9_23 V26 Output LVCMOS 2.5 V
D9_24 R23 Output LVCMOS 2.5 V
D9_25 R24 Output LVCMOS 2.5 V
D9_26 R25 Output LVCMOS 2.5 V
D9_27 U22 Output LVCMOS 2.5 V
D9_28 U23 Output LVCMOS 2.5 V
D9_29 U24 Output LVCMOS 2.5 V
D9_30 U25 Output LVCMOS 2.5 V

I/O Standard Acronyms:
LVCMOS – Low Voltage Complimentary Metal Oxide Semiconductor
HSTL_I – High-speed Transceiver Logic Class I
DCI – Digitally Controlled Impedance

The pin names match with the schematic names and the names found throughout this
manual. The engineering kit contains a reference project with the pin numbers defined
and the bus interfaces implemented. A lot of time will be saved on the first
implementation starting with the reference design. The pin list and following definitions
are for those who want to “do it themselves”.

Embedded Solutions Page 39 of 46

Transition Module Mechanical Drawing

Embedded Solutions Page 40 of 46

Mezzanine Module Connector J1

RX_SW_CTRL3 D9_24 50 51
RX_SW_CTRL0 D9_25 49 52
RX_SW_CTRL2 D9_26 48 53
RX_SW_CTRL1 GND 47 54
GND ADC_CLK0 46 55
GND GND 45 56
ADC_REFSEL D9_27 44 57
ADC_MUXSEL D9_28 43 58
ADC_PDWN0 D9_29 42 59
ADC_OEB0 D9_30 41 60
ADC_OTR0 GND 40 61
GND RX_ADC_I13 39 62
D9_23 RX_ADC_I12 38 63
D9_22 RX_ADC_I11 37 64
D9_21 RX_ADC_I10 36 65
D9_20 RX_ADC_I9 35 66
D9_19 RX_ADC_I8 34 67
D9_18 RX_ADC_I7 33 68
D9_17 RX_ADC_I6 32 69
D9_16 RX_ADC_I5 31 70
D9_15 RX_ADC_I4 30 71
D9_14 RX_ADC_I3 29 72
D9_13 RX_ADC_I2 28 73
D9_12 RX_ADC_I1 27 74
GND RX_ADC_I0 26 75
ADC_OTR1 GND 25 76
GND RX_ADC_Q13 24 77
D9_11 RX_ADC_Q12 23 78
D9_10 RX_ADC_Q11 22 79
D9_9 RX_ADC_Q10 21 80
D9_8 RX_ADC_Q9 20 81
D9_7 RX_ADC_Q8 19 82
D9_6 RX_ADC_Q7 18 83
D9_5 RX_ADC_Q6 17 84
D9_4 RX_ADC_Q5 16 85
D9_3 RX_ADC_Q4 15 86
D9_2 RX_ADC_Q3 14 87
D9_1 RX_ADC_Q2 13 88
D9_0 RX_ADC_Q1 12 89
GND RX_ADC_Q0 11 90
ADC_0EB1 GND 10 91
ADC_PDWN1 ADC_DFS 9 92
ADC_DCS GND 8 93
GND ADC_CLK1 7 94
SS_N GND 6 95
SCK GND 5 96
MOSI RF_ADC_PWM 4 97
MISO GND 3 98
RF_RST RF_PWR_CTRL_PWM 2 99
GND GND 1 100

FIGURE 22 PMC-XM MEZZANINE CONNECTOR J1 PINOUT

Embedded Solutions Page 41 of 46

Mezzanine Module Connector J2

D7_2 GND 50 51
DAC_MUXSEL GND 49 52
GND GND 48 53
TX_DAC_I9 GND 47 54
TX_DAC_I8 GND 46 55
TX_DAC_I7 GND 45 56
TX_DAC_I6 GND 44 57
TX_DAC_I5 GND 43 58
TX_DAC_I4 GND 42 59
TX_DAC_I3 GND 41 60
TX_DAC_I2 GND 40 61
TX_DAC_I1 GND 39 62
TX_DAC_I0 GND 38 63
GND GND 37 64
GND GND 36 65
DAC_WRT0 GND 35 66
GND GND 34 67
DAC_CLK0 GND 33 68
GND GND 32 69
D7_1 GND 31 70
GPIO4 GND 30 71
GPIO3 GND 29 72
GPIO2 GND 28 73
GPIO1 GND 27 74
D7_0 GND 26 75
GND GND 25 76
DAC_CLK1 GND 24 77
GND GND 23 78
DAC_WRT1 GND 22 79
GND GND 21 80
GND GND 20 81
TX_DAC_Q9 GND 19 82
TX_DAC_Q8 GND 18 83
TX_DAC_Q7 GND 17 84
TX_DAC_Q6 GND 16 85
TX_DAC_Q5 GND 15 86
TX_DAC_Q4 GND 14 87
TX_DAC_Q3 GND 13 88
TX_DAC_Q2 GND 12 89
TX_DAC_Q1 GND 11 90
TX_DAC_Q0 GND 10 91
GND GND 9 92
DAC_PDWN GND 8 93
GND GND 7 94
GND GND 6 95
filtered +5v filtered +5v 5 96
filtered +5v filtered +5v 4 97
filtered +5v filtered +5v 3 98
filtered +5v filtered +5v 2 99
filtered +5v filtered +5v 1 100

FIGURE 23 PMC-XM MEZZANINE CONNECTOR J2 PINOUT

Embedded Solutions Page 42 of 46

Applications Guide

Interfacing

Some general interfacing guidelines are presented below. Do not hesitate to contact
the factory if you need more assistance.

ESD

Proper ESD handling procedures must be followed when handling the PMC-XM. The
card is shipped in an anti-static, shielded bag. The card should remain in the bag until
ready for use. When installing the card the installer must be properly grounded and the
hardware should be on an anti-static work-station.

Start-up

Make sure that the "system" can see your hardware before trying to access it. Many
BIOS will display the PCI devices found at boot up on a "splash screen" with the
VendorID and CardId and an interrupt level. Look quickly! If the information is not
available from the BIOS then a third party PCI device cataloging tool will be helpful. We
use PCIView.

Watch the system grounds. All electrically connected equipment should have a fail­safe common ground that is large enough to handle all current loads without affecting
noise immunity. Power supplies and power consuming loads should all have their own
ground wires back to a common point.

We provide the components. You provide the system. Only careful planning and
practice can achieve safety and reliability. Inputs can be damaged by static discharge,
or by applying voltage outside of the device rated voltages.

Embedded Solutions Page 43 of 46

Construction and Reliability

PMC Modules were conceived and engineered for rugged industrial environments. The
PMC-XM is constructed out of 0.062-inch thick FR4 material.

Surface-mount components are used. The PMC connectors are rated at 1 Amp per pin,
100 insertion cycles minimum. These connectors make consistent, correct insertion
easy and reliable.

The PMC is secured against the carrier with four screws attached to the 2 stand-offs
and 2 locations on the front panel. The four screws provide significant protection
against shock, vibration, and incomplete insertion.

The PMC Module provides a low temperature coefficient of 2.17 W/°C for uniform heat.
This is based upon the temperature coefficient of the base FR4 material of 0.31 W/m-

°C, and taking into account the thickness and area of the PMC. The coefficient means
that if 2.17 Watts are applied uniformly on the component side, then the temperature

difference between the component side and solder side is one degree Celsius.

Thermal Considerations

The PMC-XM design consists of CMOS circuits. The power dissipation due to internal
circuitry is very low. It is possible to create higher power dissipation with the externally
connected logic. If more than one Watt is required to be dissipated due to external
loading, then forced-air cooling is recommended. With the one degree differential
temperature to the solder side of the board, external cooling is easily accomplished.

Embedded Solutions Page 44 of 46

Warranty and Repair

Please refer to the warranty page on our website for the current warranty offered and
options.

http://www.dyneng.com/warranty.html

Service Policy

Before returning a product for repair, verify as well as possible that the suspected unit is
at fault. Then call the Customer Service Department for a RETURN MATERIAL
AUTHORIZATION (RMA) number. Carefully package the unit, in the original shipping
carton if this is available, and ship prepaid and insured with the RMA number clearly
written on the outside of the package. Include a return address and the telephone
number of a technical contact. For out-of-warranty repairs, a purchase order for repair
charges must accompany the return. Dynamic Engineering will not be responsible for
damages due to improper packaging of returned items. For service on Dynamic
Engineering Products not purchased directly from Dynamic Engineering contact your
reseller. Products returned to Dynamic Engineering for repair by other than the original
customer will be treated as out-of-warranty.

Out of Warranty Repairs

Out of warranty repairs will be billed on a material and labor basis. The current
minimum repair charge is $100. Customer approval will be obtained before repairing
any item if the repair charges will exceed one half of the quantity one list price for that
unit. Return transportation and insurance will be billed as part of the repair and is in
addition to the minimum charge.

For Service Contact:

Customer Service Department
Dynamic Engineering
150 DuBois, Suite 3
Santa Cruz, CA 95060
[phone] Fax [phone]

[e-mail]

Embedded Solutions Page 45 of 46

Specifications

Host Interface: 33 MHz/32-bit PCI Mezzanine Card

Access types: Configuration and Memory space utilized

Clock rates supported: 33 MHz. PMC, 33 MHz data transfer between Spartan3 and Virtex

Local 40 MHz oscillator for PLL reference to provide two programmable
frequencies

Memory FIFO memory is provided to support DMA Four 4K x 32-bit FIFOs on Spartan3

and four 4K x 32-bit FIFOs on Virtex

Plug-in Module Interface: Two 100-pin FX8-100S-SV mezzanine connectors

Software Interface: Control/Status Registers within Spartan3 and Virtex

Initialization: Hardware reset forces all registers to zero except as noted

Access Modes: All registers on long-word boundary - Standard target accesses read and write to

registers and memory - DMA access to memory

Access Time: No wait states in DMA modes, One wait state in target access to Spartan3

Virtex accesses are user defined

Interrupt: One interrupt to the PCI bus is supported with multiple sources. The interrupts

are maskable and are supported with status registers.

Onboard Options: All Options are Software Programmable.

Dimensions: Standard Single PMC Module

Construction: FR4 Multi-Layer Printed Circuit, Surface Mount Components

Power: 5V and 3.3V from PCI bus. Local 2.5V, 1.8V and 1.2V created with on-

board power supplies

User 8 position software readable switch

4 software controllable LEDs
2 Power LEDs

Embedded Solutions Page 46 of 46

Order Information

PMC-XM http://www.dyneng.com/pmc_xm.html

Standard version with two 16KB FIFOs per channel,
standard XM timing and protocol.

PMC-XM-Eng-1 Engineering Kit for the PMC-XM

Board-level schematics (PDF) and Sample Virtex
design (VHDL)

PMC-XM-Eng-2 Engineering Kit for the PMC-XM

Board-level schematics [PDF], Sample Virtex Design
(VHDL), Software Drivers and Sample Test
Application

All information provided is Copyright Dynamic Engineering