Dynamic Engineering PMC-PARALLEL-TTL User Manual

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DYNAMIC ENGINEERING

150 DuBois St. Suite 3, Santa Cruz, Ca 95060

831-457-8891 Fax [phone]

http://www.dyneng.com

[e-mail]

Est. 1988

User Manual

PMC-PARALLEL-TTL

Digital Parallel Interface

PMC Module

Revision A1

Corresponding Hardware: Revision 1

10-2007-0101

FLASH 0101

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PMC-PARALLEL-TTL

Digital Parallel Interface

PMC Module

Dynamic Engineering

150 DuBois St. Suite 3, Santa Cruz CA 95060

831-457-8891 831-457-4793 FAX

This document contains information of proprietary interest to Dynamic Engineering. It
has been supplied in confidence and the recipient, by accepting this material, agrees
that the subject matter will not be copied or reproduced, in whole or in part, nor its
contents revealed in any manner or to any person except to meet the purpose for which
it was delivered.

Dynamic Engineering has made every effort to ensure that this manual is accurate and
complete. Still, the company reserves the right to make improvements or changes in the
product described in this document at any time and without notice. Furthermore,
Dynamic Engineering assumes no liability arising out of the application or use of the
device described herein.

The electronic equipment described herein generates, uses,
and can radiate radio frequency energy. Operation of this equipment in a residential
area is likely to cause radio interference, in which case the user, at his own expense,
will be required to take whatever measures may be required to correct the interference.

Dynamic Engineering’s products are not authorized for use as critical components in life
support devices or systems without the express written approval of the president of
Dynamic Engineering.

This product has been designed to operate with PMC Module carriers and compatible
user-provided equipment. Connection of incompatible hardware is likely to cause
serious damage.

©2007 by Dynamic Engineering.
Other trademarks and registered trademarks are owned by their respective manufacturers.
Manual Revision A1. Revised 9/4/07

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Table of Contents

PRODUCT DESCRIPTION 6

THEORY OF OPERATION 9

ADDRESS MAP 11

PROGRAMMING 12

Register Definitions 13

pmcparttl_BASE 13
pmcparttl_ID 14
pmcparttl_STATUS 15
pmcparttl_DirL 16
pmcparttl_DirU 16
pmcparttl_DatL 17
pmcparttl_DatU 17
pmcparttl_DatLreg 18
pmcparttl_DatUreg 18
pmcparttl_COSclk 19
pmcparttl_RisLreg 20
pmcparttl_RisUreg 20
pmcparttl_FallLreg 21
pmcparttl_FallUreg 21
pmcparttl_IntRisLreg 22
pmcparttl_IntRisUreg 22
pmcparttl_IntFallLreg 23
pmcparttl_IntFallUreg 23
pmcparttl_IntRisLstat 24
pmcparttl_IntRisUstat 24
pmcparttl_IntRisLstat 25
pmcparttl_IntRisUstat 25

PMC MODULE LOGIC INTERFACE PIN ASSIGNMENT 26

PMC MODULE LOGIC INTERFACE PIN ASSIGNMENT 27

PMC MODULE FRONT PANEL IO INTERFACE PIN ASSIGNMENT 28

PMC MODULE BACKPLANE IO INTERFACE PIN ASSIGNMENT 29

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APPLICATIONS GUIDE 30

Interfacing 30

Construction and Reliability 31

Thermal Considerations 32

Service Policy 33

Out of Warranty Repairs 33

SPECIFICATIONS 34

ORDER INFORMATION 35

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List of Figures

FIGURE 1 PMC-PARALLEL-TTL REAR VIEW 7
FIGURE 2 PMC-PARALLEL-TTL BLOCK DIAGRAM 10
FIGURE 3 PMC-PARALLEL-TTL INTERNAL ADDRESS MAP 11
FIGURE 4 PMC-PARALLEL-TTL CONTROL PORT 0 BIT MAP 13
FIGURE 5 PMC-PARALLEL-TTL ID AND SWITCH BIT MAP 14
FIGURE 6 PMC-PARALLEL-TTL STATUS PORT BIT MAP 15
FIGURE 7 PMC-PARALLEL-TTL DIRECTION LOWER BIT MAP 16
FIGURE 8 PMC-PARALLEL-TTL DIRECTION UPPER BIT MAP 16
FIGURE 9 PMC-PARALLEL-TTL DATA IO LOWER BIT MAP 17
FIGURE 10 PMC-PARALLEL-TTL DATA IO UPPER BIT MAP 17
FIGURE 11 PMC-PARALLEL-TTL DATA REG LOWER BIT MAP 18
FIGURE 12 PMC-PARALLEL-TTL DATA REG UPPER BIT MAP 18
FIGURE 13 PMC-PARALLEL-TTL COS CLK CONTROL BIT MAP 19
FIGURE 14 PMC-PARALLEL-TTL RISING LOWER BIT MAP 20
FIGURE 15 PMC-PARALLEL-TTL RISING UPPER BIT MAP 20
FIGURE 16 PMC-PARALLEL-TTL FALLING LOWER BIT MAP 21
FIGURE 17 PMC-PARALLEL-TTL FALLING UPPER BIT MAP 21
FIGURE 18 PMC-PARALLEL-TTL INT RISING LOWER BIT MAP 22
FIGURE 19 PMC-PARALLEL-TTL INT RISING UPPER BIT MAP 22
FIGURE 20 PMC-PARALLEL-TTL INT FALLING LOWER BIT MAP 23
FIGURE 21 PMC-PARALLEL-TTL INT FALLING UPPER BIT MAP 23
FIGURE 22 PMC-PARALLEL-TTL RISING COS STATUS LOWER 24
FIGURE 23 PMC-PARALLEL-TTL RISING COS STATUS UPPER 24
FIGURE 24 PMC-PARALLEL-TTL FALLING COS STATUS LOWER 25
FIGURE 25 PMC-PARALLEL-TTL FALLING COS STATUS UPPER 25
FIGURE 26 PMC-PARALLEL-TTL PN1 INTERFACE 26
FIGURE 27 PMC-PARALLEL-TTL PN2 INTERFACE 27
FIGURE 28 PMC-PARALLEL-TTL FRONT PANEL INTERFACE 28
FIGURE 29 PMC-PARALLEL-TTL PN4 INTERFACE 29

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Product Description

In embedded systems many of the interconnections are made with single ended TTL or
CMOS level signals. Depending on the system architecture an IP or a PMC will be the
right choice to make the connection. With most architectures you have a choice as
there are carriers for cPCI, PCI, VME, PC/104p and other buses for both PMC and IP
mezzanine modules.

Usually the choice is based on other system constraints as both the PMC and IP can
provide the IO you require. Dynamic Engineering would be happy to assist in your
decision regarding architecture and other trade-offs with the PMC / IP decision.
Dynamic Engineering has carriers for IP and PMC modules for most architectures, and
is adding more as new solutions are requested and required by our customers.

If you are interested in an IP module solution please refer to the IP-Parallel-IO.

PMC-Parallel-TTL is an upgrade for the PMC-Parallel-IO. After 8 years of production,
numerous updates to handle obsolete parts, and new customer requirements it is time
for an updated design. The PMC Parallel IO is still available for clients who have
designed it into their systems. The PMC Parallel TTL is recommended for new systems
and to upgrade current designs. The connector pinouts are retained for ease of system
migration.

The PMC compatible PMC-Parallel-TTL has 64 independent digital IO. The high density
makes efficient use of PMC slot resources. The IO is available for system connection
through the front panel, via the rear [Pn4] connector, or both. A high density 68 pin
SCSI III front panel connector provides the front panel IO. The IO lines can be
protected with optional transorbs. The rear panel IO has a PIM and PIM Carrier
available for rear panel wiring options.

The HDEterm68 http://www.dyneng.com/HDEterm68.html
can be used as a breakout for the front or rear panel IO. The HDEcabl68 provides a
convenient cable. http://www.dyneng.com/HDEcabl68.html Custom cables can be
manufactured to your requirements. Please contact Dynamic Engineering with your
specifications.

Each channel is programmable to be input or output on a channel-by-channel basis. All
64 IO channels can be used as interrupt generators. Interrupts are programmable to be
based on rising, falling and change of state [both] conditions. The interrupts are
maskable to allow polled operation as well.

The inputs are available unfiltered and after the transition detection. The transition
detection is programmable for clock rate. The local 50 MHz oscillator, PCI or external
clocks can be selected as the reference to the clock divider. The clock divider is

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programmable to use the reference rate or to divide it to a lower frequency. An optional
PLL capability is available for users who require more extensive frequency options.

All of the IO are routed through the FPGA to allow for custom applications that require
hardware intervention or specific timing- for example an automatic address or data
strobe to be generated. The initial model is register based. The design is DMA
capable and can be used for more intensive applications of data capture or delivery.
Please contact Dynamic Engineering with your requirements.

The IO are driven with open-drain high current drivers. When enabled, the high side is
driven with the device and augmented with pull-up resistors. When disabled the output
is pulled high with the resistors unless another device on the line is driving that line low.
The low side of the driver can sink 64+ mA. The high side drive is a few mA. All IO
have 2 pull-up locations per line. The default is for 470 ohms installed into one location.
The multiple locations allow for pull-up strengths greater than 470 ohms, and to stay
within the resistor pack wattage capabilities. The multiple packs also allow for parallel
combinations to create more options of specific pull-up values. For custom models with
additional pull-ups or alternate values please contact Dynamic Engineering. The two
columns of pull-up resistor locations are visible on the rear of the card.

Figure 1 PMC-PARALLEL-TTL REAR VIEW

The registers are mapped as 32 bit words and support byte, word and 32 bit access. All
registers are read-writeable. The Windows® compatible [XP/2000] driver is available to
provide the system level interface for this design. Use standard C/C++ to control your
hardware or use the Hardware manual to make your own software interface. The
software manual is also available on-line.

The basic functions of parallel IO and COS capture are designed into the base model.
Additional features will be added to the base model by using a mux on the output side to
allow software to select the base or extended features. Data bit 0 is the first extended
feature and is a programmable output for the COS reference clock. With software the
output definition can be changed to drive the COS clock onto Data 0. The user can use
a scope to check that their set-up is what they want it to be and then likely return it to
being a data bit. You can leave is as a clock if desired. Additional features will be
incorporated into the base design in a manner where the default is the initial base

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design => to prevent updates from conflicting with existing software. The FLASH on the
current boards will be able to be updated to use the new features in most cases.

PMC-PARALLEL-TTL is part of the PMC Module family of modular I/O components.
The PMC-PARALLEL-TTL conforms to the PMC standard. This guarantees
compatibility with multiple PMC Carrier boards. Because the PMC may be mounted on
different form factors, while maintaining plug and software compatibility, system
prototyping may be done on one PMC Carrier board, with final system implementation
on a different one.

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Theory of Operation

The PMC-PARALLEL-TTL can be used for multiple purposes with applications in
telecommunications, control, sensors, IO, test; anywhere multiple independent IO are
useful.

The PMC-PARALLEL-TTL features a Xilinx FPGA, and high current LVTH driver
devices. The FPGA contains the PCI interface and control required for the parallel
interface.

The Xilinx design incorporates the “PCI Core” and additional modules for DMA in
parallel with a direct register decoded programming model. The initial implementation
provides an enhanced feature set based on the PMC Parallel IO design. Additional
FLASH updates will provide DMA, pattern generation, pulse generation, and user
defined requirements.

The drivers are initialized to the off state and pull-ups on board hold the IO lines in the
‘high’ state. The direction registers are used to program the channel to be a driver or
not. The receivers are always enabled allowing local read-back of the transmitted data.

Data written to the IO registers can be placed on the bus. The master enable allows all
64 channels to be synchronized if desired. The master enable can be programmed “on”
to allow direct updates if 64 bit synchronization is not required.

For an IO with the direction bit set and master enabled: When a ‘0’ is written to any IO
line register position the corresponding line is driven low. When a ‘1’ is written to any IO
line register position that line is un-driven by the local driver and the output level will be
controlled by the termination resistor, and any other drivers attached to that line. The
control register is read-writeable. The data register read corresponds to the IO side.
The register read-back is at an alternate address offset. The register read-back is
independent of the bus; the data read will always match the data written. The IO data
read will reflect the state of the bus and not necessarily the state of the on-board
drivers.

The read-back registers are clocked at a programmable rate with an internal clock
generator. If desired the internal clock can be replaced with an external source and an
enable. The basic option is available under SW control. If special programming is
needed please contact Dynamic Engineering for a custom FPGA implementation.

All the IO control and registers are instantiated within the FPGA, only the drivers and
receivers are separate devices. If desired, the IO lines can be specially programmed
to create custom timing pulses etc. For example if the interface is to put out an address

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and then an address qualifier to strobe the address into the receiving hardware one of
the IO lines can be programmed to create a pulse some time after the address for the
IO registers is written to. The custom pulse will be more accurate for delay and duration
than a SW timing solution. The number of accesses to the card can be reduced as well
having the effect of greater through-put. Please contact Dynamic Engineering with your
requirements.

Figure 2 PMC-PARALLEL-TTL Block Diagram

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Address Map

Function Offset

// PMC Parallel TTL definitions
#define pmcparttl_BASE 0x0000 // 0 PMC Parallel TTL base control register offset
#define pmcparttl_ID 0x0004 // 1 PMC Parallel TTL ID Register offset
#define pmcparttl_STATUS 0x0008 // 2 PMC Parallel TTL status Register offset
#define pmcparttl_DirL 0x000c // 3 PMC Parallel TTL Direction lower Register offset
#define pmcparttl_DirU 0x0010 // 4 PMC Parallel TTL Direction upper Register offset
#define pmcparttl_DatL 0x0014 // 5 PMC Parallel TTL Data lower Register, line data read
#define pmcparttl_DatU 0x0018 // 6 PMC Parallel TTL Data upper Register, line data read
#define pmcparttl_DatLreg 0x001c // 7 PMC Parallel TTL Data lower Register read-back
#define pmcparttl_DatUreg 0x0020 // 8 PMC Parallel TTL Data upper Register read-back
#define pmcparttl_COSclk 0x0024 // 9 PMC Parallel TTL COS Clock definition Register
//#define spare 0x0028 // 10 PMC Parallel TTL
#define pmcparttl_RisLreg 0x002c // 11 PMC Parallel TTL Rising lower Register
#define pmcparttl_RisUreg 0x0030 // 12 PMC Parallel TTL Rising upper Register
#define pmcparttl_FallLreg 0x0034 // 13 PMC Parallel TTL Falling lower Register
#define pmcparttl_FallUreg 0x0038 // 14 PMC Parallel TTL Falling upper Register
#define pmcparttl_IntRisLreg 0x003c // 15 PMC Parallel TTL Interrupt Enable Rising lower Register
#define pmcparttl_IntRisUreg 0x0040 // 16 PMC Parallel TTL Interrupt Enable Rising upper Register
#define pmcparttl_IntFallLreg 0x0044 // 17 PMC Parallel TTL Interrupt Enable Falling lower Register
#define pmcparttl_IntFallUreg 0x0048 // 18 PMC Parallel TTL Interrupt Enable Falling upper Register
#define pmcparttl_IntRisLstat 0x004c // 19 PMC Par TTL Interrupt Rising LWR Stat Rd, write = clear
#define pmcparttl_IntRisUstat 0x0050 // 20 PMC Par TTL Interrupt Rising UPR Stat Rd, write = clear
#define pmcparttl_IntFallLstat 0x0054 // 21 PMC Par TTL Interrupt Falling LWR Stat Rd, write = clear
#define pmcparttl_IntFallUstat 0x0058 // 22 PMC Par TTL Interrupt Falling UPR Stat Rd, write = clear

Figure 3 PMC-PARALLEL-TTL Internal Address Map

The address map provided is for the local decoding performed within PMC-Parallel-TTL.
The addresses are all offsets from a base address. The carrier board that the PMC is
installed into provides the base address. Dynamic Engineering prefers a long-word
oriented approach because it is more consistent across platforms.

The map is presented with the #define style to allow cutting and pasting into many
compilers “include” files.

The host system will search the PCI bus to find the assets installed during power-on
initialization. The VendorId = 0x10EE and the CardId = 0x2C for the PMC-Parallel-TTL.