Dynamic Engineering PMC BISERIAL-II PS2 User Manual

DYNAMIC ENGINEERING

435 Park Dr., Ben Lomond, Calif. 95005

831-336-8891 Fax [phone]

[e-mail]

www.dyneng.com

Est. 1988

User Manual

PMC BiSerial-II PS2

4 channel

Bi-directional Serial Data Interface

PMC Module

Revision A

Corresponding Hardware: Revision A

10-2002-1201

PMC BiSerial-II PS2

t

Bi-Directional Serial Data
Interface
PMC Module

Dynamic Engineering
435 Park Drive
Ben Lomond, CA 95005
831-336-8891
831-336-3840 FAX

This document contains information of proprietary
interest to Dynamic Engineering. It has been supplied
in confidence and the recipient, by accepting this
material, agrees that the subject matter will not be
copied or reproduced, in whole or in part, nor its
contents revealed in any manner or to any person
except to meet the purpose for which it was delivered.

Dynamic Engineering has made every effort to ensure

hat this manual is accurate and complete. Still, the
company reserves the right to make improvements or
changes in the product described in this document at
any time and without notice. Furthermore, Dynamic
Engineering assumes no liability arising out of the
application or use of the device described herein.

The electronic equipment described herein generates,
uses, and can radiate radio frequency energy.
Operation of this equipment in a residential area is
likely to cause radio interference, in which case the
user, at his own expense, will be required to take
whatever measures may be required to correct the
interference.

Dynamic Engineering’s products are not authorized for
use as critical components in life support devices or
systems without the express written approval of the
president of Dynamic Engineering.

This product has been designed to operate with PMC
Module carriers and compatible user-provided

©2004 by Dynamic Engineering.

Other trademarks and registered trademarks are
owned by their respective manufactures.
Revised October 9, 2004.

equipment. Connection of incompatible hardware is
likely to cause serious damage.

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Table of Contents

PRODUCT DESCRIPTION 6

THEORY OF OPERATION 10

ADDRESS MAP 13

PROGRAMMING 14

REGISTER DEFINITIONS 15

BIS2_BASE 15
BIS2_TX 16
BIS2_TXs 17
BIS2_RX 18
BIS2_PARDAT 19

BIS2_STAT0 20

BIS2_STAT1 22
BIS2_COSEN 24

BIS2_FIFOTX0-3 25

BIS2_FIFORX0-3 25
BIS2_DIR_TERM 26
BIS2_COSEDGE 28

Interrupts 29

Loop-back 30

PMC PCI PN1 INTERFACE PIN ASSIGNMENT 31

PMC PCI PN2 INTERFACE PIN ASSIGNMENT 32

BISERIAL II FRONT PANEL IO PIN ASSIGNMENT 33

APPLICATIONS GUIDE 34

Interfacing 34

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CONSTRUCTION AND RELIABILITY 35

THERMAL CONSIDERATIONS 35

WARRANTY AND REPAIR 36

SERVICE POLICY 36

OUT OF WARRANTY REPAIRS 36

FOR SERVICE CONTACT: 36

SPECIFICATIONS 37

ORDER INFORMATION 38

SCHEMATICS 38

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List of Figures

FIGURE 1 PMC BISERIAL-II BLOCK DIAGRAM 6
FIGURE 2 PMC BISERIAL-II PS2 BLOCK DIAGRAM 7
FIGURE 3 PS2 TIMING DIAGRAM 11
FIGURE 4 PMC BISERIAL-II PS2 INTERNAL ADDRESS MAP 13
FIGURE 5 PMC BISERIAL-II BASE CONTROL REGISTER BIT MAP 15
FIGURE 6 PMC BISERIAL-II INTERRUPT ENABLE REGISTER BIT MAP 16
FIGURE 7 PMC BISERIAL-II TX CONTROL REGISTER BIT MAP 17
FIGURE 8 PMC BISERIAL-II RX CONTROL REGISTER BIT MAP 18
FIGURE 9 PMC BISERIAL-II PARALLEL OUTPUT DATA BIT MAP 19
FIGURE 10 PMC BISERIAL-II STATUS REG 0 BIT MAP 20
FIGURE 11 PMC BISERIAL-II STATUS 1 BIT MAP 22
FIGURE 12 PMC BISERIAL-II COSEN REGISTER BIT MAP 24
FIGURE 13 PMC BISERIAL-II DIRECTION TERMINATION CONTROL BIT MAP 26
FIGURE 14 PMC BISERIAL-II COSEDGE REGISTER BIT MAP 28
FIGURE 15 PMC BISERIAL-II PN1 INTERFACE 31
FIGURE 16 PMC BISERIAL-II PN2 INTERFACE 32
FIGURE 17 PMC BISERIAL-II FRONT PANEL INTERFACE 33

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Product Description

The PMC BiSerial-II PS2 is part of the PMC Module family of modular I/O
components by Dynamic Engineering. The PMC BiSerial-II is capable of providing
multiple serial protocols. The PS2 protocol implemented provides 4 serially
encoded inputs and outputs plus 8 IO with Change of State interrupt capability.

Other custom interfaces are available. We will redesign the state machines and
create a custom interface protocol. That protocol will then be offered as a
“standard” special order product. Please see our web page for current protocols
offered. Please contact Dynamic Engineering with your custom application.

485 buffers
termination

State

Machine

B

FIFO B

128K x 32

State

Machine

A

FIFO A

128K x 32

Data Flow

Control

PCI IF

FIGURE 1 PMC BISERIAL-II BLOCK DIAGRAM

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The standard configuration shown in Figure one makes use of two external [to the
Xilinx ] FIFOs. The FIFOs can be as large as 128K deep x 32 bits wide. Some
designs do not require so much memory and are more efficiently implemented
using the internal FIFOs.

485 buffers
termination

State

Machine

RX

FIFO RX

128 x 32

x4

x4

Data Flow

Control

PCI IF

State

Machine

TX

FIFO TX

128 x 32

x4

Parallel Port

8 IO

COS Int

x4

FIGURE 2 PMC BISERIAL-II PS2 BLOCK DIAGRAM

The PS2 implementation has 8 - 128 x 32 FIFOs using the internal block RAM of
the Xilinx. Each TX and RX channel has an associated FIFO. The transmit FIFOs
have the option to fill in parallel - if the same data pattern is to be sent from the 4

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ports then the 4 FIFOs can be filled with the same pattern at the same time.
Fewer PCI cycles are required and less processing by the host.

The transmit data rate can be derived from the 20 MHz on-board oscillator. The
normal transmitter data rate is 5 MHz (divide-by 4), other divisors are also
provided. The first COS port can be used as an alternate clock source as well as
the PCI clock. The max clock rate after division is required to be 20 MHz. The
receiver automatically adjusts to data rates.

The FIFOs always operate at the PCI clock frequency of 33 MHz to simplify testing
and operational functions. Loop-back is provided to allow confidence testing of an
installed board.

Thirty-two differential I/O are provided for the serial signals. The drivers and
receivers conform to the RS-485 specification (exceeds RS-422 specification).
The RS-485 input signals are selectively terminated with 100Ω. The termination
resistors are in two-element packages to allow flexible termination options for
custom formats and protocols. Optional pullup/pulldown resistor packs can also
be installed to provide a logic ‘1’ on undriven lines. The terminations and
transceivers are programmable through the Xilinx device to provide the proper
mix of outputs and inputs and terminations needed for a specific protocol
implementation. The COS directions are programmable via software. The Serial
interfaces are pre-programmed to their intended direction. The terminations are
programmable for all IO.

All configuration registers support read and write operations for maximum
software convenience, and all addresses are long word aligned.

The PMC BiSerial-II conforms to the PMC and CMC draft standards. This
guarantees compatibility with multiple PMC Carrier boards. Because the PMC
may be mounted on different form factors, while maintaining plug and software
compatibility, system prototyping may be done on one PMC Carrier board, with
final system implementation on a different one.

The PMC BiSerial-II uses a 10 mm inter-board spacing for the front panel,
standoffs, and PMC connectors. The 10 mm height is the "standard" height and
will work in most systems with most carriers. If your carrier has non-standard
connectors [height] to mate with the PMC BiSerial-II, please let us know. We may
be able to do a special build with a different height connector to compensate.

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The serial channels are each supported by a 128 by 32-bit FIFO. The FIFOs
support long word reads and writes. A full 32-bit path exists for loop-back testing
of each FIFO. Data is latched and the bus immediately released on a write-cycle.
On a read cycle the data is read after the bus is released from the previous read.
This has the effect of adding one extra read to start capturing data, but means
there is no delay in future reads.

The serial format for transmit and receive is 32 bits per word, LSB first. The
data switches on the falling edge of the reference clock and is valid on the rising
edge. The strobe is asserted on the falling edge before the first data bit should
be taken and held on until the falling edge after the last bit. If more than one
word is sent the words are sent back-to-back without a gap.

The transmit data is sent with the clock and strobe. If the receiver operates as
an asynchronous interface then the first data word can be a sync pattern and the
clock and strobe ignored. The receiver on the PS2 utilizes the clock and the
strobe. The clock is free-running.

The serial receive channels can receive continuous or burst data. The host can
poll the FIFO flags or wait for the programmable FIFO interrupt. The message can
then be read over the PCI bus directly from the FIFO.

The Output channels have a separate 128 x 32-bit FIFO each. The FIFO is written
as long words. Normal operation is to load the TX FIFO for the channel of
interest then set the TX Start bit. The data will start to be transmitted at the
programmed rate along with the strobe. The clock will already be running. The
state-machine will continue to read data from the FIFO and transmit until the FIFO
is empty. When the transmission is completed a programmable interrupt can be
set. The start bit is automatically cleared at the end of a transmission.

Various interrupts are supported by the PMC BiSerial-II PS2. An interrupt can be
configured to occur at the end of a transmitted message. An interrupt can be set
at the end of a reception. Interrupts can occur based on the IO. All interrupts are
individually maskable and a master interrupt enable is also provided to disable all
interrupts simultaneously. The current status is available for the FIFOs making it
possible to operate in a polled mode.

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Theory of Operation

The PMC BiSerial-II PS2 is designed for transferring data from one point to
another with a simple serial protocol.

The PMC BiSerial-II PS2 features a Xilinx FPGA. The FPGA contains all of the
registers and protocol controlling elements of the BiSerial II design. Only the
transceivers, and switches are external to the Xilinx device.

The PMC BiSerial-II is a part of the PMC Module family of modular I/O products. It
meets the PMC and CMC draft Standards. In standard configuration, the PMC
BiSerial-II is a Type 1 mechanical with no components on the back of the board
and one slot wide, with 10 mm inter-board height. Contact Dynamic Engineering
for a copy of this specification. It is assumed that the reader is at least casually
familiar with this document and logic design.

The PCI interface to the host CPU is controlled by a logic block within the Xilinx.
The BiSerial II design requires one wait state for read or write cycles to any
address. The PMC BiSerial-II is capable of supporting 40 MBytes per second into
and out of the FIFO's. The wait states refer to the number of clocks after the PCI
core decode before the “terminate with data” state is reached. Two additional
clock periods account for the 1 clock delay to decode the signals from the PCI
bus and to convert the terminate with data state into the TRDY signal.

The BiSerial II can support many protocols. The PMC BiSerial-II PS2 uses serial
encoded LSB first data, clock and strobe. Data is sent in 32 bit words which are
concatenated for multiple word transfers. The timing is shown in the next
diagram.

State machines within the FPGA control all transfers between the interanal FIFO
and FPGA logic, and the FPGA and the data buffers. The TX state machine reads
from the transmit FIFOs and loads the shift registers before sending the data. The
RX state machine receives data from the data buffers and takes care of moving
data from the shift register into the RX FIFOs.

Data is read from the TX FIFOs and loaded into the shift register. The LSB is then
present at the output of the data buffer. One bit period later the data is

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transitioned to the next value. The LSB+1 is now on the data lines. This process
repeats until the first word is transferred. If more data is available from the FIFO,
then the process repeats for the second word. In the standard timing there are
no inter-word gaps, the data stream is continuous from LSB to MSB for a
compact serial transfer. Please refer to the register bit definitions for more
details.

CLK

STB

DATA

1/2T1/2

FIGURE 3 PS2 TIMING DIAGRAM

LSB LSB +1

T

...

MSB LSB

...

MSB

The data rate is set by a 12-bit field in the Txs control register. The data, and
strobe change on the falling edge and are valid on the rising edge. Approximately
1/2 period of set-up and hold are available at the receiver. The transceivers are
rated for 40 MHz. The top rate programmed for the IO is 20 MHz. The State­machine is designed with the assumption that the PCI clock is faster than the IO
clock rate plus some margin. Faster clock rates are possible with minor changes
to the state-machine / FIFO architecture.

The receive function uses a free running shift register coupled with the receive
state-machine to capture the data. When strobe is detected to have
transitioned from low to high the state-machine starts to count the received
clocks. When the word has been received the data is moved from the shift
register to a parallel holding register. The shift register continues to capture the
next word. The data is moved from the parallel holding register to the RX FIFO
for that channel. When the strobe is detected to be low the receiver clears the
receive enable bit, sets the interrupt if enabled, and goes back to the idle state.

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If the receiver is enabled and a transmission is already in progress, the receiver
will ignore the data until the strobe has been detected to be low then asserted
high again. The design will help to make sure that the hardware stays on 32 bit
data boundaries. If the FIFO is full when the receiver is enabled the state-machine
will wait in the idle state until the FIFO is not full before starting a new reception.

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