Dynamic Engineering PMC-BISERIAL-III RL1 User Manual

DYNAMIC ENGINEERING

150 DuBois, Suite C

Santa Cruz, CA 95060

[phone] Fax [phone]

http://www.dyneng.com

[e-mail]

Est. 1988

User Manual

PMC-BISERIAL-III RL1

Eight-Channel UART Interface

PMC Module

Revision A

Corresponding Hardware: Revision D

10-2005-0204

Corresponding Firmware: Revision A

Embedded Solutions Page 2 of 37

PMC-BiSerial-III RL1

Eight-Channel
PMC Based UART Interface

Dynamic Engineering
150 DuBois, Suite C
Santa Cruz, CA 95060
[phone]
FAX: [phone]

This document contains information of
proprietary interest to Dynamic Engineering. It
has been supplied in confidence and the
recipient, by accepting this material, agrees that
the subject matter will not be copied or
reproduced, in whole or in part, nor its contents
revealed in any manner or to any person except
to meet the purpose for which it was delivered.

Dynamic Engineering has made every effort to
ensure that this manual is accurate and
complete. Still, the company reserves the right
to make improvements or changes in the
product described in this document at any time
and without notice. Furthermore, Dynamic
Engineering assumes no liability arising out of
the application or use of the device described
herein.

The electronic equipment described herein
generates, uses, and can radiate radio
frequency energy. Operation of this equipment
in a residential area is likely to cause radio
interference, in which case the user, at his own
expense, will be required to take whatever
measures may be required to correct the
interference.

Dynamic Engineering’s products are not
authorized for use as critical components in life
support devices or systems without the express
written approval of the president of Dynamic
Engineering.

Connection of incompatible hardware is likely to
cause serious damage.

©2005-2009 by Dynamic Engineering.
Other trademarks and registered trademarks are owned by their respective
manufactures.
Manual Revision A1 Revised October 19,2009

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Table of Contents

PRODUCT DESCRIPTION 6

THEORY OF OPERATION 9

PROGRAMMING 11

ADDRESS MAP 12

Register Definitions 14

RL1_BASE_CONTROL 14
RL1_USER_SWITCH 15
RL1_CHAN_0-7_CONTROL 16
RL1_CHAN_0-7_STATUS 18
RL1_CHAN_0-7_WR_DMA_PNTR 21
RL1_CHAN_0-7_TX_FIFO_COUNT 21
RL1_CHAN_0-7_RD_DMA_PNTR 22
RL1_CHAN_0-7_RX_FIFO_COUNT 22
RL1_CHAN_0-7_FIFO 23
RL1_CHAN_0-7_TX_AMT_LVL 23
RL1_CHAN_0-7_RX_AFL_LVL 23
RL1_CHAN_0-7_TX_CONTROL 24
RL1_CHAN_0-7_RX_CONTROL 25
RL1_CHAN_0-7_TX_START_LATCH 27
RL1_CHAN_0-7_RX_START_LATCH 27
RL1_CHAN_0-7_RX_BYTE_COUNT 28

Loop-back 29

PMC PCI PN1 INTERFACE PIN ASSIGNMENT 30

PMC PCI PN2 INTERFACE PIN ASSIGNMENT 31

FRONT PANEL I/O PIN ASSIGNMENT 32

APPLICATIONS GUIDE 33

Interfacing 33

CONSTRUCTION AND RELIABILITY 34

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THERMAL CONSIDERATIONS 34

WARRANTY AND REPAIR 34

Service Policy 35

Out of Warranty Repairs 35

For Service Contact: 35

SPECIFICATIONS 36

ORDER INFORMATION 37

SCHEMATICS 37

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List of Figures

FIGURE 1 PMC-BISERIAL-III BLOCK DIAGRAM 6
FIGURE 2 PMC-BISERIAL-III RL1 BLOCK DIAGRAM 7
FIGURE 3 PMC-BISERIAL-III RL1 XILINX ADDRESS MAP 13
FIGURE 4 PMC-BISERIAL-III RL1 BASE CONTROL REGISTER 14
FIGURE 5 PMC-BISERIAL-III RL1 USER SWITCH PORT 15
FIGURE 6 PMC-BISERIAL-III RL1 CHANNEL CONTROL REGISTER 16
FIGURE 7 PMC-BISERIAL-III RL1 CHANNEL STATUS PORT 18
FIGURE 8 PMC-BISERIAL-III RL1 WRITE DMA POINTER REGISTER 21
FIGURE 9 PMC-BISERIAL-III RL1 TX FIFO DATA COUNT PORT 21
FIGURE 10 PMC-BISERIAL-III RL1 READ DMA POINTER REGISTER 22
FIGURE 11 PMC-BISERIAL-III RL1 RX FIFO DATA COUNT PORT 22
FIGURE 12 PMC-BISERIAL-III RL1 RX/TX FIFO PORT 23
FIGURE 13 PMC-BISERIAL-III RL1 TX ALMOST EMPTY LEVEL REGISTER 23
FIGURE 14 PMC-BISERIAL-III RL1 RX ALMOST FULL LEVEL REGISTER 23
FIGURE 15 PMC-BISERIAL-III RL1 TX CONTROL REGISTER 24
FIGURE 16 PMC-BISERIAL-III RL1 RX CONTROL REGISTER 25
FIGURE 17 PMC-BISERIAL-III RL1 TX START LATCH 27
FIGURE 18 PMC-BISERIAL-III RL1 RX START LATCH 27
FIGURE 19 PMC-BISERIAL-III RL1 RX BYTE COUNT PORT 28
FIGURE 20 PMC-BISERIAL-III RL1 PN1 INTERFACE 30
FIGURE 21 PMC-BISERIAL-III RL1 PN2 INTERFACE 31
FIGURE 22 PMC-BISERIAL-III RL1 FRONT PANEL INTERFACE 32

Product Description

The PMC-BiSerial-III RL1 is a part of the PMC Module family of modular I/O products by
Dynamic Engineering. It meets the PMC and CMC draft Standards. In standard
configuration, the PMC-BiSerial-III RL1 is a Type 1 mechanical with only low profile
passive components on the back of the board, one slot wide, with 10 mm inter-board
height. Contact Dynamic Engineering for a copy of this specification. It is assumed that
the reader is at least casually familiar with this document and basic logic design.

FIGURE 1 PMC-BISERIAL-III BLOCK DIAGRAM

The PMC-BiSerial-III is capable of providing multiple serial protocols using either LVDS
or RS-485 I/O standards. The PMC-BiSerial-III standard configuration shown in Figure
1 has two optional data FIFOs that can be as large as 128k x 32-bits to accommodate
designs requiring a large amount of buffering. In most designs these FIFOs are not
installed and internal FIFOs implemented with the block RAM in the Xilinx FPGA are
used instead.

FIGURE 2 PMC-BISERIAL-III RL1 BLOCK DIAGRAM

The PMC-BiSerial-III RL1 configuration is shown in figure 2. The protocol implemented
provides eight I/O channels each consisting of RS-485 transmit and receive data. The
on-board PLL is used to generate two clocks that can be independently selected by
each channel in the design. The PLL is programmable and uses a 40 MHz reference
oscillator to generate a wide range of frequencies. The UART interface uses a 16x
clock to detect received data bits. The interface can operate at up to 10 Mbits/second
using a 160 MHz clock.

Data for all channels is sent and received LSB first using a low start-bit and one or two
high stop-bits to separate data bytes. An optional parity bit following the eight data bits
can be configured to implement odd, even, mark (always high), or space (always low)
parity. The marking (idle) state of the interface is high.

Each channel can be configured for either half or full-duplex operation. In half-duplex
mode, the receiver data is read from the transmit I/O while the transmitter is in a high
impedance state. Pull-up/pull-down resistor packs have been installed on the eight
transmit I/O lines to provide a logic ‘1’ when the I/O is un-driven. This prevents glitching

when switching directions in half-duplex mode.
The RL1 implementation has two 1K by 32-bit FIFOs per channel, created using the
Xilinx internal block RAM, one for the transmitter and one for the receiver. The two
FIFOs have separate reset bits and a data bypass feature that automatically moves
data from the transmit to the receive FIFO to allow FIFO data-path testing without using
the external I/O.

Various interrupts are supported by the PMC-BiSerial-III RL1. An interrupt can be
configured to occur at the end of a received or transmitted message, when the transmit
FIFO becomes almost empty or when the receive FIFO becomes almost full or when
the receive FIFO overflows (attempt to write to a full FIFO). Receiver parity or framing
errors are detected and latched, but can not cause an interrupt to occur. All interrupts
are individually maskable, and a master channel interrupt enable is also provided to
disable all interrupts for a channel simultaneously. The current status is available even
when an interrupt is disabled making it possible to operate in a polled mode. All
configuration registers support read and write operations for maximum software
convenience. All addresses are long word (32-bit) aligned.

Potentially thirty-four differential I/O are available at the front bezel for the serial signals.
The drivers and receivers conform to the RS-485 specification. The RS-485 input
signals are selectively terminated with 100Ω. The termination resistors are in two­element packages to allow flexible termination options for custom formats and
protocols. Optional pull-up/pull-down resistor packs can also be installed to provide a
logic ‘1’ on undriven lines. In this design 4.7 kΩ pull-up/pull-down resistors have been
installed on the eight transmit lines to prevent erroneous data when switching directions
in half-duplex mode. This design uses only sixteen of the I/O lines, one in and one out
for each of the eight channels.

Other custom interfaces are available on request. We will redesign the state machines
and create a custom interface protocol that meets your requirements. That protocol will
then be offered as a “standard” special order product. Please see our web page for
current protocols offered. Please contact Dynamic Engineering with your custom
application.

Since the PMC-BiSerial-III RL1 conforms to the PMC and CMC draft standards, it is
guaranteed to be compatibile with multiple PMC Carrier boards. Because the PMC may
be mounted on different form factors, while maintaining plug and software compatibility,
system prototyping may be done on one PMC Carrier board, while final system
implementation uses a different one.

The PMC-BiSerial-III RL1 uses a 10 mm inter-board spacing for the front panel,
standoffs, and PMC connectors. The 10 mm height is the "standard" height and will
work in most systems with most carriers. If your carrier has non-standard connectors
(height) to mate with the PMC-BiSerial-III RL1, please let us know. We may be able to
do a special build with a different height connector to compensate.

Theory of Operation

The PMC-BiSerial-III RL1 features a Xilinx FPGA. The FPGA contains all of the
registers, FIFOs and protocol controlling elements of the PMC-BiSerial-III RL1 design.
Only the transceivers, switches and PLL circuit are external to the Xilinx device.

A logic block within the Xilinx controls the PCI interface to the host CPU. The PMC­BiSerial-III RL1 design requires one wait state for read or writes cycles to any address.
The wait states refer to the number of clocks after the PCI core decodes the address
and control signals and before the “terminate with data” state is reached. Two
additional clock periods account for the delay to decode the signals from the PCI bus
and to convert the terminate-with-data state into the TRDY signal.

Scatter-gather DMA is provided for in this design with the memory page information
stored in host RAM as a series of chaining descriptors. Once the physical address of
the first chaining descriptor is written to the appropriate DMA pointer register, the
interface will read a 12-byte block from this location. The first four bytes comprise a
long-word indicating the physical address of the first block of the I/O buffer passed to
the read or write call. The next four bytes represent a long-word indicating the length of
that block. The final four bytes are a long-word indicating the physical address of the
next chaining descriptor along with two flag bits, in bit position 0 and 1. Bit zero is set to
a ‘1’ if this descriptor is the last in the chain. Bit one is set to a ‘1’ if the I/O transfer is
from the PMC-BiSerial-III RL1 board to host memory, and a ‘0’ if the transfer is from
memory to the board. These bits are then replaced with zeros to determine the address
of the next descriptor, if there is one.

To transmit data requires a number of steps to be performed. First, the PLL must be
programmed to supply the transmit clock. The data to be sent written to the TX FIFO
and the transmitter enabled. These steps do not need to be performed in this order, but
they must all be done to accomplish the transfer. If the requested transmit byte count is
zero, all the data written to the transmit FIFO will be sent, otherwise only the specified
number of bytes will be sent. The least significant byte of the FIFO word is sent first
then the next significant byte follows until the entire 32-bit word is sent. If a byte count
is requested that is not divisible by four, the remaining bytes of the last FIFO word are
discarded and a subsequent transmission will begin with the next FIFO word.

In order to receive data it is only necessary to configure the PLL, enable the receiver
and wait for data to be received. A 16-bit counter is incremented for each data byte
received. Once the reception has started, a 32-bit data word will be stored in the
receive FIFO for each four bytes received. The first byte is stored in the least significant
byte of the FIFO word and each subsequent byte is stored in the next most significant
byte. When the input data line is idle for at least eight bit-periods the reception will
terminate. This will cause the received byte count to be written to the byte count
register, clear the 16-bit byte counter and set the Receive Done status bit. If the last
FIFO word has not been completed, the last partial word will be written to the receive

FIFO with the unfilled bytes set to zeros. Also if the Receive Start Clear Enable is set,
the Receiver Enable bit will be cleared. Otherwise the receiver will remain enabled and
will wait for the next start-bit to continue receiving data.

TX FIFO almost empty and RX FIFO almost full levels are programmable by writing
values into the respective FIFO level registers. Besides generating FIFO level status
and potentially causing an interrupt, these values can also be used to give DMA
arbitration priority to a FIFO approaching its limit if enabled to do so. This process helps
to prevent TX FIFO underrun and RX FIFO overrun when data is being transferred on
multiple channels. If a channel FIFO has reached its almost empty/full level, that FIFO
will get priority in the DMA arbiter if priority arbitration is enabled for that FIFO.

Programming

Programming the PMC-BiSerial-III RL1 requires only the ability to read and write data
from the host. The base address is determined during system configuration of the PCI
bus. The base address refers to the first user address for the slot in which the PMC is
installed.

Depending on the software environment it may be necessary to set-up the system
software with the PMC-BiSerial-III RL1 "registration" data. For example in WindowsNT
there is a system registry, which is used to identify the resident hardware.

Before I/O data can be sent or received, the PLL must be programmed to the desired
clock configuration. The PLL is connected to the Xilinx by an I2C serial bus. The PLL
internal registers are loaded with 40 bytes of data that are derived from a .jed file
generated by the CyberClock utility from Cypress semiconductor

http://www.dyneng.com/CyberClocks.zip. Routines to program the PLL are included in

the driver and UserApp code provided in the engineering kit for the board.

The interrupt service routine should be loaded and the interrupt mask set. The interrupt
service routine can be configured to respond to the TX/RX interrupts. After an interrupt
is received, new TX data can be written or RX data retrieved. An efficient loop can then
be implemented to process the data. New messages can be sent or received even as
the current one is in progress.

If more than one interrupt is enabled, then the software needs to read the status to see
which source caused the interrupt. The status bits are latched, and are explicitly
cleared by writing a one to the corresponding bit. It is a good idea to read the status
register and write that value back to clear all the latched interrupt status bits before
starting a transfer. This will insure that the interrupt status values read by the interrupt
service routine came from the current transfer.

If DMA is to be used it will be necessary to acquire blocks of non-paged memory that
are accessible from the PCI bus in which to store the DMA chaining descriptor list
entries.

Refer to the Theory of Operation section above and the register definition section below
for more information regarding the exact sequencing and interrupt definitions.

The PMC-BiSerial-III RL1 VendorId = 0x10EE. The CardId = 0x0032. The device class
code is 0x0680 (PCI bridge – other)

Address Map

Register Name Offset Description

RL1_BASE_CONTROL 0x0000 Base Control Register
RL1_PLL_WRITE 0x0000 Base Control - Bits 16-19 Used for PLL Control
RL1_PLL_READ 0x0004 Switch Port Bit 19 Used for pll_sdat Input
RL1_USER_SWITCH 0x0004 User Switch Read Port and Xilinx Design Revision

RL1_CHAN_0_CONTROL 0x0010 Channel 0 Control Register
RL1_CHAN_0_STATUS 0x0014 Channel 0 Status Register
RL1_CHAN_0_WR_DMA_PNTR 0x0018 Channel 0 Write DMA Physical PCI dpr Address
RL1_CHAN_0_TX_FIFO_COUNT 0x0018 Channel 0 TX FIFO Count
RL1_CHAN_0_RD_DMA_PNTR 0x001C Channel 0 Read DMA Physical PCI dpr Address
RL1_CHAN_0_RX_FIFO_COUNT 0x001C Channel 0 RX FIFO Count
RL1_CHAN_0_FIFO 0x0020 Channel 0 FIFO Single-Word Access
RL1_CHAN_0_TX_AMT_LVL 0x0024 Channel 0 TX almost empty level
RL1_CHAN_0_RX_AFL_LVL 0x0028 Channel 0 RX Almost Full Level
RL1_CHAN_0_TX_CONTROL 0x002C Channel 0 TX Control Register
RL1_CHAN_0_RX_CONTROL 0x0030 Channel 0 RX Control Register
RL1_CHAN_0_TX_START 0x0034 Channel 0 TX Start Latch
RL1_CHAN_0_RX_START 0x0038 Channel 0 RX Start Latch
RL1_CHAN_0_RX_BYTE_COUNT 0x0038 Channel 0 RX Byte Count

RL1_CHAN_1_CONTROL 0x003C Channel 1 Control Register
RL1_CHAN_1_STATUS 0x0040 Channel 1 Status Register
RL1_CHAN_1_WR_DMA_PNTR 0x0044 Channel 1 Write DMA Physical PCI dpr Address
RL1_CHAN_1_TX_FIFO_COUNT 0x0044 Channel 1 TX FIFO Count
RL1_CHAN_1_RD_DMA_PNTR 0x0048 Channel 1 Read DMA Physical PCI dpr Address
RL1_CHAN_1_RX_FIFO_COUNT 0x0048 Channel 1 RX FIFO Count
RL1_CHAN_1_FIFO 0x004C Channel 1 FIFO Single-Word Access
RL1_CHAN_1_TX_AMT_LVL 0x0050 Channel 1 TX almost empty level
RL1_CHAN_1_RX_AFL_LVL 0x0054 Channel 1 RX Almost Full Level
RL1_CHAN_1_TX_CONTROL 0x0058 Channel 1 TX Control Register
RL1_CHAN_1_RX_CONTROL 0x005C Channel 1 RX Control Register
RL1_CHAN_1_TX_START 0x0060 Channel 1 TX Start Latch
RL1_CHAN_1_RX_START 0x0064 Channel 1 RX Start Latch
RL1_CHAN_1_RX_BYTE_COUNT 0x0064 Channel 1 RX Byte Count

RL1_CHAN_2_CONTROL 0x0068 Channel 2 Control Register
RL1_CHAN_2_STATUS 0x006C Channel 2 Status Register
RL1_CHAN_2_WR_DMA_PNTR 0x0070 Channel 2 Write DMA Physical PCI dpr Address
RL1_CHAN_2_TX_FIFO_COUNT 0x0070 Channel 2 TX FIFO Count
RL1_CHAN_2_RD_DMA_PNTR 0x0074 Channel 2 Read DMA Physical PCI dpr Address
RL1_CHAN_2_RX_FIFO_COUNT 0x0074 Channel 2 RX FIFO Count
RL1_CHAN_2_FIFO 0x0078 Channel 2 FIFO Single-Word Access
RL1_CHAN_2_TX_AMT_LVL 0x007C Channel 2 TX almost empty level
RL1_CHAN_2_RX_AFL_LVL 0x0080 Channel 2 RX Almost Full Level
RL1_CHAN_2_TX_CONTROL 0x0084 Channel 2 TX Control Register
RL1_CHAN_2_RX_CONTROL 0x0088 Channel 2 RX Control Register
RL1_CHAN_2_TX_START 0x008C Channel 2 TX Start Latch
RL1_CHAN_2_RX_START 0x0090 Channel 2 RX Start Latch
RL1_CHAN_2_RX_BYTE_COUNT 0x0090 Channel 2 RX Byte Count

RL1_CHAN_3_CONTROL 0x0094 Channel 3 Control Register
RL1_CHAN_3_STATUS 0x0098 Channel 3 Status Register
RL1_CHAN_3_WR_DMA_PNTR 0x009C Channel 3 Write DMA Physical PCI dpr Address
RL1_CHAN_3_TX_FIFO_COUNT 0x009C Channel 3 TX FIFO Count
RL1_CHAN_3_RD_DMA_PNTR 0x00A0 Channel 3 Read DMA Physical PCI dpr Address
RL1_CHAN_3_RX_FIFO_COUNT 0x00A0 Channel 3 RX FIFO Count
RL1_CHAN_3_FIFO 0x00A4 Channel 3 FIFO Single-Word Access
RL1_CHAN_3_TX_AMT_LVL 0x00A8 Channel 3 TX almost empty level
RL1_CHAN_3_RX_AFL_LVL 0x00AC Channel 3 RX Almost Full Level
RL1_CHAN_3_TX_CONTROL 0x00B0 Channel 3 TX Control Register
RL1_CHAN_3_RX_CONTROL 0x00B4 Channel 3 RX Control Register
RL1_CHAN_3_TX_START 0x00B8 Channel 3 TX Start Latch
RL1_CHAN_3_RX_START 0x00BC Channel 3 RX Start Latch
RL1_CHAN_3_RX_BYTE_COUNT 0x00BC Channel 3 RX Byte Count

RL1_CHAN_4_CONTROL 0x00C0 Channel 4 Control Register