Dynamic Engineering PCIe8LSwVPX3U User Manual
DYNAMIC ENGINEERING
150 Dubois St. Suite C, Santa Cruz, CA 95060
831-457-8891 Fax 831-457-4793
http://www.dyneng.com
sales@dyneng.com
Est. 1988
User Manual
PCIe8LSwVPX3U
PCIe 8 Lane VPX 3U Compatible Carrier
©2014-2017 by Dynamic Engineering.
Corresponding Hardware: Revision B
Fab number 10-2014-1102
Revision B3 10/19/17
2
PCIe8LSwVPX3U
PCIe and VPX Compatible Carrier
Dynamic Engineering
150 Dubois St. Suite C
Santa Cruz, CA 95060
831457-8891
831457-4793 FAX
This document contains information of
proprietary interest to Dynamic Engineering. It
has been supplied in confidence and the
recipient, by accepting this material, agrees that
the subject matter will not be copied or
reproduced, in whole or in part, nor its contents
revealed in any manner or to any person except
to meet the purpose for which it was delivered.
Dynamic Engineering has made every effort to
ensure that this manual is accurate and
complete. Still, the company reserves the right to
make improvements or changes in the product
described in this document at any time and
without notice. Furthermore, Dynamic
Engineering assumes no liability arising out of
the application or use of the device described
herein.
The electronic equipment described herein
generates, uses, and can radiate radio
frequency energy. Operation of this equipment
in a residential area is likely to cause radio
interference, in which case the user, at his own
expense, will be required to take whatever
measures may be required to correct the
interference.
Dynamic Engineering’s products are not
authorized for use as critical components in life
support devices or systems without the express
written approval of the president of Dynamic
Engineering.
Connection of incompatible hardware is likely to
cause serious damage.
Other trademarks and registered trademarks are owned by their
respective manufactures.
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PRODUCT DESCRIPTION 5
Clocking 7
Headers and TestPoints 8
DipSwitch Settings 9
Switch Status LED’s 11
VPX MODULE BACKPLANE IO INTERFACE PIN ASSIGNMENT 12
SCSI P2 – VPX J2 USER VPX P2 12
VPX Module J1 PCIe lane assignments 13
VPX Module J0 Power assignments 14
APPLICATIONS GUIDE 15
Interfacing 15
Construction and Reliability 16
Thermal Considerations 16
VITA Multipoint SSC Clocking implemenation 17
Loopback Testing 18
WARRANTY AND REPAIR 19
Service Policy 19
Out of Warranty Repairs 19
For Service Contact: 19
SPECIFICATIONS 20
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ORDER INFORMATION 21
FIGURE 1 PCIE8LSWVPX3U CLOCKING 7
FIGURE 2 PCIE8LSWVPX3U P2/J2/USER P2 IO 12
FIGURE 3 PCIE8LSWVPX3U PCIE/J1 13
FIGURE 4 PCIE8LSWVPX3U POWER/J0 14
FIGURE 5 VITA SYSTEM CLOCKING – MAXIMUM CONFIGURATION 17
FIGURE 6 PCIE8LSWVPX3U LOOPBACK TEST CONFIGURATION 18
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Product Description
PCIe8LSwVPX3U is part of the Dynamic Engineering PCI and VPX Compatible family
of modular I/O components. PCIe8LSwVPX3U adapts a 3U VPX device to one PCIe
position.
PCIe8LSwVPX3U features a 16 lane switch buffering the connection between the Gold
fingers on the PCIe side and the VPX connector. The switch provides isolation to allow
the VPX side to operate at a different Gen level than the upstream port, and to provide
clock domain separation. In many cases it is desirable to have the upstream port run
Spread Spectrum enabled, and the VPX side operate with a fixed frequency clock. The
switch is Gen3 compliant and can operate with Gen 1, 2 or 3 on either port.
New with Revision B, PCIe8LSwVPX3U has support for both SSC and NSSC clocking
on the VPX port. REF_CLK is supported with a 25 MHz SSC. The switch can be
programmed via dipswitch to use SSC or NSSC on the downstream port. The installed
VPX card will need to match the settings for proper operation.
Extended testing has been performed in both modes using the VPX8LXMC3U adapter
and an installed XMC-Parallel-TTL. DMA operations were run overnight multiple times
in both modes without failure or TLP corrections required at the switch.
VPX devices have 3 connectors for Power, Bus IF, and IO respectively.
The power connector supplies 5V, 3.3V and 12V. PCIe has +12V available. Local
power supplies generate the 3.3V and 5V for the VPX module. Approximately 10A are
available on each rail. Voltage monitor circuits check under and overvoltage conditions
of each rail including the ones for the switch, and illuminate an LED when the voltage is
within tolerance.
The Bus IF connector provides up to 8 lanes from the downstream port on the switch.
Differential routing with length and impedance control are maintained for all relevant
PCIe signals on both sides of the switch.
The IO is routed from the VPX rear IO connector through to a SCSI connector mounted
at the bezel of PCIe8LSwVPX3U. Differential routing with impedance control and
matched length traces are employed.
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Special features:
• 8 lane PCIe interface
• DIP switch to configure and select:
- Switch/board PCIe NSSC or VITA Spec SSC
- PLX PEX8718 internal register access modes.
• Voltage monitors, each with LED’s on plus 12V, 5V, 3.3V, .9V and 1.8V
• 10A regulator for VPX 3.3V and 5V supplies. 12V from PCIe interface or optional –AP
connector.
• Front panel connector access through PCIe bracket for Rear IO
• User IO P2/J2 available through SCSI connector. Routed as differential pairs,
matched length, controlled impedance.
• JTAG programming support – optional header routed to VPX JTAG pins
• DIP switch to select global addressing on VPX
• PCIe Switch Status LED’s for FATAL, Port Good0, and Port Good1
• Optional EEPROM to configure PCIe Switch registers before boot.
• With Rev B cards, coax [SMA] are supplied on the SSC and NSSC ports to support
T&I
PCIe8LSwVPX3U is ready to use with the default settings. Just install the VPX onto the
PCIe8LSwVPX3U and then into the system. The board is designed to allow the use of
the PCIe8LSwVPX3U + VPX with other 1/2 length cards in the system.
For example we have a test set-up for a VPX card [VPX-RCB] with differential IO. We
use PMC-BiSerial-III to act as a system simulator. PCIeBPMC + PMC BiSerial III in the
front slot to create, and read back the IO. PCIe8LSwVPX3U + VPX in the second slot
for test. The BiSerial also has a SCSI connector allowing easy connection between the
bezels for a complete test path.
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Clocking
PCIe8LSwVPX3U Clocking
EIA-899 M -LVDS
25MHz REFCLK +/-
with Mo dulation
+/- 100ppm max
50% duty cycle +/- 5%
PCI Express
Host
PCI
Express
Switch
VPX Add-In Card or
Carrier such as
Dynamic Engineering’s
VPX8LXMC3U
x8 PCIe link
REFCLKp/n
VPX/PCIe
Compliant
Downstream
Ports Clock
with Spread
Upstream
Port Clock with
Spread or
No Spread
X8 PCIe link
SSC Off
25MHz
Crystal
PCIe compliant
100MHz Clock
No Spread
Straps
Clock
Generator
SSC Off
Straps
25MHz in
100MHz out
with SSC
Generator
1.8V
M-LVDS
Transmitter
25MHz
100MHz
25MHz in
25MHz SSC out
Clock Generator
M-LVDS
Receiver
Note: VPX Spec allows up to 32
circuits to be connected to the
common transmission media
Backplane differential REF_CLK+/- lines are differentially
terminated at each end with a resistor of 61.9 Ohms +/- 1%
PCIe
Compliant
Downstream
Ports Clock
No Spread
Downstream
Port
Clock Select
PCIe compliant
100MHz Clock
with Spread
VITA
25MHz in
100MHz out
with SSC
Generator
PCIe
Compliant
100MHz
NSSC
Generator
AND
OR
PCIe8LSwVPX3U VPX (PCIe downstream) port supports both PCI Express
Independent Non-Spread Spectrum Clocking (NSSC) and VITA Spread Spectrum
Clocking (SSC). The upstream/host port supports a PCIe REFCLK that is either a SSC
or a NSSC, or can be configured to use an on board NSSC if desired. Figure 1 shows
the clocking architecture of the PCIe8LSwVPX3U. The clocking mode is selected using
DIP Switches described in the DIP switch settings section.
FIGURE 1 PCIE8LSWVPX3U CLOCKING
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