Dynamic Engineering PCI5IP User Manual

DYNAMIC ENGINEERING

150 DuBois St. Suite C, Calif. 95060
831-457-8891 Fax [phone]

http://www.dyneng.com

[e-mail]

Est. 1988

PCI5IP

User Manual

Integrated PCI ó IP Module Carrier

Key Features

Fast Access with integrated PCI ó IP Bridge

5 IP Positions with IO

8/32 MHz IP operation

8/16/32 bit accesses supported

16/32 bit IP module support

Data Alignment – Byte and Word Swapping

Watch Dog Timer

LED’s - Power, IP Access, User

Multi-board support

Manual Revision G1

Corresponding Hardware: Revision G

Fab Number 10-2002-0307

FLASH revision G1

Page 2 of 32 Embedded Solutions

PCI5IP

Dynamic Engineering
150 DuBois St Suite C
Santa Cruz, CA 95060

This document contains information of proprietary interest to Dynamic
Engineering. It has been supplied in confidence and the recipient, by accepting
this material, agrees that the subject matter will not be copied or reproduced, in
whole or in part, nor its contents revealed in any manner or to any person except
to meet the purpose for which it was delivered.

Dynamic Engineering has made every effort to ensure that this manual is
accurate and complete. Still, the company reserves the right to make
improvements or changes in the product described in this document at any time
and without notice. Furthermore, Dynamic Engineering assumes no liability
arising out of the application or use of the device described herein.

The electronic equipment described herein generates, uses, and can radiate
radio frequency energy. Operation of this equipment in a residential area is likely
to cause radio interference, in which case the user, at his own expense, will be
required to take whatever measures may be required to correct the interference.

Dynamic Engineering’s products are not authorized for use as critical
components in life support devices or systems without the express written
approval of the president of Dynamic Engineering.

This product has been designed to operate with IP Modules and compatible user­provided equipment. Connection of incompatible hardware is likely to cause
serious damage.

©2002-2016 by Dynamic Engineering.

Other trademarks and registered trademarks are
owned by their respective manufactures.
Revised July 21, 2016

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PRODUCT DESCRIPTION 5!

Theory of Operation 11!

INSTALLATION 12!

ADDRESS MAP 13!

PROGRAMMING 14!

pci5ip_intreg_base 17!
pci5ip_intreg_(a-e) 20!
pci5ip_intreg_int 23!
pci5ip_intreg_dswitch 25!

APPLICATIONS GUIDE 26!

Interfacing 26!

Engineering Kit 26!

IP Module Logic Interface Pin Assignment 27!

Construction and Reliability 28!

MTBF 28!

Thermal Considerations 28!

WARRANTY AND REPAIR 29!

Service Policy 29!

Out of Warranty Repairs 29!

For Service Contact: 29!

SPECIFICATIONS 30!

ORDER INFORMATION 31!

Table of Contents

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FIGURE 1! PCI5IP POWER FILTERING 8!
FIGURE 2! PCI5IP RESET CIRCUIT 9!
FIGURE 3! PCI5IP STROBE CONNECTION TABLE 10!
FIGURE 4! PCI5IP ADDRESS MAP 13!
FIGURE 5! PCI5IP CONTROL PORT 17!
FIGURE 6! PCI5IP SLOT CONTROL PORT 20!
FIGURE 7! PCI5IP 16 BIT BYTE SWAPPING 21!
FIGURE 8! PCI5IP 32 BIT BYTE SWAPPING 21!
FIGURE 9! PCI5IP INTERRUPT STATUS PORT 23!
FIGURE 10! PCI5IP USER SWITCH PORT 25!
FIGURE 11! PCI5IP LOGIC INTERFACE 27!
FIGURE 12! PCI5IP LOCATION REFERENCE 32!
FIGURE 13! PCI5IP CONNECTOR REFERENCE 32!

List of Figures

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Product Description

IndustryPack® Modules are an important part of solutions for Embedded situations.
Rugged, Small, light .. just right for many applications. IndustryPack® Modules require
a “carrier” to adapt them to the system. Dynamic Engineering has carrier solutions for a
variety of formats. PCI5IP is designed to support PC computer based solutions. Other
supported formats include PCIe, cPCI, PC104p, VPX.

PCI5IP is part of the Dynamic Engineering IP Compatible family of modular I/O
components. PCI5IP provides five IndustryPack® Compatible sites in one PCI slot. Two
of the slot pairs can be used for double wide IP Modules with either 16 or 32 bit IP
Module bus.

PCI5IP is supported with Windows® compliant [WDM32] drivers for XP and 2000
[WFM] for Win7 and Linux [Ubuntu]. VxWorks is in development. The drivers come
with a generic IP driver to allow use with “unknown” IP’s – IP’s that do not have a driver
designed yet. For example, third party IP’s

ID, IO, INT, and MEM access types are supported for read and write cycles. The full 8
Mbytes of address space is allocated to each of the MEM spaces.

The PCI bus is 32 bits wide and most industry packs are 16 bit devices. Byte, word,
and long word accesses are supported. Bytes can be to any address. Word accesses
need to be word aligned. Long word accesses need to be long word aligned. Each of
the access types has a one-to-one correspondence to the hardware. There are no
"extra" accesses with the PCI5IP design.

The Data bus is designed as a 32-bit bus with slots A,C,E on the D15-0 segment. B
and D are on the D31-16 half of the bus. The current hardware compensates and
allows for standard accesses to all slots – software transparent. The BC and DE slots
can be accessed as a 32 bit wide data path. The BC and DE slots are mechanically
aligned for double wide card installation as well as pairs of single wide cards.

A long word access to a 16 bit port will automatically be converted into two back-to-back
IP accesses with the address incrementing between cycles unless the increment
disable function is selected (see Slot control register description). In the increment
disable case the hi or low address can be specified for the double access.

For a read, one 32 bit data word will be returned. For example a long word read to the
ID space would yield $xx50xx49 for many boards as the "0" location has $49 and the
next address has $50. The long word mode happens automatically when all 4 of the
byte lane enables are detected asserted. The overall throughput is greatly enhanced

Page 6 of 32 Embedded Solutions

with this mode of operation. Please note the non-data bytes should be masked, as
many IPs do not drive the “off byte”.

For a long word access to a long word port the 32 bit IP data bus is utilized. Slots B/C
and D/E form 32 bit slots when 32 bit IPs are installed. The access type is automatic
based on the address space used to access the slots. You can use 16 and 32 bit
accesses intermixed without changing your control registers if the IP supports both.
Slot C and E control registers define the access when in 32 bit mode. It may be
necessary to match Slot B clock to slot C and Slot D clock to slot E if your IP uses both.

The address is shifted from long [32] to short [16] by hardware and the byte strobes
used to access the individual bytes or words. If your card has mixed addressing
requirements you may need dual defines to account for the 32 bit and 16 bit addressing.

The PCI bus is defined as little endian and many IPs have their register sets defined to
operate efficiently with a little endian interface. The default settings on the PCI5IP are
“straight through” byte for byte and D15-0 written to address 0x00 before D31-D16
written to address 0x02 when long words are written to 16 bit ports. Please note that
any long word address can be used. The lower data is written to the lower address first,
then the upper data to the upper address. Each slot has a BS and WS control bit to
allow Byte and Word Swapping to be performed to accommodate alternate IP and OS
requirements.

Byte Swapping

16 bit ports
D15-8 ó D7-0
D31-24 óD23-16
32 bit ports
D31-24 => D7-0
D23-16 => D15-8
D15-8 => D23-16
D7-0 => D31-24

Word Swapping will swap D31-16 with D15-0

If byte swapping is enabled and 0x1234 is written to an IP slot, then the IP will see
0x3412. If 0x12345678 is written to a 32-bit port then the IP will see 0x78563412. The
“is written” is defined by the data on the PCI bus. Your software/OS may do its own
conversion before the data gets to the PCI bus.

The byte and word swap controls are separated to allow the conversion to be used for
big-little endian and for register mapping purposes. Each slot has separate controls for

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access to that slot.

PCI5IP has a watch-dog timer function which completes the IP access if the IP does not
respond within 7.6 uS. The watch-dog timer has a master status bit and an optional
interrupt output. In addition to the master status each slot control register reports status
for the bus error. Multi-threaded programs can tell if their hardware access caused the
Bus Error even if other threads have accessed other hardware since the bus error was
caused.

The design of PCI5IP tags all accesses from the PCI bus. IP Modules can take longer
than the PCI response specification leading to the use of retry cycles on the PCI bus.
In a single CPU system the retry accesses are done serially. The current IP access will
be the correct one to respond to the retry access. In a multi-CPU system it is possible
to get out of sequence accesses, and potentially have the IP response sent to the
wrong retry access. By storing the PCI parameters for the IP access and only
responding to the correct retry cycle; multiprocessor cross contamination is avoided.
This feature is incorporated beginning with the revision F.

Each slot is programmable for 8 or 32 MHz. operation. The control register has
separate bits for slot A, B, C, D and E. The clocks are locked together and can be
switched at any time. Hardware insures that the clocks switch basis on a clock period
boundary to provide seamless operation.

PCI5IP supports interrupts from each slot with separate mask bits. Two interrupts from
each of the five slots. An interrupt “force” bit is supplied to aide in software
development. The bus error [watch dog timer] can also be an interrupt condition. The
masked interrupts are tied together and connected to INTA on the PCI bus.

PCI5IP has LED's for power, access, and user functions. The supplied voltages are
monitored and an LED illuminated when in tolerance. +12, -12, +5, 3.3. An additional 8
LED's are supplied which are controlled via the control register for user defined
purposes. Five LED’s are controlled by a timer circuit which is activated by the
acknowledge from each of the IP slots.

The power to each of the IP slots is individually filtered and fused for +5 and ±12. The
fuses are rated at 2A on the 5V rail and 1.1A on the ±12V rails. PCI5IP is designed to
route maximum power to each slot in parallel. The power supply capabilities for your
chassis may provide additional constraints. Each slot filter has a separate RF filter, bulk
capacitor, “self healing” fuse, and bipass capacitors. A bipass capacitor is located at
each of the power pins on the PCI5IP with the bulk capacitor near the filter pin for
optimum noise rejection, voltage hold-up and local filtering. For power hungry IP’s the
fuses can be replaced with a strap to allow for more than the specified current.

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FIGURE 1 PCI5IP POWER FILTERING

With the filter pin on each slot and bulk capacitor each IP is effectively isolated from the
other IP’s mounted to the PCI5IP. Additional work was done in layout to minimize the
amount of cross-slot electronic noise. Each of the IP slots is also isolated from the PCI
interface by the power conditioning. The FPGA uses 3.3 and 2.5V power which is
derived from the 5V supply and bussed on mini-planes to the FPGA. The FPGA is
effectively isolated from the IP slots by the regulators and additional filtering.

PCI5IP is well behaved with low noise power provided to each of the slots. PCI5IP is
designed for analog and digital IP applications including data acquisition,
instrumentation, measurement, command and control, telemetry and other industrial
applications.

An 8 bit "dip switch" is provided on the PCI5IP. The switch configuration is readable via
a register. The switch is for user defined purposes. We envision the switch being used
for software configuration control, PCI board identification or test purposes.

P C I P o w e r

IP Po w e r

F1

L1

Page 9 of 32 Embedded Solutions

The reset switch provided can be used to reset the IP devices without affecting the PCI
bus. Power, PCI reset, and a control register bit also cause the IP Reset to be
activated. The reset is controlled to be synchronous to the 8 MHz. clock. Alternatively,
the IP-Debug-Bus card can be used for individual slot resets.

FIGURE 2 PCI5IP RESET CIRCUIT

The IO are brought to 50 pin headers. The headers are installed without ejectors to be
PCI compliant [height]. The ejectors can be installed by special request. Routing is
matched length, impedance controlled, and differential on a per IP basis. The
differential pairs are 1-2,3-4,..23-24, 25-50, 26-27… 48-49. With this pattern the
differential pairs can be properly routed for both the IP and Header connectors with
adjacent pin pairs used except for the single 25-50 pair. Frequently 25 and 50 are
grounds. Routing is still 1:1 as well making signal tracing through the carrier easier to
deal with. Dynamic Engineering IP modules take advantage of the differential definition
just outlined.

PCI5IP conforms to the VITA standard for IndustryPack Carriers. This guarantees
compatibility with multiple IndustryPack compatible modules.

PCI5IP conforms to the PCI 2.3 specification and supports both 3.3V and 5V signaling
levels. PCI5IP is accessible in the memory space on the PCI bus. This guarantees
compatibility with other PCI compliant hardware – most PC’s.

The PCI interface is integrated with the IP interface providing superior performance over
designs relying on a separate PCI interface device. In addition to access speed the
higher level of integration results in fewer initialization steps and requirements, more
flexibility in operation, a higher MTBF, and less complex software with only one Base
Address [BAR] to deal with.

If your project can benefit from a "non-standard" implementation, or features that we
have not thought of, or implemented yet please let us know. The Xilinx has room. For
example; if your project will use IP's that can operate at 33 MHz instead of 32, then we
could synchronize the IP and PCI clocks and save several synchronization steps.

C

D Q

C

D Q

IP REFERENCE CLK

IP RESET

VCC DETECT TIMER

RESET REG BIT

PUSH BUTTON

Page 10 of 32 Embedded Solutions

Wired but not yet implemented. (1) All of the DMA control signals are available for a
future revision to implement.

Wired and User implemented. The IP Strobe signal is connected from each IP slot to a
5 pin header to allow for inter-slot user defined communications. The IP specification
does not define what the strobe can be used for. The header is rarely used. If you
need it please add “–STB” to your order number and we will install the 5 pin header for
you. Standard .025” sq. posts suitable for wire-wrap inter-connection.

On each IP Slot the Strobe signal is connected to pin 46.

FLASH memory is used to program the FPGA. Future updates can be added to your
card with the Xilinx Impact tool should you want to make use of a new feature. For
example with the Revision G FLASH, the PCI Core is now a Dynamic Engineering
design. This is important because we have corrected a defect in the core previously
used which interfered with use in external chassis.

FLASH Revisions:
Initial Release A 4/2002, ported from PCI3IP and added 2 positions plus independent
controls
Rev B 6/03 Add independent bus error status bits
Rev C 6/03 Add 32 bit addressing and dual slot operation capability
Rev D 7/03 Add byte and word swap capability
Rev E 6/09 Add protection for multi-processor operation
Rev F 8/09 minor update for 32 bit addressing with multi-processor protection
Rev G 4/16 Update to use DE designed PCI core, add Readable Revision field
Rev G.1 7/16 Update to add Bus Error status bits to base status register and master
bus error clear control. Modification to Bus Error capture logic. Addition
of readable FLASH major and minor revision.

Strobe Pinout on Header
TP1

1 STB A
2 STB B
3 STB C
4 STB D
5 STB E

FIGURE 3 PCI5IP STROBE CONNECTION TABLE