Dynamic Engineering IP-429-II User Manual

DYNAMIC ENGINEERING

150 DuBois St Suite C, Santa Cruz, CA 95060

831-457-8891 Fax [phone]

Web Page http://www.dyneng.com

E-Mail [e-mail]

Est. 1988

User Manual

IP-429-II

ARINC 429 Interface

IP Module

Revision A1

Corresponding Hardware: 10-2007-0501/2

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IP429-II
ARINC 429 Interface
IP Module

Dynamic Engineering
150 DuBois St Suite C
Santa Cruz, CA 95060
831- 457-8891
831-457-4793 FAX

This document contains information of proprietary interest
to Dynamic Engineering. It has been supplied in
confidence and the recipient, by accepting this material,
agrees that the subject matter will not be copied or
reproduced, in whole or in part, nor its contents revealed in
any manner or to any person except to meet the purpose
for which it was delivered.

Dynamic Engineering has made every effort to ensure that
this manual is accurate and complete. Still, the company
reserves the right to make improvements or changes in the
product described in this document at any time and without
notice. Furthermore, Dynamic Engineering assumes no
liability arising out of the application or use of the device
described herein.

The electronic equipment described herein generates,
uses, and can radiate radio frequency energy. Operation of
this equipment in a residential area is likely to cause radio
interference, in which case the user, at his own expense,
will be required to take whatever measures may be
required to correct the interference.

Dynamic Engineering’s products are not authorized for use
as critical components in life support devices or systems
without the express written approval of the president of
Dynamic Engineering.

This product has been designed to operate with IP Module
carriers and compatible user-provided equipment.
Connection of incompatible hardware is likely to cause
serious damage.

©1998-2015 by Dynamic Engineering.
IndustryPack is a registered trademark of GreenSpring Computers Inc..
Other trademarks and registered trademarks are owned by their
respective manufactures.
Manual Revision A2. Revised November 3rd, 2015

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Table of Contents

PRODUCT DESCRIPTION 6

THEORY OF OPERATION 8

ADDRESS MAP 10

PROGRAMMING 12

Register Definitions 13

IP429II_BASE_REG0 13
IP429II_BASE_REG1 14
IP429II_BASE_REG2 15
IP429II_BASE_REG3 15
IP429II_VECTOR 16
IP429II_STATUS0 17
IP429II_STATUS1 18
IP429II_Parallel 19
IP429_Encoder/Decoder 20
IP429_CHx_CNTL 21
IP429_CHXX_TS 23

Interrupts 24

ID PROM 25

LOOP-BACK 26

IP MODULE LOGIC INTERFACE PIN ASSIGNMENT 27

IP MODULE IO INTERFACE PIN ASSIGNMENT 28

APPLICATIONS GUIDE 29

Interfacing 29

Construction and Reliability 30

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Thermal Considerations 31

WARRANTY AND REPAIR 31

Service Policy 31

Out of Warranty Repairs 31

For Service Contact: 32

SPECIFICATIONS 33

ORDER INFORMATION 34

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List of Figures

FIGURE 1 IP-429 INTERNAL ADDRESS MAP 11
FIGURE 2 IP-429 CONTROL REGISTER 0 BIT MAP 13
FIGURE 3 IP-429 CONTROL REGISTER 1 BIT MAP 14
FIGURE 4 IP-429 CONTROL REGISTER 2 BIT MAP 15
FIGURE 5 IP-429 CONTROL REGISTER 3 BIT MAP 15
FIGURE 6 IP-429 STATUS REGISTER 0 BIT MAP 17
FIGURE 7 IP-429 STATUS REGISTER 1 BIT MAP 18
FIGURE 8 IP-429 CONTROL REGISTER 0 BIT MAP 19
FIGURE 9 IP-429 3282 CONTROL REGISTER BIT MAP 21
FIGURE 10 IP-429 ID PROM STANDARD 25
FIGURE 11 IP-429 LOGIC INTERFACE 27
FIGURE 12 IP-429 IO INTERFACE 28

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Product Description

ARINC 429 is a versatile standardized bus interface. ARINC 429 is robust featuring
Manchester encoding and enough voltage swing to provide excellent noise immunity
and reasonable throughput rates. ARINC 429 is the interface of choice for critical
applications; for example aircraft instrumentation and control. There are many devices
supporting the 429 bus - printers, instrumentation, sensors and more.

IP-429-II makes it easy to gain access to the ARINC 429 bus. Just connect; program a
few registers and use like an IO device. Reference software, schematics and
debugging aides are available in the Engineering Kit.

IP-429-II is an upgrade to the original IP-429 design. Dynamic Engineering designed
the original IP-429 in 1998 and both manufactured and licensed the design.
GreenSpring Computers, and later SBS manufactured the board under their licensing
agreements.

The base version of the upgraded design uses the same address and bit maps. The
design is enhanced with the Time Trigger / Time Stamp capability now being included
on all versions and moved into the IO space. The IO connector has the same signal
definitions. The revision 2 and later boards have FLASH memory instead of the PROM
and the JTAG signals available on the IO connector.

Please refer to the web page for updated versions with enhanced features. The new
versions will have different IDPROM definitions to allow differentiation in your system.
Previously purchased IP-429-II rev B and later boards can be updated to make use of
the new features.

IP-429-II is capable of providing up to 8 Receive and 4 Transmit channels of ARINC 429
compatible IO in one IP position. Each of the eight (8) receive channels has a 32 bit
Time Tag register associated with it. The Time Tag generator operates with a 1 uS
resolution. When each new message is received the Data Ready signal from the 429
decoder device is used to trigger the time stamp for that channel.

In addition to the ARINC 429 capability, a parallel IO port is provided to allow custom
formats and specialized status to be implemented. The hardware is capable of other
formats including 571, 575, and 706 with software set-up changes.

IP-429 supports both the High and Low speed standards for data transmission. A
programmable register allows each TX channel to operate at either rate. Each
transmitter is supported by an 8 deep 32 bit wide FIFO.

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Transmission and Reception can be done on an interrupt or polled basis. The interrupts
are individually maskable. The vector is user programmable by a read/write register.
The interrupt occurs on IntReq0.

The IP interface is 8 and 32 MHz. capable for efficient programming and data transfer.

All configuration registers support read and write operations for maximum software
convenience. Word and byte operations are supported (please refer to the memory
map).

IP-429-II conforms to the VITA standard. This guarantees compatibility with multiple IP
Carrier boards. Because the IP may be mounted on different form factors, while
maintaining plug and software compatibility, system prototyping may be done on one IP
Carrier board, with final system implementation on a different one. Dynamic
Engineering carrier boards have Drivers available for Windows® and Linux. IP-429-II is
supported with a Windows driver included with the purchase of the card. This manual
contains enough data to write your own driver should you prefer to take that approach.

Using IP-429 and a PCI3IP or PCI5IP creates a PCI-429 capability. For example using
an IP-429-4 and a PCI3IP makes a PCI slot compatible ARINC 429 solution with 8
receivers and 4 transmitters. Adding more IP’s can add more channels up to 40
receivers and 20 transmitters in the PCI slot [on a PCI5IP]. Other options are available
for PCIe, cPCI [3U and 6U] and PC104p. Coming soon VPX, cPCIe, and PCIe104
carriers.

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Theory of Operation

IP-429-II is designed for the purpose of transferring data from one point to another with
the ARINC-429 protocol.

IP-429-II features a Xilinx FPGA and industry standard 3282 compatible ARINC 429
receiver / transmitter devices. The FPGA contains the IP interface and control required
for the 429 devices. Each 3282 provides two Receiver channels and one partial
Transmit channel. A separate device provides the “drive” circuitry for the transmit
channel. The ‘3282 data sheet is available on-line from the IP-429 webpage.

IP-429-II is a part of the IP Module family of I/O products. It meets the IP Module VITA
Standard. Contact VITA for a copy of this specification. It is assumed that the reader is
at least casually familiar with this document and logic design. In standard configuration
it is a Type II mechanical with passive low profile components on the back of the board
and one slot wide.

The bus interface to the host CPU is controlled by a logic block within the Xilinx device
that contains the decoding and timing elements required to interface to the IP bus
interface. The timing is referenced to the 8 or 32 MHz IP logic clock. The IP responds to
the ID, INT, MEM and IO selects. The FPGA design requires wait states for read or
write cycles to any address. Hold cycles are supported as required by the host
processor. Data remains enabled during a read until the host removes the SEL line.
Local timing terminates a write cycle prior to SEL being de-asserted.

The interface to the 429 encoder/decoder modules is operated at 100 MHz. to allow for
precise timing with as little wasted time as possible. The IO space decodes for the write
and read functions are set based on the IP clock rate. The state-machine detects the
request and handles the data transfer to/from the encoder/decoder. The number of
wait-states will depend on the IP clock rate in use. At 8 Mhz the timing of the
encoder/decoder is similar which will lead to fewer wait states. At 32 Mhz the IP clock is
faster than the read or write timing to the encoder/decoder leading to more wait-states.
The overall time will be shorter with the 32 MHz clock. If available it [32 MHz] is
recommended for use.

Before transmitting or receiving data IP-429-II requires register programming to select
data rates and formats as well as system clock speed, interrupt masking etc.. Each of
the programmable registers is described in the programming section. Once IP-429-II
has been set-up for operation in your environment, data can be transferred.

To transmit, data is loaded into the transmitter FIFO within the channel of interest and
the transmission enabled. If programmed, an interrupt will alert the host that the data

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has been transferred. If preferred, the TX status can be polled and the transmitter
status determined. Each transmitter channel is independent of the other transmitter
channels.

To receive data another transmitter in the system sends data on the bus, which is
connected, to the IP-429. There are up to eight receive channels per IP-429-II and
each channel can be connected to a different ARINC 429 bus. The Receiver channels
are controlled in pairs for the clock speed. When data is received, an interrupt can be
generated to the host. The interrupt to the host is the ‘OR’ of the interrupt requests from
all of the channels. Each channel has an interrupt mask. There is a status register to
allow the host to determine the cause of the interrupt and to set priorities for responding
to the interrupt(s). The interface can be operated in a polled mode by reading the status
register.

If the system needs to know when data was received, Time Tagging can be useful. IP­429-II supports Time Tagging by providing a 32 bit counter, which operates at 1 MHz to
provide a 1 uS Time Tag count. When the interrupt from any of the receive channels is
asserted the current “time” is registered into one of eight Time Tag registers. The
software can access the registers to read the count. The time should be read before
another interrupt is generated on that channel or the time will be updated for the new
interrupt. The counter is resettable to allow synchronization with a system timer. With
32 bits, the counter will roll over after ~71.58 minutes.

The Time Tag registers are internal to the Xilinx and are loaded automatically. The
registers are aligned to allow reading as longwords – using the automatic double reads
built into Dynamic Engineering carriers.

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Address Map

IO Space

Function Offset Width Type

// IP 429 relative addresses //
#define IP429II_BASE_REG0 0x00 // byte on word boundary
#define IP429II_BASE_REG1 0x02 // byte on word boundary
#define IP429II_BASE_REG2 0x04 // byte on word boundary
#define IP429II_BASE_REG3 0x06 // byte on word boundary
#define IP428II_VECTOR 0x08 // byte on word boundary
#define IP429II_STATUS0 0x0a // byte on word boundary
#define IP429II_STATUS1 0x0c // byte on word boundary
#define IP429II_PARALLEL 0x0e // byte on word boundary
#define IP429II_INFO 0x10 // Driver info register word

#define IP429II_TS_DEV1_CH1_LWR 0x14 Time Tag Device 1 receiver 1 D15..D0 read only
#define IP429II_TS_DEV1_CH1_UPR 0x16 Time Tag Device 1 receiver 1 D31..D16 read only
#define IP429II_TS_DEV1_CH2_LWR 0x18 Time Tag Device 1 receiver 2 D15..D0 read only
#define IP429II_TS_DEV1_CH2_UPR 0x1A Time Tag Device 1 receiver 2 D31..D16 read only

#define IP429II_TS_DEV2_CH1_LWR 0x1C Time Tag Device 2 receiver 1 D15..D0 read only
#define IP429II_TS_DEV2_CH1_UPR 0x1E Time Tag Device 2 receiver 1 D31..D16 read only
#define IP429II_TS_DEV2_CH2_LWR 0x20 Time Tag Device 2 receiver 2 D15..D0 read only
#define IP429II_TS_DEV2_CH2_UPR 0x22 Time Tag Device 2 receiver 2 D31..D16 read only

#define IP429II_TS_DEV3_CH1_LWR 0x24 Time Tag Device 3 receiver 1 D15..D0 read only
#define IP429II_TS_DEV3_CH1_UPR 0x26 Time Tag Device 3 receiver 1 D31..D16 read only
#define IP429II_TS_DEV3_CH2_LWR 0x28 Time Tag Device 3 receiver 2 D15..D0 read only
#define IP429II_TS_DEV3_CH2_UPR 0x2A Time Tag Device 3 receiver 2 D31..D16 read only

#define IP429II_TS_DEV4_CH1_LWR 0x2C Time Tag Device 4 receiver 1 D15..D0 read only
#define IP429II_TS_DEV4_CH1_UPR 0x2E Time Tag Device 4 receiver 1 D31..D16 read only
#define IP429II_TS_DEV4_CH2_LWR 0x30 Time Tag Device 4 receiver 2 D15..D0 read only
#define IP429II_TS_DEV4_CH2_UPR 0x32 Time Tag Device 4 receiver 2 D31..D16 read only

#define IP429II_OE0_DEV1_L 0x40 // read from Device 1 port 1 lower half
#define IP429II_OE0_DEV1_U 0x42 // read from Device 1 port 1 upper half
#define IP429II_OE1_DEV1_L 0x44 // read from Device 1 port 2 lower half
#define IP429II_OE1_DEV1_U 0x46 // read from Device 1 port 2 upper half
#define IP429II_LD1_DEV1 0x48 // write to Device 1 TX port lower half
#define IP429II_LD2_DEV1 0x4a // write to Device 1 TX port upper half
#define IP429II_CNTL_DEV1 0x4c // write to Device 1 control word

#define IP429II_OE0_DEV2_L 0x50 // read from Device 2 port 1 lower half
#define IP429II_OE0_DEV2_U 0x52 // read from Device 2 port 1 upper half
#define IP429II_OE1_DEV2_L 0x54 // read from Device 2 port 2 lower half

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#define IP429II_OE1_DEV2_U 0x56 // read from Device 2 port 2 upper half
#define IP429II_LD1_DEV2 0x58 // write to Device 2 TX port lower half
#define IP429II_LD2_DEV2 0x5a // write to Device 2 TX port upper half
#define IP429II_CNTL_DEV2 0x5c // write to Device 2 control word

#define IP429II_OE0_DEV3_L 0x60 // read from Device 3 port 1 lower half
#define IP429II_OE0_DEV3_U 0x62 // read from Device 3 port 1 upper half
#define IP429II_OE1_DEV3_L 0x64 // read from Device 3 port 2 lower half
#define IP429II_OE1_DEV3_U 0x66 // read from Device 3 port 2 upper half
#define IP429II_LD1_DEV3 0x68 // write to Device 3 TX port lower half
#define IP429II_LD2_DEV3 0x6a // write to Device 3 TX port upper half
#define IP429II_CNTL_DEV3 0x6c // write to Device 3 control word

#define IP429II_OE0_DEV4_L 0x70 // read from Device 4 port 1 lower half
#define IP429II_OE0_DEV4_U 0x72 // read from Device 4 port 1 upper half
#define IP429II_OE1_DEV4_L 0x74 // read from Device 4 port 2 lower half
#define IP429II_OE1_DEV4_U 0x76 // read from Device 4 port 2 upper half
#define IP429II_LD1_DEV4 0x78 // write to Device 4 TX port lower half
#define IP429II_LD2_DEV4 0x7a // write to Device 4 TX port upper half
#define IP429II_CNTL_DEV4 0x7c // write to Device 4 control word

FIGURE 1 IP-429 INTERNAL ADDRESS MAP

The address map provided is for the local decoding performed within the IP-429. The
addresses are all offsets from a base address. The carrier board where the IP is
installed provides the base address and controls the “naming of the bytes”. We refer to
the bytes following Motorola conventions i.e. upper is D15-D8 and lower is D7-D0.
When byte wide data is located on the lower byte then an odd address results or the
use of a word access using only the lower byte of data. We prefer the word oriented
approach because it is more consistent across platforms.

Please note the double wide registers for TX and RX data functions are located on LW
boundaries allowing for 32 bit read or write actions with carriers that support automatic
32 ó 16 conversion. All Dynamic Engineering carriers have this feature.

IP-429-II can have up to 4 of the encoder/decoder “chips” installed. The –1 version has
device 1 installed , -2 has both device 0 and device 1 and so forth. The names for the
decodes above have the chip number followed by the port within the chip and the
function. For example IP429II_OE1_DEV3_U is the upper half data read from chip 3
port 1. The OE, LD, CNTL etc. can be used as a guide to the IC function name when
comparing with the schematic or datasheet.