DSP TP400 PC, TP104-plus, 104-plus Reference Manual

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TP400 PC/104-PLUS

PC COMPATIBLE COMPUTER

TECHNICAL REFERENCE MANUAL

Revision B00 19 February 2001

TRM-TP400 158004.B00 CGP

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All information in this manual is believed to be accurate and reliable. However, no responsibility is assumed by DSP Design Limited for its use. Since conditions of product use are outside our control, we make no warranties express or implied in relation thereto. W e therefore cannot accept any liability in connection with any use of this information. Nothing herein is to be taken as a license to operate under or a recommendation to infringe any patents.

Whilst every ef fort has been made to ensure that this document is correct , er rors can occur. If you find any errors or omissions please let us know, so that we can put this right.

All information contained in this manual is proprietary to DSP Design Limited and cannot be reproduced without the consent of DSP Design Limit ed. The circuit design and printed circuit board design is copyright of DSP Design Limited 2000.

DSP Design Limited Tapton Park Innovation Centre Brimington Road Chesterfield S41 0TZ United Kingdom

Tel +44 (0) 1246 545 910 Fax +44 (0) 1246 545 911 Email sales@dspdesign.com Web: www.dspdesign.com

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158004.B00 i

CONTENTS

1 INTRODUCTION ..................................................................................................1

1.1 OVERVIEW .......................................................................................................................................1

1.2 TP400 FEATURES............................................................................................................................2

1.3 PC/AT COMPATIBILITY....................................................................................................................3

1.4 PC/104-PLUS AS A PC EXPANSION BUS......................................................................................4

1.5 THE TP400 ARCHITECTURE..........................................................................................................4

1.6 GETTING STARTED QUICKLY .......................................................................................................7

1.6.1 TCDEVPLUS and TCDEV Development Systems ..................................................................7

1.6.2 Using the TCDEVPLUS Development System ........................................................................8

1.6.3 Using the Rev D TCDEV Development System.......................................................................9

1.6.4 TCONN Connector Breakout Board .......................................................................................11

1.7 AVOIDING COMMON PROBLEMS................................................................................................12

2 PROCESSOR AND MEMORY...........................................................................13

2.1 PROCESSOR..................................................................................................................................13

2.2 CLOCK.............................................................................................................................................15

2.3 SDRAM............................................................................................................................................16

2.4 FLASH MEMORY............................................................................................................................17

2.5 MEMORY ADDRESS MAP.............................................................................................................18

3 PERIPHERALS...................................................................................................19

3.1 I/O ADDRESS MAP.........................................................................................................................19

3.2 SUPER I/O CHIP.............................................................................................................................21

3.3 EXTRA UART..................................................................................................................................21

3.4 SERIAL PORTS...............................................................................................................................21

3.4.1 Signals, Addressing and Interrupts.........................................................................................21

3.4.2 RS-485 Operation....................................................................................................................22

3.4.3 Disabling Serial Ports ..............................................................................................................23

3.4.4 Extended Modes......................................................................................................................23

3.4.5 Infra-Red Operation Modes.....................................................................................................23

3.5 PRINTER PORT..............................................................................................................................24

3.6 REAL TIME CLOCK........................................................................................................................25

3.7 KEYBOARD AND MOUSE..............................................................................................................26

3.8 FLOPPY DISK DRIVE.....................................................................................................................27

3.9 IDE DISK DRIVE..............................................................................................................................27

3.10 DISPLAY CONTROLLER................................................................................................................29

3.10.1 Overview..................................................................................................................................29

3.10.2 Using CRTs and TFT LCDs....................................................................................................30

3.10.3 External Graphics Cards, and No Graphics ...........................................................................31

3.10.4 Native Display Drivers.............................................................................................................32

3.10.5 The System Management Interrupt Issue ..............................................................................32

3.10.6 PanelLink.................................................................................................................................33

3.10.7 TV Clock..................................................................................................................................33

3.11 VIDEO PLAYBACK..........................................................................................................................34

3.12 AUDIO RECORDING AND PLAYBACK.........................................................................................34

3.13 SPEAKER........................................................................................................................................34

3.14 USB PORTS....................................................................................................................................35

3.15 ETHERNET .....................................................................................................................................35

3.16 ANALOG TO DIGITAL CONVERTER............................................................................................36

3.17 SERIAL EEPROM ...........................................................................................................................38

3.18 UTILITY REGISTER........................................................................................................................38

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4 STAND-ALONE OPERATION AND EXPANSION BUSES...............................40

4.1 STAND-ALONE OPERATION........................................................................................................ 40

4.2 PC/104 BUS.................................................................................................................................... 40

4.3 PC/104-PLUS BUS........................................................................................................................... 41

4.4 PC/104 AND PC/104-PLUS CLOCK AND RESET SIGNALS.........................................................43

4.4.1 PC/104 Clock and Reset Signals............................................................................................ 43

4.4.2 PC/104-Plus Clock and Reset Signals ...................................................................................43

4.5 INTERRUPTS .................................................................................................................................44

4.5.1 On-Board and PC/104 Bus Interrupts..................................................................................... 44

4.5.2 PC/104-Plus Bus Interrupts ....................................................................................................45

4.5.3 Plug and Play Control of Interrupts......................................................................................... 46

4.6 DMA.................................................................................................................................................47

5 HARDWARE RESET OPTIONS ........................................................................48

5.1 POWER SUPPLY MONITOR......................................................................................................... 48

5.2 ONBOARD WATCHDOG TIMER...................................................................................................48

5.3 RESET SWITCH.............................................................................................................................49

5.4 RESETTING THE PC/104 AND PC/104-PLUS BUSES .................................................................49

6 SOFTWARE...........................................................................................................50

6.1 SYSTEM BIOS................................................................................................................................50

6.2 BIOS SETUP PROGRAM...............................................................................................................50

6.2.1 Operation of the Setup Program............................................................................................. 51

6.2.2 Reducing Boot Time ...............................................................................................................52

6.3 VGA BIOS AND OTHER BIOS EXTENSIONS.............................................................................. 52

6.3.1 Principles of Operation............................................................................................................ 52

6.3.2 The VGA BIOS Extension.......................................................................................................52

6.3.3 The Flash File System BIOS Extension .................................................................................53

6.4 MS-DOS AND OTHER OPERATING SYSTEMS..........................................................................53

6.5 FLASH MEMORY PROGRAMMING............................................................................................. 54

6.5.1 Programming the 2M byte 29F016 Flash Chips.....................................................................54

6.5.2 Programming the 4M byte 29F032 Flash Chips.....................................................................56

6.5.3 Steps to Perform after Programming BIOS............................................................................ 57

6.6 FLASH FILE SYSTEM.................................................................................................................... 57

6.6.1 Overview..................................................................................................................................58

6.6.2 Operation of the Flash File System ........................................................................................59

6.6.3 Write Operations and Garbage Collection.............................................................................. 60

6.6.4 Flash File System Statistics....................................................................................................61

6.7 SAVING CMOS RAM DATA IN THE SERIAL EEPROM............................................................... 62

6.8 SERIAL EEPROM PROGRAMMING.............................................................................................63

6.9 WATCHDOG TIMER PROGRAMMING ........................................................................................64

7 POWER MANAGEMENT ...................................................................................65

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APPENDIX A: SPECIFICATION...............................................................................A1

APPENDIX B: TP400 SET-UP PROCEDURE.........................................................B1

B.1 PROCESSOR COOLING................................................................................................................B1

B.2 SDRAM CONFIGURATION............................................................................................................B1

B.3 SOLDER LINK AREAS....................................................................................................................B2

LK1 - LK4 Not Present .....................................................................................................................B2

LK5 PME# Connection........................................................................................................................B2

LK6 VREF or Microphone..................................................................................................................B2

LK7 ADC0 or LINE_IN_R....................................................................................................................B2

LK8 ADC1 or LINE_IN_L....................................................................................................................B3

LK9 ADC2 or LINE_OUT_R ...............................................................................................................B3

LK10 ADC3 or LINE_OUT_L............................................................................................................B3

LK11 A/D Converter Reference........................................................................................................B3

LK12 Clock Shutdown.......................................................................................................................B3

LK13 Super I/O Configuration...........................................................................................................B3

LK14 VREF or Microphone..............................................................................................................B4

LK15 COM2 RS-232/RS-485 Selection ...........................................................................................B4

LK16 Remote Bootstrap ...................................................................................................................B4

LK17 Not Present..............................................................................................................................B4

LK18 PC/104-Plus VI/O Selection....................................................................................................B4

LK19 PanelLink Disable....................................................................................................................B4

LK20 PanelLink Power......................................................................................................................B5

LK100 - LK102 Processor Clock Speed ..............................................................................................B5

LK103 A/D Converter Input ADC3......................................................................................................B5

LK104 - LK107 Vcore Voltage Selection. ................................................................................................B6

LK108 Power Supply Clock ................................................................................................................B6

LK109 Ethernet Serial EEPROM........................................................................................................B6

LK110 Ethernet TxD Circuit................................................................................................................B6

LK111 Ethernet PCI Slot Selection.....................................................................................................B6

LK112 Ethernet PCI Interrupt Selection..............................................................................................B6

LK113 SDRAM Clock Feedback ........................................................................................................B7

LK114 IDE /PDIAG Pin .......................................................................................................................B7

APPENDIX C: MECHANICAL DRA WINGS AND SCHEMATICS........................... C1

APPENDIX D: OPTIONS AND ORDERING INFORMATION..................................D1

D.1 PROCESSOR BOARDS................................................................................................................D1

D.2 SDRAM MEMORY MODULES...................................................................................................... D1

D.3 TP400 PROCESSOR STARTER PACK........................................................................................ D2

D.4 PC/104 I/O BOARDS...................................................................................................................... D3

D.5 ACCESSORIES.............................................................................................................................. D4

APPENDIX E: CONNECTOR PIN ASSIGNMENTS ................................................ E1

E.1 SUMMARY OF CONNECTORS.....................................................................................................E1

E.2 EXPANSION BUS CONNECTORS................................................................................................E2

E.3 TP400 PERIPHERAL CONNECTOR.............................................................................................E5

E.4 COM3, COM4 SERIAL PORT CONNECTOR................................................................................E7

E.5 AUDIO, A/D CONVERTOR AND CRT CONNECTOR ..................................................................E7

E.6 PANELLINK CONNECTOR ...............................................................................................................E8

E.7 FLAT PANEL CONNECTOR ..........................................................................................................E9

E.8 USB CONNECTOR...................................................................................................................... E10

E.9 IDE CONNECTOR ....................................................................................................................... E11

E.10 FLOPPY CONNECTOR............................................................................................................... E12

E.11 POWER SUPPLY AND FAN CONNECTORS............................................................................ E13

E.12 ETHERNET CONNECTOR ......................................................................................................... E13

E.13 INTER-BOARD CONNECTORS.................................................................................................. E14

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APPENDIX F: TFTIF FLA T PANEL INTERFACE BOARDS...................................... F1

F.1 INTRODUCTION.............................................................................................................................F1

F.2 INSTALLATION...............................................................................................................................F2

F.3 CABLE LENGTHS...........................................................................................................................F2

F.4 TFTIF CONNECTOR AND SOLDER LINKS.................................................................................F3

F.5 TFTIF41 CONNECTOR AND SOLDER LINKS.............................................................................F4

F.6 TFTIF31 CONNECTOR AND SOLDER LINKS.............................................................................F5

F.7 TFTIFS15 CONNECTOR AND SOLDER LINKS...........................................................................F7

APPENDIX G: CF100 COMPACT FLASH IDE DRIVE...............................................G1

G.1 INTRODUCTION............................................................................................................................ G1

G.2 INSTALLING THE CF100 ONTO THE TP400.............................................................................. G1

G.2.1 Direct Connection................................................................................................................... G1

G.2.2 Cable Connection................................................................................................................... G2

G.3 INSTALLING THE COMPACT FLASH CARD INTO THE CF100................................................ G2

G.4 CONFIGURING THE TP400 FOR THE CF100 AND CARD........................................................ G2

G.5 USING COMPACT FLASH CARDS.............................................................................................. G3

G.5.1 Hot Plugging........................................................................................................................... G3

G.5.2 Formatting and Making the Card Bootable............................................................................ G3

G.5.3 Configuring the CF100 as a slave drive................................................................................. G3

G.6 ACCESSORIES.............................................................................................................................. G4

G.7 DIMENSIONS................................................................................................................................. G4

APPENDIX H: RELIABILITY.......................................................................................H1

H.1 ASSUMPTIONS AND METHODOLOGY.......................................................................................H1

H.1.1 Reliability Standard..................................................................................................................H1

H.1.2 Methodology............................................................................................................................H1

H.1.3 Failure Effect Assumptions.....................................................................................................H2

H.2 RELIABILITY DATA USEAGE........................................................................................................H2

H.2.1 Operating Temperature...........................................................................................................H2

H.2.2 Flash Memory Usage..............................................................................................................H2

H.2.3 Usage Environment.................................................................................................................H2

H.2.4 Sensitivity Analysis..................................................................................................................H3

H.3 RELIABILITY DATA ............................................................................................................... .........H3

APPENDIX J: TP400ET ETHERNET ADAPTER BOARD..........................................J1

APPENDIX K: TP400 USB ADAPTER BOARD.........................................................K1

APPENDIX L: FAULT REPORTING ...........................................................................L1

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TABLES

TABLE 1 - TP400 PERFORMANCE RATINGS.........................................................................................14

TABLE 2 - TP400 ADDRESS MAP - FIRST 1M BYTE.............................................................................18

TABLE 3 - ON-BOARD I/O DEVICES.......................................................................................................20

TABLE 4 - SDRAM ALLOCATED TO DISPLAY CONTROLLER ............................................................29

TABLE 5 - TFT PANEL DISPLAY RESOLUTIONS..................................................................................30

TABLE 6 - CRT DISPLAY RESOLUTIONS ..............................................................................................31

TABLE 7 - UTILITY REGISTER BIT ALLOCATIONS...............................................................................39

TABLE 8 - PCI BUS RESOURCE ALLOCATIONS ..................................................................................42

TABLE 9 - INTERRUPT ALLOCATION....................................................................................................45

TABLE B1 - SODIMM MODULES..............................................................................................................B1

TABLE B2 - PROCESSOR CLOCK SPEED.............................................................................................B5

TABLE B3 - VCORE VOLTAGE SELECTION..........................................................................................B6

TABLE D1 - PROCESSOR BOARDS...................................................................................................... D1

TABLE D2 - SDRAM MEMORY MODULES............................................................................................ D1

TABLE D3 - CONTENTS OF THE TP400PAK........................................................................................ D2

TABLE D4 - PC/104 I/O BOARDS............................................................................................................ D3

TABLE D5 - TP400 ACCESSORIES........................................................................................................ D4

TABLE D6 - COMPACT FLASH ACCESSORIES ................................................................................... D5

TABLE E1 - CONNECTORS USED ON TP400 MAIN BOARD...............................................................E1

TABLE E2 - CONNECTORS USED ON TP400 DAUGHTER BOARD ...................................................E1

TABLE E3 - PC/104 J2 PIN ASSIGNMENTS ...........................................................................................E2

TABLE E4 - PC/104 J1 PIN ASSIGNMENTS ...........................................................................................E3

TABLE E5 - PC/104-PLUS J3 PIN ASSIGNMENTS ................................................................................E4

TABLE E6 - RS485 FUNCTION OF COM2 SERIAL PORT.....................................................................E5

TABLE E7 - J4 I/O CONNECTOR PIN ASSIGNMENTS..........................................................................E6

TABLE E8 - J5 COM3, COM4 CONNECTOR PIN ASSIGNMENTS.......................................................E7

TABLE E9 - J6 VGA AND A/D CONNECTOR PIN ASSIGNMENTS.......................................................E8

TABLE E10 - J7 PANEL LINK CONNECTOR PIN ASSIGNMENTS.......................................................E8

TABLE E11 - J8 FLAT PANEL CONNECTOR PIN ASSIGNMENTS ......................................................E9

TABLE E12 - FUNCTION OF FLAT PANEL SIGNALS......................................................................... E10

TABLE E13 - J9 USB CONNECTOR PIN ASSIGNMENTS.................................................................. E10

TABLE E14 - J101 IDE CONNECTOR PIN ASSIGNMENTS............................................................... E11

TABLE E15 - J103 FLOPPY CONNECTOR PIN ASSIGNMENTS....................................................... E12

TABLE E16 - J101 POWER SUPPLY CONNECTOR PIN ASSIGNMENTS........................................ E13

TABLE E17 - J102 POWER SUPPLY CONNECTOR PIN ASSIGNMENTS........................................ E13

TABLE F1 - TFTIF BOARDS AND THEIR DISPLAYS.............................................................................F1

TABLE F2 - TFTIF DISPLAY PIN ASSIGNMENTS..................................................................................F3

TABLE F3 - TFTIF41 DISPLAY PIN ASSIGNMENTS..............................................................................F4

TABLE F4 - TFTIF41 SOLDER LINK CONNECTIONS............................................................................F5

TABLE F5 - TFTIF31 DISPLAY PIN ASSIGNMENTS..............................................................................F5

TABLE F6 - TFTIF31 SOLDER LINK CONNECTIONS............................................................................F6

TABLE F7 - TFTIF31 AND TFTIF41 J3 PIN ASSIGNMENTS .................................................................F6

TABLE F8 - TFTIFS15 J4 PIN ASSIGNMENTS.......................................................................................F7

TABLE F9 - TFTIFS15 PIN ASSIGNMENTS............................................................................................F8

TABLE H1 - TP400 RELIABILITY DATA.................................................................................................. H5

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FIGURES

FIGURE 1

- TP400 BLOCK DIAGRAM....................................................................................................... 6

FIGURE 2 - RECOMMENDED BATTERY BACK-UP CIRCUIT ..............................................................26

FIGURE C1 - MAIN BOARD TOP COMPONENT PLACEMENT ............................................................C2

FIGURE C2 - MAIN BOARD BOTTOM COMPONENT PLACEMENT....................................................C3

FIGURE C3 - DAUGHTER BOARD TOP COMPONENT PLACEMENT.................................................C4

FIGURE C4 - DAUGHTER BOARD BOTTOM COMPONENT PLACEMENT ........................................C5

FIGURE C5 - MAIN BOARD MECHANICAL DIMENSIONS....................................................................C6

FIGURE C6 - DAUGHTER BOARD MECHANICAL DIMENSIONS.........................................................C7

FIGURE H1 - TP400 MEAN TIME TO FAILURE......................................................................................H4

FIGURE H2 - TP400 UNIT FAILURE RATE.............................................................................................H4

FIGURE J1 - TP400ET MECHANICAL DRAWINGS ...............................................................................J2

FIGURE J2 - TP400ET CIRCUIT DIAGRAM............................................................................................ J2

FIGURE K1 - TP300USB MECHANICAL DRAWINGS............................................................................K2

FIGURE K2 - TP300USB CIRCUIT DIAGRAM.........................................................................................K2

REVISION HISTORY

B00 First release of this manual.

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1 INTRODUCTION

1.1 OVERVIEW

To maintain our lead in advanced and highly integrated PC compatible computers, DSP Design have released a very highly integrated, high performance processor board compliant with the PC/104-Plus V1.1 specification. The board has been specially designed to allow low power operation.

This processor card is fitted with the National Semiconductor Geode GX1 high integration processor chip set, which operates at up to 300MHz. The Geode GX1 is a Pentium-class processor, with MMX instruction set capability. The Geode GX1 incorporates a high-perf ormance graphics controller and audio processor. The chip set integrates many of the functions commonly found in core logic chips on PC motherboards and provides a num ber of power saving features. Both ISA bus and PCI bus interfaces are provided.

The consequence of using the Geode GX1 chip set is that an extremely high performance PC compatible computer can be implemented in a very small form factor.

The TP400 is the first processor board from DSP Design that complies with the PC/104-Plus standard. The PC/104-Plus standard adds a PCI bus interface to the PC/104 standard, thus allowing the use of high- performance PCI expansion boards while retaining the small size and rugged construction of t he PC/104 bus boards. The PCI bus connector is a 120-pin connector on the edge of the PCB opposite the PC/104 connectors.

The board supports up to 256M bytes of high-speed SDRAM. It also features the

standard PC compatible floppy and IDE disk interfaces, serial ports, parallel port, keyboard interface, PS/2 mouse port and the standard PC speaker. The powerful graphics controller in the Geode GX 1 can dr ive both CRT and flat panel displays, and a SoundBlaster-compatible sound system is also implemented in the Geode GX1. Two USB ports, a 10/100Base-T Ethernet interface and an A/D converter are also provided.

The TP400 is a single board PC/104-Plus compatible comput er t hat can operate as a

stand-alone module or can be used in a system consisting of a number of other PC/104 or PC/104-Plus modules.

The standard TP400 boards are provided with Flash File System software, which

converts the on-board 2M byte flash chip into a solid-state read/write disk drive. Up t o 8M bytes of Flash memory can be fitted, subject to a minimum order quantity.

A range of other PC/104 boards is available from DSP Design. Various designs

include the TP300, An earlier version of the T P400 with 10base-T Ethernet, and the TB486, a highly integrated low-power single board computer. A wide range of I/O boards is available. Contact DSP Desig n f or up- to-dat e inf orm ation on ot her product s in our range.

The TP400 provides connectors with the same pin assignments as other DSP Design

processor boards, for easy upgrading.

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1.2 TP400 FEATURES

• High integration processor: a Geode GX1 processor is fitted, running at up to 300MHz.

• PC/104 V2.3 16-bit bus interface for wide compatibility.

• PC/104-Plus connector is fitted to allow PCI expansion cards to be used.

• Floppy and IDE disk controllers.

• Four serial ports - three are RS-232 compatible and one provides TTL level

signals only. COM2 is user-configurable as RS-485.

• The CO M2 serial port can be optionally config ured for IrDA-compatible infrared serial communications.

• Bi-directional Centronics parallel port. EPP and ECP compatible.

• Up to 256M bytes of SDRAM. SDRAM is implemented with a user-installable 144-

pin SODIMM module (dual in line memory module). 32M, 64M, 128M and 256M byte modules are available.

• 2M-byte flash memory for BIOS and solid-state disk is fitted as standard. Alternatively 4M or 8M bytes may be fitted by special order. A Flash File System is provided with every TP400, to provide a read-write logical disk drive.

• Keyboard, PS/2 mouse and speaker ports.

• Two high-speed USB ports. Filter components and a dual USB socket are

provided on a small PCB (the T P300USB) which connects via twisted pair cable to the TP400

• The Geode GX1 integrates graphics circuitry, providing VGA graphics on CRT monitors at resolutions of up to 1280 x 1024 and TFT displays at resolutions of up to 1024 x 768. The graphics accelerator uses part of the system memory for high performance and low system cost. MMX instruction set and MPEG hardware acceleration enhance video performance.

• High-speed serial PanelLink interface to drive displays over twisted pair cable at a distance of up to 10m.

• The Geode GX1 integrates a SoundBlaster compatible sound system. The TP400 can record and play back high-quality audio.

• 10/100Base-T Ethernet chip. The Ethernet magnetics and RJ45 socket are provided on a small PCB (the TP400ET, an optional extra) that connects via twisted pair cable to the TP400.

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• Powered by a single 5V supply. A switched mode power supply is provided to efficiently produce 2.2V and 3.3V for the processor and memory that require these voltages.

• Millennium compliant AT compatible calendar/clock chip uses external battery.

• A 512-byte size serial EEPROM is provided to retain set-up parameters in the

absence of an external battery. Space is also available for user data.

• Reset, power supply monitor and watchdog timer circuitry.

• Expansion is by way of a full-function PC/104 bus that complies with the V2.3

version of the PC/104 bus specification. High performance expansion is by way of the PCI-compatible PC/104-Plus connector.

• The TCDEVPLUS Development System provides all the facilities to get your TP400 running quickly, and is recommended for fast product development.

• Largely pin compatible with the TC386, TC486, TX486, TC586, TB486 and TP300 processors.

1.3 PC/AT COMPATIBILITY

The TP400 offers an extremely high degree of compatibility with desktop PC computers. This compatibility extends from the operating system level, through BIOS-level compatibility to register-level compatibility.

The Geode GX1 chip set used on the TP400 board includes on-chip peripherals timers, interrupt controller, DMA controller etc. These are software compatible with equivalent Intel peripheral chips used on the original IBM PC and PC/AT.

Around the Geode GX1 chip DSP Design has integrated floppy and IDE disk controllers, a keyboard and mouse controller, four serial ports and a Centronics parallel port. These peripherals are software and hardware compatible with the standard PC.

The Geode GX1’s in-built graphics circuitry provides for VGA, SVGA and XGA graphics. Windows drivers provide access to the high performance 2D graphics accelerator engine. Audio logic within the Geode GX1 chip set is also software compatible with SoundBlaster industry-standard sound chips. Note that some aspects of the VGA and SoundBlaster circuitry are em ulated in software, which can lead to some incompatibilities.

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1.4 PC/104-PLUS AS A PC EXPANSION BUS

Users can operate the TP400 as a single board computer . If expansion is required I/O boards can be accessed via the PC/104 and PC/104-Plus interfaces provided on the TP400.

The PC/104 bus is a compact version of the IEEE P996 (PC and PC/AT) bus, optimized for embedded systems applications. DSP Design and other PC/104 manufacturers offer a wide range of I/O boards that will work with the TP400, in the same manner that a conventional PC can be enhanced by the addition of expansion boards.

The PC/104 I/O card range includes analog and digital I/O cards, serial comms, local area network boards and other specialist functions. DSP Design manufactures a number of PC/104 modules and is committed t o expanding this range. It is the policy of DSP Design to introduce, where appropriate, new PC/104 I/O cards that are software compatible with similar cards for the PC. This has the tremendous advantage of allowing users to make use of the software that has already been written for desktop PC cards.

The PC/104-Plus specificat ion enhances the PC/104 specification by adding a new 120-pin connector. This connector consists of four rows of thirty pins each arr anged in a 2mm-pitch grid. It is positioned on the board edge opposite the PC/104 bus connectors. This new connector carries the PCI bus signals, allowing the TP400 to access high-performance PCI chips on expansion boards.

PC/104 and PC/104-Plus boards stack one on top of another, providing a compact, rugged computer system. For details of the PC/104 bus specification and the PC/104-Plus specification, see DSP Design’s web site.

Because the Geode GX1 may require a heat sink or fan, the T P400 must be the top board in a stack of PC/104 boards.

1.5 THE TP400 ARCHITECTURE

The block diagram in Figure 1 shows the archit ecture of the TP400. The Geode GX1 processor is directly connected to the SDRAM through a 64-bit wide high-speed memory bus. It also performs t he “north bridg e” functions, accessing most of the rest of the circuitry through the PCI bus.

The CS5530A companion chip provides the south bridge funct ions, and implements an ISA bus interface to the PC/104 bus and slower peripherals. The CS5530A includes a high-speed Ultra-ATA disk interface, USB ports and motherboard functions (timers, interrupt and DMA controllers etc).

A high-speed connection between the Geode GX1 and the CS5530A transfers graphics and video data from the Geode GX1 to the CS5530A, which drives both analog CRT monitor s and TFT LCD displays. A PanelLink interf ace chip is attached to the TFT LCD interface.

The Geode GX1 and CS5530A are also linked by the PCI bus, which goes to the Ethernet chip and to the PC/104-Plus connector.

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The audio processor logic in the CS5530A chip connects to an AC97 compatible audio codec chip, which provides audio A/D and D/A conversions.

The CS5530A also provides a slower PC/104 bus (ISA bus), on which the Flash memory and Super I/O chips are located. The Super I/O chip includes the floppy and IDE disk controllers, serial and parallel I/O functions as well as the keyboard and mouse controller. A second dual UART chip implements COM3 and COM4.

A 16-bit PC/104 interface allows the TP400 to perform memory and I/O accesses to the PC/104 bus, and a PC104/Plus interface allows PCI bus transfers.

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FIGURE 1 - TP400 BLOCK DIAGRAM

+5V

PC/104-PLUS

Geode GX1

SDRAM

5530A

SUPER I/O

AC97

CODEC

A/D

E2PROM +

RESET

FLASH

UARTS

ETHERNET

SPKR

CRT

Utility Register

POWER

SUPPLY

2.0V

3.3V

CLOCK

GEN.

J10

IDE

J9 J8

USB

TFT

CRT AUDIO

A/D

ETHERNET

J106

J1/J2

PC/104

COM3 COM4

SPEAKER COM1 COM2 PRN KBD

MOUSE IRDA BATT

FLOPPY

Video + Graphics

PCI Bus

RS232

RS232 / RS485

J10

PANELLINK

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1.6 GETTING STARTED QUICKLY

This manual gives all of the inform ation that most users will need in order to operate the TP400. This section g ives a quick introduction to g etting started. More details on configuring the board are given in Appendix B: TP400 Setup Procedure. Those people who have special requirements m ay require further information. If this is the case our support engineer s will be pleased to help you, but please read the manual first.

As well as reading this section, please read section 1.7 which identifies common problems.

1.6.1 TCDEVPLUS and TCDEV Development Systems

DSP Design strongly recommend developing with the TCDEVPLUS Development System, as in our experience this significantly reduces development tim e and users’ technical problems.

The TCDEVPLUS is a PC/104 based development platform. It supercedes the TCDEV development system that many DSP Design’s customers may already have. The TCDEVPLUS adds new features to those of the TCDEV, and customers who already have a TCDEV can continue to use it, although they will not benefit f rom the new features added to the TCDEVPLUS. Throughout this manual the term “TCDEVPLUS” can be read as “TCDEV or TCDEVPLUS”, except where explicitly noted. In particular, jumper areas E2 – E7 have the same functions on both boards.

The features of the TCDEVPLUS include an on-board VGA g raphics controller with 15 pin VGA connector, a floppy and hard disk controller , a floppy drive plus cable, PC/AT and PCI slots f or interfacing standard PC and PCI bus cards to the PC/104 bus and a battery for CMOS RAM backup. The TCDEVPLUS has all the st andard PC connectors for interf acing to the outside world. These include serial port 9-way D-type connectors, a parallel port 25-way D-type connector, a VGA connector and PS/2 style keyboard and mouse connectors. Connectors for the TP400’s Ethernet and USB ports are also provided on the TCDEVPLUS (but not on the TCDEV).

The TCDEVPLUS (but not the TCDEV) provides convenient options for connecting t o

2.5” and 3.5” IDE drives, CD-ROM drives and Compact Flash cards. It allows power

consumption to be monitored and provides diagnostic LEDs with programmable address decoding. It also supports DSP Design’s GCAT486 range of embedded PC computers.

DSP Design also supply the TPPSU, which is a compact 45W power supply with cabling to make it easy to use with the TCDEVPLUS. The 25W TCPSU power supply that we have supplied with the TCDEV in the past may not have enough capacity to drive the TP400 and TCDEVPLUS, particularly if disk drives and other peripherals are used. Users with a TCPSU should ensure they obtain the TPPSU supply.

Most users will find getting started with the TP400 and TCDEVPLUS simplicity itself. The TP400 plugs directly onto the TCDEVPLUS. A 50-way ribbon cable connects the TP400 J4 I/O connector to the TCDEVPLUS. This links the COM1 and COM2 serial ports, parallel port, and keyboard and m ouse onto the TCDEVPLUS, and in turn to the PC compatible connectors mounted on t he edge of the T CDEVPLUS board. The

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TCDEVPLUS (but not the TCDEV) also includes 14-way ribbon cable connects to the TP400 J5 connector, making connections for COM3 and COM4.

The TP400 includes its own VGA, floppy and IDE disk controller s, and VGA, floppy and IDE disk controllers are also present on the TCDEVPLUS. It is possible to use either the VGA and disk controllers on the TP400 or the controllers on the TCDEVPLUS (though not a mixture of both). These instructions assume that the VGA controller and floppy disk controller on the TCDEVPLUS are used initially, as this will be more convenient during early stages of development. Users can move to the TP400’s on-board disk and graphics controllers as the development process progresses.

The next two sections describe using the TCDEVPLUS and the TCDEV with the TP400. Note that the old REV B TCDEV cannot be used with the TP400. The old REV B TCDEV boards can be identified by having only one site for PC/104 boards, and only one power LED.

1.6.2 Using the TCDEVPLUS Development System

To use the system, first inst all an SDRAM SODIMM module into the TP400 SDRAM socket, observing its polarity, and observing proper anti-static precautions. The SODIMM socket has a lug that engages with a cutout on the module, which prevents incorrect installation.

A fan or heatsink should be added to t he TP400, as it may ge t too hot without one. A heatsink is supplied as part of the TP400PAK starter pack (see Appendix D for details).

Enable the floppy disk controller and VGA graphics on the TCDEVPLUS. This is done by setting the jumpers at jumper areas E3 and E5 to the "EN" position. Disable the IDE disk controller on the TCDEVPLUS by setting jumper E4 to the “DIS” position. The TCDEVPLUS COM4 UART should be disabled at E8. The battery back-up jumper should be set in the BATT position at E2. The status LED jumpers at E7 should both be set in the 1 - 2 position. At jumper area E6 set t he C000 jumper to the "EN" position and the other seven jumpers to t he "DIS" position. T he speaker should be enabled by fitting a jumper at E1. T he GCAT486 pr inter should be disabled at E9. Jumpers should be removed from E10 and E11.

Plug the TP400 onto the TCDEVPLUS and connect the 50-way and 14-way ribbon cables from J4 and J5 of the TP400 to the corresponding connectors on the TCDEVPLUS. Ensure that pin 1 of the TP400 connectors go to pin 1 of the TCDEVPLUS connectors. Failure to connect the 50-way cable correctly may damage the equipment.

Connect but do not switch on the TPPSU. (Note that t he TPPSU power connector is polarized. Ensure that the locking tab on the power supply cable mates with the locking tab on the TCDEVPLUS connector). Failure to connect t he power supply

cable assembly correctly may damage the equipment.

Connect the keyboard and VGA monitor to the appropriate connectors. Insert a bootable f loppy disk into the TCDEVPLUS floppy disk drive and switch the

power supply on. The computer should begin booting. You may press the F2 key

158004.B00 9

before or during the memor y test to enter t he Setup prog ram, where you can change the time and date and make ot her changes. The "EXIT" menu option allows you to save the settings in CMOS RAM and exit.

While using the TCDEVPLUS’s floppy disk controller the BIOS will print a warning message to the effect that it is disabling the floppy disk controller on board the TP400.

You should now boot DOS from the floppy disk drive on the TCDEVPLUS. An alternative to using floppy disks is to mak e use of the hard disk present on the

TP400 or the TCDEVPLUS. You m ay connect an IDE drive, or Compact Flash card installed in the CF100 adapter , t o the 44-way IDE connector J100 on the T P400. T he BIOS will automatically detect the drive’s parameters.

Alternatively, you may use the IDE controller on the TCDEVPLUS. T his allows you to connect to both 2.5” and 3.5” IDE drives, and to make use of the Compact Flash socket on the TCDEVPLUS. To use the TCDEVPLUS IDE controller you must enable it at jumper E4, and use t he BIOS Setup program to disable the TP400’s on-board IDE controller.

(The IDE disk controller on the TCDEVPLUS is slower than the controller on the TP400, but it offers the convenience of the wider range of connectors. I n principle it is possible to use a 44-way cable to connect the TP400’s IDE controller to the TCDEVPLUS PCB, to take advantage of the wider range of connectors on the TCDEVPLUS PCB, while using the faster TP400’s IDE controller. Unfortunately, if you want to do this with the REV B TCDEVPLUS you must cut pin 32 of the ribbon cables. The REV C TCDEVPLUS provides links to do this.)

Section 3.9 has more details on the IDE interface. A Flash File system is also provided with the TP400. Section 6.6 has details of the Flash File System.

When you want to use the TP400's on-boar d floppy and graphics controllers then you may make the appropriate connections to the TP400's connectors and disable the corresponding TP400 device at the TCDEVPLUS jumper areas E3 and E5. To disable the TCDEVPLUS's VGA chip you must also set the E6 jumpers all to the "DIS" position.

When development is complete the TP400 is removed from the TCDEVPLUS Development System. It can then operate stand-alone, or be used with other PC/104 modules.

Refer to the TCDEVPLUS Technical Reference Manual for full details of the TCDEVPLUS.

1.6.3 Using the Rev D TCDEV Development System

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A fan or heatsink should be added to t he TP400, as it may ge t too hot without one. A heatsink is supplied as part of the TP400PAK starter pack (see Appendix D for details).

Enable the floppy disk controller and VGA graphics on the TCDEV. This is done by setting the jumpers at jumper areas E3 and E5 to the " EN" position. Disable the IDE disk controller on the TCDEVPLUS by setting jumper E4 to the “DIS” position. Ensure there are jumpers between positions 1 and 12, and between 4 and 9 at jumper area E1. T he battery back-up jumper should be set in the BATT position at E2. The status LED jumpers at E7 should both be set in the 1 - 2 position. At jumper area E6 set the C000 jumper to the "EN" position and the other seven jumpers to the "DIS" position.

Plug the TP400 onto the T CDEV and connect t he 50-way ribbon cable from J4 of the TP400 to the corresponding connect or on the TCDEV (J3 on the TCDEV). Ensure that pin 1 of the TP400 50-way connector J4 goes to pin 1 of the TCDEV J3 connector. Failure to connect the 50-way cable correctly may damage the equipment.

Connect but do not switch on the TPPSU. (Note that t he TPPSU power connector is polarized. Ensure that the locking tab on the power supply cable mates with the locking tab on the TCDEV connector) . Failure to connect the pow er supply cable

assembly correctly may damage the equipment.

Note that on the TPPSU the mains earth is connect ed to 0V. This is done in the 6way connector, with the braid (earth) connecting to one of the 0V wires. Users who are using the earlier TCPSU power supply must explicitly connect the mains earth to their TCDEV, by plug ging the green and yellow earth lead onto the spade terminal soldered to the printer connector, though note the earlier warning that the 25W TCPSU will probably not have enough capacity for TP400 development.

Connect the keyboard and VGA monitor to the appropriate connectors. Insert a bootable f loppy disk into the TCDEV floppy disk drive and switch the power

supply on. The computer should begin booting. You m ay press the F2 key before or during the memory test to enter t he Setup program, where you can change the time and date and make other changes. T he "EXIT" menu option allows you to save the settings in CMOS RAM and exit.

While using t he TCDEV's floppy disk controller the BIOS will print a warning message to the effect that it is disabling the floppy disk controller on board the TP400.

You should now boot DOS from the floppy disk drive on the TCDEV. An alternative to using floppy disks is to mak e use of the hard disk present on the

TP400 or the TCDEV. You may connect an IDE drive, or Compact Flash card installed in the CF100 adapter , t o the 44-way IDE connector J100 on the T P400. T he BIOS will automatically detect the drive's parameters.

Alternatively, you may use the IDE controller on the TCDEV. This allows you to connect to 2.5” IDE drives (and to 3.5” IDE drives with an appropriate cable). To use the TCDEV IDE controller you must enable it at j umper E4, and use the BIOS Setup program to disable the TP400’s on-board IDE controller.

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Section 3.9 has more details on the IDE interface. A Flash File system is also provided with the TP400. Section 6.6 has details of the Flash File System.

When you want to use the TP400’s on-board floppy and graphics controllers then you may make the appropriate connections to the TP400’s connectors and disable the corresponding TP400 device at t he TCDEV jumper areas E3 and E5. To disable the TCDEV’s VGA chip you must also set the E6 jumpers all to the "DIS" position.

When development is complete the TP400 is removed from the TCDEV Development System. It can then operate stand-alone, or be used with other PC/104 modules.

Refer to the TCDEV Technical Reference Manual for full details of the TCDEV.

1.6.4 TCONN Connector Breakout Board

After developing your product with the TCDEVPLUS you may be interested in using our TCONN board for production.

The TCONN is a breakout board that provides an easy way of connecting to DSP Design’s PC/104 processor boards. It mates with the I/O connectors of the PC/104 board, and provides standard PC compatible connectors for most of the peripherals.

All connectors are filtered, which gr eatly simplifies compliance with EMC standards. Features include:

• PC/104 board plugs directly into the TCONN.

• All connectors filtered for good EMC performance.

• Two 6-pin mini-DIN connectors for keyboard and mouse.

• Keyboard and mouse power rails have thermal fuse protection.

• Three 9-way D-type connectors for serial ports.

• 25-way D-type connector for printer.

• 15-way high density D-type connector for VGA.

• Circular power inlet connector.

• Pin header carrying miscellaneous signals.

• Lithium battery for CMOS SRAM and RTC.

• Small speaker.

• Reset switch.

• Power LED.

See Appendix D for ordering information.

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1.7 AVOIDING COMMON PROBLEMS

This section draws your attention to a number of issues that can cause problems, but that can be avoided if you are aware of them.

The battery pin must not be connected to +5V and must not be left floating. See section 3.6 for further details.

Some old disk drives and some Compact Flash cards do not report t heir parameters and so the parameters will need to be set manually for these devices. See section 3.9 for further details.

Some form of cooling may be needed for the Geode GX1 processor. This is discussed in section 2.1.

The VGA display controller and SoundBlaster-compatible audio circuitry is not fully implemented within the Geode chip. Missing registers are emulated in software, using SMIs (System Management Interrupts). This can cause problems in certain cases, although there is usually a work-around. W hen t he VGA emulation is in operation, in some display modes, a regular SMI occurs every 1ms. During this time the Geode will not respond to interrupts, and if interrupts are arriving at high speed (due to highspeed serial comms f or example) then inter rupts can be lost. There are solut ions for Windows, Linux and some other operating systems, and work-arounds to some extent for DOS. The problem and its resolution are discussed in section 3.10.5.

If you find that a USB peripheral does not operate correctly when directly plugged into the TP400, then you should consider using a powered hub. This is discussed in section 3.14.

158004.B00 13

2 PROCESSOR AND MEMORY

The TP400 single board computer is based around the National Semiconductor

Geode GX1 chip set. There is one SODI MM SDRAM socket. The standard TP400 is supplied without memory, allowing you to choose memory to suit your application. SDRAM options are detailed in Appendix D, Options and Ordering Information.

2.1 PROCESSOR

The TP400 is based on the National Semiconductor Geode GX 1 chip set. This is a highly integrated chip set that includes a Pentium-class MMX-Enhanced x86 compatible processor and many integrated peripherals. It includes all of the motherboard support circuits used in PCs as well as graphics and audio circuitry.

The Geode GX1 is a 320-pin pin-grid ar ray (PGA) chip that is visible on the top side of the TP400. The processor is sock eted, allowing different speed-grade processors to be fitted. The Geode GX 1 is available at a variety of speed grades, up to 300MHz. A 300MHz processor is fitted as standard, although it may be run at slower clock speeds to reduce power consumption. A heatsink or fan can be fitted to the processor, and a connector close to the processor provides power to the fan. Although the Geode GX1 runs much cooler than equivalent Pentium processors, some heatsink or fan is likely to be required in most applications.

DSP Design can supply a passive heatsink, and a heatsink/fan combination. See Appendix D for ordering information.

The Geode GX1 also integrates a high- performance graphics engine. This provides VGA-compatible graphics as well as adding high-performance 2D graphics accelerator logic that is driven by operating system-specific drivers. To provide a high level of system integration, improve performance and reduce system costs, the graphics engine uses a portion of the system SDRAM memory as graphics memory. This is referred to as u n i fie d me mo ry architecture (UMA).

So as to stop the graphics sub-system from using too much of the memory bandwidth, the Geode GX1 implement s graphics compression and caching circuitry. Under this scheme, graphics data is read f rom the graphics memory, compressed, and written back to a separate graphics cache memor y. From then on, and until that line of the display is changed, it is the compressed data t hat is read from the cache and displayed, rather than the full uncompressed graphics data.

The graphics compression and caching scheme, together with the fact that the processor, graphics engine and SDRAM interface are closely coupled, results in a very high level of graphics performance.

As a compromise, not all of the legacy VGA register s are implemented in hardware. Some registers are emulated by an SMI interrupt. National Semiconductor refers to this as VSA - Virt ual System Architecture. T he VSA code is also responsible for the SoundBlaster-compatible audio and some power management features. This software emulation of hardware can give rise to some problem s, which are described in section 3.10.

The companion chip to the Geode GX1 processor is t he CS5530A. This is the BGA

14 158004.B00

(ball grid array) device on the main printed circuit board. The CS5530A contains graphics processing logic, the IDE and USB ports, clock generators, ISA bus interface and the peripheral devices traditionally implemented in a motherboard chip set. (Earlier versions of the TP400 used the CX5530A, which has the same functionality).

These peripherals include two 8237 compatible DMA control units (7 channels), one 8254 compatible timer control unit (3 channels) and two 8259 compatible interrupt control units (15 int errupts). The majorit y of the peripheral f unctions are the same on all PC compatible computers. This includes the tim ers, interrupt controllers and DMA controllers as well as registers such as the NMI and speaker inhibit registers, fast reset and A20 gate registers. Software that accesses desktop PC peripherals will have the same effect when running on the TP400, giving rise to a high degree of PC-compatibility.

The other housekeeping functions provided by the CS5530A are:

• PCI to ISA bus bridge.

• ISA bus memory and I/O address decoding logic.

• Power management.

• Game port (unused on the TP400).

• MPEG playback hardware assist circuitry

The Geode GX1 and CS5530A chips also include a number of internal conf iguration registers. These r egisters ar e unique to the G eode GX1 chip set. They control timing on the expansion bus, shadow RAM, SDRAM configuration, memory mapping and so forth. They ar e initialized by the BIOS and will not normally need to be accessed by the user.

The performance of t he TP400 may be gauged by the processor performance ratings produced by the Norton SI program as shown in Table 1. T his table also g ives typical power consumption figures for the TP400. At the tim e of writing the BIOS does not support operation at 133MHz. The board will run at 333MHz, but the processor is not rated to operate at this speed, so the 333MHz entry is for reference only.

The TP400 off ers very low power consumption for a board of its perform ance. One power measurement has been made with the graphics disabled – as can be seen power consumption is significantly reduced with the graphics disabled. There is a small increase of power as the graphics resolution increases, and a further small increase when the PanelLink interface is used.

CPU FREQUENCY

NORTON RATING

TYPICAL POWER CONSUMPTION

POWER WITH GRAPHICS OFF

133MHz N/A N/A 166MHz 317 670mA 200MHz 387 700mA 233MHz 456 820mA 266MHz 526 870mA 300MHz 595 1.03A 810mA 333MHz 663 1.09A -

TABLE 1 - TP400 PERFORM ANCE RATINGS

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The above measurements were made with a 4-chip 32M-byte SODIMM module

installed. The power consumption figures were tak en after DOS had booted and the processor was sitting idle at the DOS prompt. Power management was disabled.

Users should make their own decision concerning cooling of the processor. The TP400 draws very little power, considering its level of perfor mance, but is still lik ely to need cooling. The TP400 dissipates up to 5W , depending on the clock speed (see Table 1 for overall power consumption) Most of this cur rent goes to the processor, which may get quite hot. We recommend a heat sink and/or a fan to keep the temperature of the processor down. The cooler a chip is t he more reliable it will be. A fan or fan and heatsink combinat ion can be fitted to the processor, or a fan could be provided in the enclosure along with the PC/104 boards. Connector J102 is provided to power a +5V fan. DSP Design can provide both a passive heatsink and a fan/heatsink combination.

As an alternative the enclosur e could be desig ned so that part of the enclosur e acted as the heat sink. Thermal materials are available to provide a good thermal bond between the CPU and the case.

2.2 CLOCK

A number of clock frequencies are used on the TP400. Most of these are derived from a 14.318MHz crystal and a synthesiser chip that generates other required frequencies.

Several 33MHz clocks are generated. These are fed to the PCI bus and to the Geode GX1 and CS5530A chip.

The Geode GX1 incorporates its own clock multiplier that generates the processor clock. A number of processor clock frequencies can be selected by solder links on the board, which are set as described in Appendix B. The TP400 is fitted with a Geode GX1 processor with a clock frequency 300MHz.

The clock synthesiser logic also generates the following clock frequencies:

• 14.318MHz for the PC/104 OSC signal.

• 8MHz for the PC/104 BUSCLOCK signal.

• 24MHz for the Super I/O chip (where it is used for serial ports, keyboard controller

and floppy disk controller).

• 48MHz for the USB ports.

• 24.5MHz for the AC97 audio codec.

• 1.8MHz for the COM3 and COM4 UARTs.

The Geode GX1 and CS5530A generate clocks for the SDRAM (synchronous SDRAM) and graphics sub-systems.

The real-time clock, or calendar/clock, in the Super I/O chip uses a separate

32.768kHz crystal to maintain the time and date. The Ethernet chip has its own

25MHz crystal.

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2.3 SDRAM

The main memory of the TP400 consist s of Synchronous Dynamic RAM (SDRAM) chips. The chips are mounted on a small 144-pin printed circuit board called a SODIMM module (small outline dual-in-line memory module). T he memory is 64-bits wide. Four options are available:

• 32M bytes

• 64M bytes

• 128M bytes

• 256M bytes

The standard configuration of the TP400 is to have no SDRAM fitted. SODIMM modules must be ordered separately and fitted into the SODIMM socket on the TP400. Thus users can select the correct memor y capacity for their application. See Appendix D: TP400 Options and Ordering Information.

The use of SODIMM modules for SDRAM memory means that the SDRAM configuration can be alter ed at a later stag e. DSP Desig n car ry stock of the SO DIMM modules described above, or customers may provide their own. PC100 SODIMM modules should be used.

Care must be tak en when handling the TP400 and associated components. Ensure that all anti-static handling precautions are taken. See Appendix B: TP400 Setup Procedure for instructions on installing SODIMM modules.

The BIOS automatically deter mines the amount of SDRAM present and configures the internal Geode GX1 registers accor dingly. Registers within the Geode GX1 chip allow SDRAM timing to be optimised according to CPU speed and SDRAM access time. At reset the SDRAM timing defaults to the slowest case and the BIOS then optimizes timing for the best performance.

Some of the SDRAM is taken from the processor and allocated to the graphics controller, using a technique ref err ed to as UMA (unified mem ory architectur e). Up to

4.5M bytes may be allocated to graphics; the BIOS configures the correct amount depending on the graphics mode selected in the BIOS Setup menu.

Note that only the f irst 640k bytes of SDRAM are usually directly accessible by DOS. Some of the remaining SDRAM is used to shadow the BIOS (see section 6.1) and the remainder is re-mapped above the 1M byte boundary, where it can be used by DOS extenders and by Windows and other operating systems.

Memory between C0000H and FFFFFH (the top of the 1M-byte block) can be used to shadow BIOS code. This allows the BIOSes to run at t he fast SDRAM speed rather than the slow EPROM speed. Typically the system BIOS (from E8000H - FFFFFH), the VGA BIOS (from C0000H - C7FFFH) and the Flash File System (from CC000H CFFFFH) driver are shadowed. Memory beyond the 1M byte limit is available for Windows and other protected mode operating systems.

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2.4 FLASH MEMORY

By default the TP400 is fitted with one 2M-byte AMD or Fujitsu 29F016 Flash memory chip. However, the TP400 has sites for two flash chips, and the 4M byte 29F032 can be fitted as an alternat ive to the 29F016. Thus there are options f or 4M or 8M bytes of Flash memory as well as the standard 2M-byte complement. The 4M and 8M byte options are available by special order and are subject to a minimum order quantity.

Flash memory is non-volatile memory that can be program med while it is soldered to the TP400. Data written to the Flash memory is retained after power is removed.

The Flash memory serves two purposes. Firstly, it contains the BIOS: machine-dependent software that is required to run an operating system.

The second function of the Flash memory is to provide a Flash File System f or users who want a solid state disk.

The top 256k bytes of the Flash chip ar e used for the system BIOS and any BIOS extensions, such as the VGA BIOS extension and the Flash File System BIOS extension. The TP400 comes pre-programmed with a system BIOS, a VGA BIOS extension for on-chip graphics controller and a Flash File System BIOS extension. See section 2.5 for mor e informat ion on memory mapping of the TP400, and section

6.3 for more information on BIOS extensions.

Utility programs are provided on the TP400 Ut ility Disks that allow the Flash chip to be programmed by the user. This allows the user to program various alternative BIOS image files into the Flash memory. These utility programs are described in section

6.5.

A Flash File System is provided with every TP400. This converts the remaining 1744k bytes of the 2M byte Flash chip into a non-volatile read-write logical disk dr ive. This Flash disk can contain the MS-DOS operating system as well as your application program. The Flash File System is described in section 6.6.

Optionally, 4M byte and 8M byte Flash disks are available. The TP400 allows the Flash File System to access the large Flash chips through a

window in the 1M byte address space. Memory management logic in the Geode GX1 and hardware in the Super I/O chip allows the high order address lines of the Flash chip to be changed by software. The Flash File System driver software controls the memory management logic and bank switch hardware transparently to the user’s software.

The Flash File System is intended for ROM-DOS and MS-DOS. In principle Flash file systems could be created for other operating systems, such as Linux, QNX, OS/9 and VxWorks, but at the tim e of writing this work has not been done and DSP Design cannot provide FFS drivers for these operating systems. This situation may change in the future, so contact us if you have an interest in these operating systems.

The Flash chip resides on the eight-bit PC/104 data bus. The BIOS makes use of "shadow RAM" in place of t he Flash chip for gr eater speed.

In this scheme the BIOS contained within the Flash chip is copied by the BIOS to SDRAM at the same addresses. The Flash chip is then disabled and the BIOS is

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executed from the 32-bit wide SDRAM, much faster than it would be from the Flash chip. Section 6.3 contains further information on BIOS extensions.

2.5 MEMORY ADDRESS MAP

Table 2 shows the memory map as configured by the standard BIO S of the TP400. This table shows the bottom 1M byte address space. Extra SDRAM is located immediately above the 1M byte boundary. Memory accesses beyond the top of the SDRAM are performed on the PCI bus.

ADDRESS MEMORY DEVICE DECODED MEMORY SIZE

FFFFF E8000

BIOS in Flash Chip - copied to shadow SDRAM memory during the boot sequence. 96K

E7FFF E0000

This space is reserved for the Flash memory programming program and the Flash File System.

32K DFFFF D0000

Available for PC/104 memory mapped boards. BIOS Extension code can be located here and optionally shadowed in SDRAM.

64K CFFFF

CC000

The Flash File System BIOS extension is initially located here, before it copies itself to low memory. Available for PC/104 bus memory mapped boards if the FFS is not used.

16K

CBFFF C8000

Available for PC/104 memory mapped boards. BIOS Extension code can be located here and optionally shadowed in SDRAM.

16K C7FFF

C0000

Usually VGA BIOS, which is copied from Flash chip to shadow SDRAM at this address. Alternatively used by VGA BIOS on PC/104 or PC/104-Plus bus that can also be shadowed.

32K

BFFFF A0000

Usually allocated to VGA memory.

128K 9FFFF 00000

SDRAM

640K

TABLE 2 - TP400 A DDRESS MAP - FIRST 1M BYTE

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3 PERIPHERALS

This section describes the I/O address map and the on-board peripherals.

3.1 I/O ADDRESS MAP

The TP400 features a number of on-board I/O mapped resources, and supports access to the PC/104 bus I/O space as well.

All I/O mapped functions that are present on deskt op PCs are present at the same I/O addresses on the TP400. The TP400 is therefore compatible at the machine code or register level with desktop PCs.

On-board I/O devices include registers within the Geode GX1 chip set, the Super I/O chip, Ethernet chip and the extra UART chip. The Super I/O chip contains the floppy disk controller, Utility Register, keyboard controller, calendar/clock module and the serial and parallel I/O ports. The on-board I/O addresses are listed in Table 3.

I/O accesses are routed as follows. I/O accesses within the Geode GX1 processor remain internal to this chip. I/O addresses that are within PCI bus devices (which includes the registers internal to the CS5530A chip) are performed on t he PCI bus. Those I/O accesses that are not claimed by PCI bus peripherals are translated into ISA bus accesses (by the CS5530A PCI bridge) and performed on the ISA bus.

Thus those addresses that are not on-board the TP400 are available for peripheral devices on either the PC/104-Plus bus (PCI bus peripherals) or on the PC/ 104 bus (ISA bus peripherals). The PCI bus peripher als get the first option to respond to an access; only if there is no PCI response will the accesses be routed to the ISA bus peripherals.

I/O addressing of PC/104 bus boards is reasonably straightforward: if an I/O address is not used by on-board resources then it can be allocated to a PC/104 board. Putting this another way, the addresses of PC/104 bus boards should be chosen to avoid the on-board I/O resources.

Note that, in common with many ISA bus I/O boards, address decoding logic on PC/104 boards often decodes only address lines A0 - A9, which can result in “aliasing” - whereby a PC/104 board can respond to more than one address. For example, a PC/104 bus board set for I/O address 200h may also respond at I/O addresses 600h, A00h, E00h and so on.

I/O addressing of PC/104-Plus (PCI bus) peripherals is to a large extent programmable, via each per ipheral's PCI Conf ig uration r egist ers. T hese re gister s are programmed by the BIOS f ollowing reset, in a process that should normally ensure that no conflicts occur. PCI I/O addressing uses all 32 bits of the PCI address space, so aliasing cannot occur.

20 158004.B00

ADDRESS I/O FUNCTION

00 - 0F DMA Controller in Geode GX1 20 - 21 Interrupt controller in Geode GX1

22 - 23 Geode GX1 Processor Configuration Registers 2E - 2F Super I/O Chip Configuration Registers 40 - 43 Timer Unit in Geode GX1 60 and 64 Keyboard controller in Super I/O chip. 61 Port B Control/Status Port in Geode GX1 70 - 71 Real-Time Clock in Super I/O chip and NMI enable in Geode GX1.

80 - 8F DMA Page Registers in Geode GX1 92 Port A System Control Port in Geode GX1 A0 - A1 Interrupt Control/Status Reg. in Geode GX1 C0 - DE (Even

addresses only)

DMA Controller in Geode GX1

E0 - E7 Utility Register in Super I/O Chip F0 - F1 Coprocessor Error Registers in Geode GX1 102 Enable Register in 65550 1F0 - 1F7 IDE disk controller 200 - 201 Reserved for Game Port

220 - 22F, or 240 - 24F, or 260 - 26F, or 280 - 28F

Sound card compatibility registers, if enabled. One of these addresses is selected.

2E8 - 2EF COM4: in extra UART chip. 2F8 - 2FF COM2: Serial Port in Super I/O chip. 330 - 38B Sound card FM registers. 378 - 37A Parallel Port in Super I/O chip. 3B4 - 3B5 VGA Register in Geode GX1 (monochrome modes). 3BA VGA Register in Geode GX1 (monochrome modes). 3C0 - 3CF VGA registers in Geode GX1. 3D4 - 3D5 VGA Register in Geode GX1 (colour modes). 3DA VGA Register in Geode GX1 (colour modes). 3E8 - 3EF COM3: Serial Port in extra UART chip. 3F0 - 3F7 Floppy Disk Controller 3F8 - 3FF COM1: Serial Port in Super I/O chip. 481 - 48B DMA high page registers. 4D0 - 4D1 IRQ edge/level select registers. CF8 - CFF PCI Configuration Registers 121C - 121F ACPI Timer Count Register in Geode GX1 AC00 - AC8F ACPI Registers F800 – F8FF Typical address range for DP83815 Ethernet chip

TABLE 3 - ON-BOA RD I/O DEVICES

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3.2 SUPER I/O CHIP

Many of the peripheral functions are implemented in a single chip, the "Super I/O" chip. This is the PC97317 f rom national Semiconductor. The following f unctions are included in the PC97317:

• Two serial ports (operating as COM2 and COM3).

• A printer port.

• A keyboard controller (providing a PS/2 mouse as well as the keyboard)

• A floppy disk controller.

• A real time clock with CMOS SRAM.

• Several general-purpose I/O bits, used on the TP400 as the "Utility Register".

Each of these functions (except the general purpose I/O) have their own I/O addresses, allocated at the same locations as in every PC. In addition, the PC97317 has its own set of configuration reg isters, which can be used by the BIOS to enable or disable each function, assign I/O addresses, place the functions in low power modes etc.

3.3 EXTRA UART

The Super I/O chip contains two serial ports; two further serial ports are provided by an additional dual UART chip. This chip provides the COM3 and COM4 serial ports. The chip selects for these two ports are in turn generated by two of the programmable chip select registers within the Super I/O chip.

Further details of all four serial ports are given in section 3.4.

3.4 SERIAL PORTS

The TP400 features f our serial por ts that are accessed as CO M1, COM2, COM3 and COM4. The first three are RS-232 ports. COM4 provides TTL level transmit and receive data signals only. Addit ionally the COM2 port can be configured for RS-485 operation.

3.4.1 Signals, Addressing and Interrupts

The serial ports are hardware and software compatible with the serial port s used on PCs, and all PC communications software packages should work with the serial ports. The UARTs are 16C550 compatible and t hus provide a 16 byte transmit and receive FIFOs.

The COM1 and COM2 UARTs are contained within the PC97317 Super I/O chip. The COM3 and COM4 UARTs are contained within an additional dual UART chip.

Connection is made to the COM1 and COM2 serial ports via the 50-way J4 connector. If you are using a TCDEVPLUS t hese serial ports are available through the standard 9 pin D-Type connectors at J4 (COM1) and J5 (COM2). These connectors are pin compatible with all PC computers.

22 158004.B00

Connection is made to the COM3 and COM4 serial ports via the 14-way J5 connector.

The pin assignments of the f irst thr ee serial ports are such that they easily connect to 9-pin D-type connectors.

The first t hree serial ports provide the full complement of RS-232 signals. Transmit Data, Request To Send ( RTS) and Data T erminal Ready (DTR) ar e outputs f rom the TP400. Receive Data, Data Carr ier Detect (DCD), Data Set Ready (DSR), Clear to Send (CTS) and Ring Indicator (RI) are inputs to the TP400. COM4 provides only Transmit Data and Receive Data, and as TTL-level signals. The control inputs of COM4 are all connected so as to appear permanently asserted.

Following a reset of the TP400 t he serial ports are initialized as 2400 baud, one st op bit, eight data bits and no parity. These par ameters can be changed by the MS-DOS MODE command.

COM1 serial port uses interrupt level IRQ4 to interrupt the processor. The COM2 serial port uses interrupt level IRQ3. COM3 and COM4 use interrupt levels IRQ5 and IRQ9 respectively. Note that in som e PC systems with four serial port s COM3 shares an interrupt with COM1 and COM4 shares an interrupt with COM2. The TP400 design allows each serial port to have its own interrupt. (See section 4.5 for information on re-allocating interrupts).

It should be noted t hat the BIOS does not m ake use of serial por t interrupts, but that most comms software packages enable the interrupts and make use of them to increase the speed of serial data transfer.

3.4.2 RS-485 Operation

As an option COM2 can be re-configured as an RS-485 serial port . This is done with a solder link on the board - see Appendix B for configuration details.

The COM2 RS-485 port configuration provides either half-duplex or full duplex interfaces. In full duplex mode one t wisted pair is used for transmission and another twisted pair is used f or reception. Full duplex mode would normally be used in pointto-point communication between two computers.

In half duplex mode the transmit and receive twisted pairs are connect ed together at the TP400. In t his mode several boards can be connected to the single twisted pair, with no more than one board driving the cable at once. A suitable protocol needs t o be agreed by all nodes on the twisted pair to ensure that only one computer transmits at any one time.

On the TP400 the RS-485 driver is controlled by the RT S bit of the on-board UART. When RTS is of f (inactive) the RS-485 transceiver chip does not drive the transmit twisted pair cable. This is the default state after a TP400 reset. W hen RTS is set active the RS-485 transceiver does drive the transmit twisted pair cable and the TP400 can transmit. Note that the r eceiver part of the tr ansceiver is always enabled. Thus in half duplex mode COM2 will receive the characters that it transmits itself.

158004.B00 23

In RS-485 mode the DTR control output has no eff ect, and the CTS, DCD, DSR and RI status inputs are undefined (they can be in either state, and software must not assume any particular values of these signals).

No RS-485 termination resistors are provided on the TP400. These must be provided externally if required.

When operat ing as an RS-485 port the COM2 RS-232 signals on connector J4 are re-assigned. Appendix E provides information on RS-485 pin assignments.

3.4.3 Disabling Serial Ports

The COM1, COM2, COM3 and COM4 serial ports can be individually disabled by the BIOS Setup program (use the Advanced / I/O Device Configuration menu). See section 6.2 for details of the Setup program.

3.4.4 Extended Modes

The serial ports within the PC97317 Super I/O chip may be programmed to operate in "extended mode". This allows for operation at up to 1.5M baud, using DMA to transfer data and provides more sophisticated interrupt handling.

The BIOS does not support this extended mode, but users who need these features may reprogram the PC97317 registers to suit their needs.

3.4.5 Infra-Red Operation Modes

(At the time of writing the T P400 BIOS does not support t he IrDA mode of the Super I/O chip. The rest of this section describes how the IrDA would operate if and when the BIOS implements IrDA. Contact DSP Design if you have an IrDA application.)

The COM2 serial port can also be configured to operate in one of three infrared modes, transmitting and r eceiving data as infrar ed light pulses. The t hree modes are IrDA, Sharp-IR and Consumer-IR. At present the BIOS only configures the COM2 UART for some of the modes, but users who need the other modes may repr ogram the PC97317 registers to suit their needs.

The IrDA standard defines a number of protocols. The TP400 supports the SIR format, with speeds of up to 115k baud. T he IrDA transmit and receive data signals (IRTX and IRRX) are available on the 50-way I/O connector J4 pins 2 and 1 respectively, from where they can be connected to an IrDA infra-red transceiver module. The TCDEVPLUS (but not the TCDEV) incorporates a suitable IrDA transceiver.

To configure the COM2 serial port as an IrDA port you must use the Advanced / I/O Device Configuration menu within the BIOS Setup program (see section 6.2 for details of the Setup program). This sets a bit in an internal Super I/O configuration register, so that COM2 data is routed thr ough the IRTX and I RRX pins on the Super I/O chip, rather than the pins that connect to the RS-232 transceiver chip. The COM2 handshake lines, however are still routed through the RS-232 transceiver chip and behave as in normal RS-232 operation.

24 158004.B00

The polarity of the incom ing signal on the IRRX pin is of opposit e polarity to that on the IRTX pin. The IRTX pin is normally low, and will emit a series of narr ow positive going pulses as a character is transmitted. These positive pulses are designed to switch on the LED of the IrDA transmitter. For proper operation the IRRX receiver must deliver to the Super I/O chip a signal that is normally high, but which pulses low on receipt of a pulse of light from an IrDA transmitter. Depending on the nature of your IrDA transceiver, t his requirement may involve adding a logic inverter between the IrDA transceiver and the IRRX pin on the TP400.

An IrDA optical transceiver is present on the top edge of the TCDEVPLUS. See t he TCDEVPLUS Technical Reference Manual for details of how to enable this.

The TCDEV Development system has no IrDA optical t ransceiver. However, the I rDA pins are accessible on the TCDEV at jumper ar ea E1 - the transmit sig nal on E1 pin 10 and the receive signal on E1 pin 7. By setting E1 jum pers to 7 - 8 and 9 - 10, and removing other jumpers, the IrDA signals as well as power are available on the mouse connector J8.

The Sharp-IR mode is fixed at 38.4k baud. The Consumer-IR mode supports all the pr otocols currently used in remote-controlled

home entertainment equipment: RC-5, RC-6, RECS80, NEC and RCA. For further information on the IrDA standards, see this web site: www.irda.org

3.5 PRINTER PORT

The TP400 implements a full-f unction Centronics compatible pr inter port. This port is the MS-DOS PRN device. The printer port is contained within the PC97317 Super I/O chip.

The printer port feat ures an 8-bit data por t and t he f ull compliment of contr ol sig nals four output signals and five input signals.

The 8-bit data port is normally used as an output por t for driving a printer. Provided that the printer port is set up f or bi-dir ectional operation ( which it is by default), then it can also be used as an input port. The default setting (after reset) is output. To configure the pr inter as an input bit 5 of the printer port Control Reg ister must be set to 1. To re-config ure as an output set bit 5 to 0. The Control Register is a read/write register located at address 37AH.

The printer port signals are brought out on the 50-way J4 I/O connector on the TP400. On the TCDEVPLUS the parallel port is accessed via a PC compatible 25 way female D-type connector.

If enabled by sof tware, the parallel port is able to use inter rupt IRQ7 to interrupt the processor. Users should note that the BIOS does not make use of interrupts for accessing the printer port, but other software drivers may do so. See section 4.5 for a discussion of interrupt allocation on the TP400.

158004.B00 25

The printer port can optionally be configured as an output-only port, an Enhanced Parallel Port (EPP) and as an Extended Capabilities Printer Por t (ECP). In EPP mode greater throughput is provided by automatically generating strobe signals. In ECP mode a 16-byte FIFO is provided. Users must provide their own software for these modes. The parallel port mode can be set with the BIOS Setup program (use the Advanced / I/O Device Configuration). The port can also be disabled using this Setup program. See section 6.2 for details of the Setup program.

The I/O signals on the printer port can be treated as general purpose digital input and output signals, and as such can be used for other applicat ions, such as driving an alphanumeric LCD display, or inputting from switches, for example.

The printer port control output signals (/STROBE, /AUTOFD, /INIT and / SLCTIN) are open drain with 4k7 pull-up resistors fitted. The printer port status inputs (BUSY, PE, SLCT, /ACK and /ERRO R) have pull-up and pull-down resistors present, inside the super I/O chip. There are pull-up resistors on /ACK and /ERROR, and pull-down resistors on the other three signals. T he printer port data lines (PD0-7) are driven to TTL levels when outputs. When inputs they do not have pull-up resistors fitted.

3.6 REAL TIME CLOCK

Calendar/Clock facilities are provided in PC comput ers. T he calendar/ clock module is often known as the Real Time Clock, or RTC. These RTC f unctions emulate those found in the Motorola MC146818 chip, and include time of day functions, calendar functions and CMOS RAM for storing setup parameters. An alarm facility is also provided; this allows an interrupt to be generated when a particular time is reached. Calendar/clock functions are implemented within the PC97317 Super I/O chip.

The calendar/clock hardware is read by the BIOS, which maintains time and date on behalf of the operating system. The BIOS does this in a millennium-compliant fashion.

The calendar/clock logic may be accessed throug h the MS-DOS calls (interrupt 1AH) or with MS-DOS TIME and DATE commands. As well as the calendar clock functions there are 242 bytes of static RAM (usually called “CMOS SRAM”) that are backed up by the battery. Some of this is used to store conf iguration parameters used by the BIOS. The serial EEPROM can be used to store these parameters in systems that have no battery - see section 6.7 for details.

The 242 bytes of SRAM are divided between 114 bytes that are normally accessible through the RTC index and data registers at I/O addresses 70h and 71h, and 128 further bytes that are accessible in a less direct m anner. Users who want to make use of the further 128 bytes should understand how to do this by reading the PC97317 data sheet. These 128 bytes are not used by the BIOS.

A battery can be used to provide power to maintain the clock and CMOS RAM when the main +5V power supply is not present. This external battery should be connected between the BATT input and GND of J4. The battery voltage should be between 3.0V and 3.6V and can be either be a rechargeable battery (e.g. NiMH) or a nonrechargeable battery (e.g. Lithium).

Do not connect a 5V supply to the battery pin. This will prevent the TP400 from booting. Leaving the battery pin floating may also prevent booting. If no battery

26 158004.B00

is present then the battery pin on the J3 connect or must be connected t o GND, to prevent it floating. The battery pin is called BATT and is pin 28. A ground pin exists on the adjacent pin, pin 27.

The calendar/clock circuitry draws approximately 2uA from the battery when the TP400 is powered down and draws no current when operating normally (i.e. powered up).

The TCDEVPLUS has a 3.6V NiMH rechargeable battery installed. This connects to the BATT input via an enable/disable jumper, as described in the TCDEVPLUS manual. The TCDEVPLUS NiMH battery should be sufficient f or the clock to operate for several months in the absence of the +5V power supply. The jumper E2 is provided on the TCDEVPLUS that can be used to disconnect the batter y in order to extend the battery life or to deliberately corrupt the contents of the CMOS SRAM. The battery should be disconnected while the TP400/TCDEVPLUS is in storage.

Figure 2 gives a suitable circuit for a rechargeable battery back-up circuit.

NOTE: This circuit is suitable only when using a NiMH or Nicad battery of the type used on the TCDEVPLUS. T he circuit shown in Figure 2 is not suitable for Lithium or other non-rechargeable battery types. The diode and t he resist or must be omit ted if a lithium battery is used.

FIGURE 2 - RECOMMENDED BATTERY BACK-UP CIRCUIT

3.7 KEYBOARD AND MOUSE

The TP400 uses an AT or PS/2 type keyboard. Your supplier can provide a suitable keyboard. Alternatively, USB keyboards can be used - see section 3.14 for details of the USB ports.

In many applications the familiar desktop keyboard is inappropriate. A variety of industrial keyboards and keypads are available - contact DSP Design f or details. The TP400 will work without a keyboard if required.

Users should avoid plugging in the keyboard or mouse when the TP400 is powered on.

VCC

BATT

NiMH

3.6V

10K Ohm

158004.B00 27

The keyboard controller circuitry on the TP400 is contained within the Super I/O chip, and also includes a PS/2 style mouse port. The keyboard uses the IRQ1 int errupt line and the mouse uses IRQ12. Connections to the keyboard and mouse are made through the 50-way J4 connect or. On t he TCDEVPLUS these are r outed to two PS/2 style connectors (6-pin mini-DIN connectors). On the TCDEV the keyboard connector is a 5-pin DIN connector and the mouse connector is a 6-pin mini-DIN connector.

3.8 FLOPPY DISK DRIVE

The TP400 includes an on-board floppy disk controller. The floppy disk controller electronics are included within the Super I/O chip.

Due to a limitation on PCB space the floppy disk controller is accessed through a 26way flat flexible cable connector, J105, rather than the more common 34-way IDC connector. The 26-way connector is used on f loppy disk drives used in laptop PCs. The cable carries power as well as control and data signals. The laptop floppy drives tend to be much sm aller than the drives used in desktop PCs. The signals used on the flat flexible cable are the same as used on the 34-way connector, so if necessary the more common floppy drives could be driven.

DSP Design is able to supply suitable floppy disk drives and the 26-way cable. We are also able to supply an adapter boar d called the DIS35-26 that allows the 26-way cable to connect to drives with the usual 34-way connector.

The TCDEVPLUS development system incorporates a complete floppy system, including a floppy diskette drive and cable. The T CDEVPLUS also provides an IDE disk controller. Connection to the TP400 is via the PC/104 bus.

Users will probably prefer to use the TCDEVPLUS f loppy controller while using the TCDEVPLUS. To do this the TCDEVPLUS f loppy disk controller must be enabled at jumper area E5. The TP400’s on-board floppy disk controller may be optionally disabled, using the Setup program (Advanced / I/O Device Configuration menu). If it is not disabled the TCDEVPLUS’s floppy drive will be used anyway, and you will receive a warning message on the screen.

The floppy disk circuit uses an interrupt (IRQ6) and a DMA channel (DREQ2 and /DACK2). These can be re-assigned to other uses if the floppy disk controller is not used.

3.9 IDE DISK DRIVE

The TP400 includes an on-board IDE disk controller. The IDE disk controller electronics is included partly within the CS5530A chip and partly within the disk drive itself.

The IDE port can connect to hard disks, CD- ROM drives and Compact Flash cards, which behave like small hard disk drives.

The IDE port is capable of high speed data transfer modes, referred to as PIO modes 0 - 4. Normally the BIOS will interr ogat e the dr ives attached to t he T P400 and set the highest possible transfer speed.

28 158004.B00

In addition, the "Ultra DMA/33", or "UDMA" Mode allows even higher data transfers by transferring two words on every data transfer cycle, and using DMA. UDMA however requires an operating-system specific device driver. Suit able device drivers are available for the Windows 95/98 and Windows NT operating systems and are included on the TP400 Utility Disks.

IDE disk drives can be connected through the 44-pin 2mm-pitch connector, J100. One or two drives can be connected on this cable - one configured as a master and the other as a slave. Any combination of hard disks, CD-ROM drives and Compact Flash cards can be connected.

The CF100 solid-state IDE disk drive is a small print ed circuit board that contains a connector for a Compact Flash memory module. The removable Compact Flash modules are available in a wide range of sizes from 4M bytes to 128M bytes and beyond. IBM sell a mechanical drive in Compact Flash format with a 1G byte capacity. The CF100 PCB can be fixed to the TP400, m ating directly on the J100 IDE connector. Alternatively it can be connected to J100 through a length of ribbon cable, and thus mounted elsewhere on the TP400 or elsewhere within the TP400’s enclosure.

The Compact Flash cards can be removed from the CF100 and data transf erred to other PC computers. DSP Design sell Compact Flash cards and also a Compact Flash card reader that plugs into the printer port of any PC. W e have found that not all Compact Flash cards will operate with the TP400 – we think this is more a fault of the Compact Flash cards than the IDE code in the BIO S. Users who are considering buying their own Compact Flash cards should take care, or contact DSP Design for advice.

Appendix G contains details of the CF100. The TP400 BIOS automatically identifies the drives connected to the TP400 at

power-on. It ascertains drive parameters (numbers of heads, cylinders etc, as well as allowable transfer speeds) that are then used by the BIOS as it accesses the drives. These parameters can be over-ridden if required, using the BIOS Setup program. Use the Main / Primary Master and Main / Primary Slave menu entries.

Some old disk drives and some Compact Flash cards do not report their parameters and so the parameters will need to be set manually for these devices. For Compact Flash cards and IDE drives that do not seem to be working

properly when you use the Auto Detect option, do the following. In the Main / Primary Master menu set the "type" to "User". Then set the Multi-sector Transfer to Disabled, the LBA to Disabled, 32-Bit I/O to Disabled and Transfer Mode to Standard. These settings may be unnecessarily conservative for some Compact Flash cards, but others do not work in the faster modes. If necessary set the ot her disk parameters (number of heads, cylinders and sectors per track) to the actual number of the drive.

A 2.5 inch to 3.5 inch IDE drive converter cable is available that allows 3.5 inch hard disk drives to be connected to the TP400 (a separate power source is required for the

3.5 inch drive in this configuration). The converter cable is called the IDE3020. The TCDEVPLUS development system also incorporates an I DE disk controller, as

well as a floppy disk controller and drive. Connection to the TP400 is via the PC/104 bus. The IDE disk controller on the TCDEVPLUS (but not on the T CDEV) presents more options for connecting to dr ives. It has two 44-way 2mm connectors to connect to 2.5” IDE drives, a 40-way 0.1” connector to connect to 3.5” IDE drives and CD-

158004.B00 29

ROM drives, and a Compact Flash socket to allow the use of Compact Flash card s in place of mechanical hard disk drives.

Users will probably prefer to use the TP400’s IDE controller rather than the TCDEVPLUS’s IDE controllers while using the T CDEVPLUS, since it is faster than the TCDEVPLUS IDE controller . However, the TCDEVPLUS IDE controller may be used. To do this the TCDEVPLUS IDE controller must be enabled at jumper area E4. In addition, the IDE disk controllers on t he TP400 must be disabled. T his is achieved using the Setup program (Advanced / I/O Device Configuration menu entries).

3.10 DISPLAY CONTROLLER

The TP400 provides a powerful graphics controller system. This display controller logic is able to support CRT displays and active-matrix TFT colour LCDs. A PanelLink driver is provided. Some EL and plasma panels may also work with the TP400. The CRT and flat panel can operate simultaneously. CRT resolution is up to 1280 x 1024 and TFT resolution is up to 1024 x 768.

3.10.1 Overview

The graphics controller logic is one of the most interesting aspect s of the Geode GX1 architecture. The logic is implemented in the Geode GX1 processor chip and the CS5530A companion chip.

Some of the SDRAM is taken from the processor and allocated to the graphics controller, using a technique ref err ed to as UMA (unified mem ory architectur e). Up to

4.5M bytes may be allocated to graphics. The BIOS allows an appropriate amount to be reserved for graphics, in the Advanced / Advanced Chipset Control / Video Resolution menu. The memory taken by each BIOS opt ion is given in Table 4. This memory is used for the display frame buf fer, for the Geode’s unique display buffer compression cache, for SMI processing and for video (MPEG and AVI) processing. Unfortunately theref ore, there is no direct correlation between the SDRAM allocated and the display resolution and colour depth – this will be dependent on how each display driver has been implemented. You may have to experiment with different settings to get an optimum t rade off between memory used and display resolution. Table 4 shows guidelines which are adequate f or Windows 95. (Note that t here are some anomalies here, which must be attributed to problems with the display driver).

BIOS SETTING SDRAM ALLOCATED TYPICAL DISPLAY RESOLUTION

LOW 1.5M bytes 1024 x 768 x 256 colours MEDIUM 1.5M bytes 1024 x 768 x 256 colours

800x 600 x 65536 colours

HIGH 2.5M bytes 1024 x 768 x 65536 colours

1280 x 768 x 256 colours

SUPER 4.5M bytes 1024 x 768 x 65536 colours

1280 x 768 x 256 colours

TABLE 4 - SDRA M ALLOCATED TO DISPLA Y CONTROLLER

In order to display an image on the screen, video data is read out of the graphics area within the SRAM memory by the Geode GX1 processor, and sent to the

30 158004.B00

CS5530A for formatting and dispatch to the CRT or flat panel. The CS5530A contains the RAMDAC for t he analog CRT displays. In or der to minimise the am ount of memory bandwidth taken up by the refreshing of the displays, the Geode GX1 incorporates data compression circuitry. Thus in normal operation only the compressed representation of the graphics image needs to be read from the SDRAM.

As well as offering VGA com patible log ic f or cr eation of im ages, the G eode GX 1 also incorporates a high-performance BITBLT graphics engine, driven by operating system-specific drivers. This 2D graphics accelerator results in very high speed updating of the display. Support for video playback is also provided – see section

3.11.

3.10.2 Using CRTs and TFT LCDs

The display controller drives CRTs, and can drive TFT LCD panels as well. Simultaneous operation is possible.

By default the TP400 is configur ed for CRT operation only. Users can use the BIO S Setup program to optionally enable TFT operation as well. This also allows the display size to be set at 640 x 480, 800 x 600 or 1024 x 768. Use the Advanced / Advanced Chipset Control / Geode GX1 LCD menu item. There are two clock frequency options for the 1024 x 768 display. Choose the option that gives you the most stable picture.

Connection to a CRT from the TP400 is made via the 16-way connector J6. Connection to flat panel displays is made through the 40-way 0.05” pitch connector J8. Connection is made from the J8 connector to flat panels using a ribbon cable.

Possible display resolutions for TFT displays are given in Table 5. Possible resolutions for CRT displays are given in Table 6. Simultaneous CRT and flat panel display is supported for resolut ions of 640 x 480, 800 x 600 and 1024 x 768. (Some of the higher colour depths and display sizes require t he display resolution to be set to “Super” in the BIOS Setup program).

RESOLUTION SIMULTANEOUS

COLOURS

REFRESH RATE

DOTCLK RATE

8 BPP. 256 colours out of a palette of 256.

60Hz 25.175MHz 640 X 480

16 BPP. 64k colours 5-6-5. 60Hz 25.175MHz 8 BPP. 256 colours out of a palette of 256.

60Hz 40.0MHz 800 x 600

16 BPP. 64k colours 5-6-5. 60Hz 40.0MHz 8 BPP. 256 colours out of a palette of 256.

50Hz or 60Hz 54MHz or 65MHz 1024 x 768

16 BPP. 64k colours 5-6-5. 50Hz or 60Hz 54MHz or 65MHz

TABLE 5 - TFT PA NEL DISPLAY RESOLUTIONS

158004.B00 31

RESOLUTION SIMULTANEOUS

COLOURS

REFRESH RATE

DOTCLK RATE

72Hz 31.5MHz

8 BPP. 256 colours out of a palette of 256.

75Hz 31.5MHz 60Hz 25.175MHz 72Hz 31.5MHz

640 X 480

16 BPP. 64k colours 5-6-5.

75Hz 31.5MHz 60Hz 40.0MHz 72Hz 50.0MHz

8 BPP. 256 colours out of a palette of 256.

75Hz 49.5MHz 60Hz 40.0MHz 72Hz 50.0MHz

800 x 600

16 BPP. 64k colours 5-6-5.

75Hz 49.5MHz 60Hz 65MHz 72Hz 75.0MHz

8 BPP. 256 colours out of a palette of 256.

75Hz 78.5MHz 60Hz 65MHz 72Hz 75.0MHz

1024 x 768

16 BPP. 64k colours 5-6-5.

75Hz 78.5MHz 60Hz 108.0MHz 1280 X 1024 8 BPP. 256 colours out of a

palette of 256.

75Hz 135.0MHz

TABLE 6 - CRT DISPLAY RESOLUTIONS

Connection to flat panel displays is made through the 40-way 0.05” pitch connector J8. Connection is made from the J8 connector to flat panels using a ribbon cable.

DSP Design also makes a rang e of interface boards for the display end of t his 40way cable. These interface boards suit many 640 x 480, 800 x 600 and 1024 x 768 TFT LCD displays. The interface boards, known as the TFTIF range, solve the otherwise tedious problem of wiring between the TP400 and the display. These interface boards carry power to the displays from the TP400, and can switch off power to the LCD when the display is placed into a suspend mode. The interface boards also convey a backlight enable signal from the TP400 to the display, from where it can be taken t o the backlight inverter. Appendix F contains descriptions and pin assignments of these interface boards. See Appendix D for ordering information.

The TP400 drives the f lat panel signals at 3.3V levels, rather than 5V levels. These

3.3V signals are compat ible with both 5V and 3.3V displays. The 40-way ribbon cable carries both 5V and 3.3V power supplies to the flat panel display.

3.10.3 External Graphics Cards, and No Graphics

The BIOS searches for VGA boards on t he PC/104 bus or PC/104-Plus bus. If these boards are located then the Geode GX1 internal graphics controller may disabled and the off-board VGA boar d is used instead. Alternatively, it is possible to operate with the two display controllers simultaneously, for operating systems such as Windows 98 that support multiple displays. The operation of the TP400 in the presence of an

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external graphics adapter is defined by the BIOS Setup program (Advanced / Advanced Chipset Control / Multiple Monitor Support menu). It is also possible to disable the internal gr aphics controller, and operate the TP400 without any gr aphics controller at all. This is done in the Advanced / Advanced Chipset Control menu.

3.10.4 Native Display Drivers

Native display drivers will give better performance than treating the display controller as a VGA device. They will also overcome the SMI issue described in section 3.10.5.

Drivers for W indows operating systems (Win 3.1x, W in 95/98 and Win NT4.0) are also provided on the TP400 Utilities Disks.

Native display drivers also exist for Linux, QNX and VxWorks. Contact DSP Desig n if you need to use these operating systems.

3.10.5 The System Management Interrupt Issue

There are a number of solutions to this problem. The first is to disable the Geode VGA controller. This can be done in the Setup menu ( in the Advanced / Advanced Chipset Control menu). Another alter native is to use an external graphics controller board. The next option is to use a native-mode display driver, written specifically for the Geode GX1. These drivers do not need to em ulate VGA hardware, and so the SMIs do not occur. Native-mode drivers are available for Windows 95/98, Linux, Windows NT, QNX, VxWorks. Drivers for other operating systems may become available in the future, so ask if you are interested.

There are two solutions f or Linux. Text based users should use VESA frame buf fer console. Graphics based users should use the native Geode X-Windows display driver. In both cases an 8-bpp or 16-bpp mode should be used. DSP Design can provide further information on this.

If a native display driver is not available the problem can be greatly reduced by operating the display controller in an 8 bits-per-pixel display mode, such as VESA mode 101h. In these modes t he regular 1ms SMI interrupt stops, though there are still SMIs that occur whenever the screen is updated. We have produced a simple program called DOSMODE that can be used to change the video mode. This is included on Utility Disks.

158004.B00 33

3.10.6 PanelLink

The TP400 includes a PanelLink transmitter chip, which can be used to drive displays located at up to 10 meters from the TP400.

PanelLink is a technology which converts the digital sig nals normally sent to a TFT LCD into four high-speed serial data streams which can be transmitted over four twisted pair cables. PanelLink was invented by Silicon Image, and has been adopted by the DVI (Digital Visual Interface) consortium for use with digital monitors. For further details of the technology see these web sites:

www.siimage.com www.ddwg.org

To use the PanelLink interf ace on the TP400 the BI OS Setup prog ram must be used to enable and select a TFT display of the req uired resolution. Link LK19 must be set to enable the PanelLink transmitter. If this is done then the transmitter will encode and transmit the signals that are being generat ed for a local TFT display. Connection can be made to the PanelLink signals at connector J7.

You will need to connect the TP400 to a PanelLink monitor through twisted pair cable. In practice we have found that standard CAT5 Ethernet cable will work, but we would recommend a higher quality, shielded cable, such as supplied by Molex as part of their MicroCross DVI Connector System product range.

DSP Design may be introducing further PanelLink accessories. Ask us if you are interested.

3.10.7 TV Clock

A signal called TV_CLK is available at the 40-way flat panel connector J8. The TV_CLK signal is an optional input to the CS5530A chip. It can be used as t he

timing reference for the graphics sub-system, therefore enabling the Geode graphics sub-system to be synchronised to external TV signals.

DSP Design offers no software support for suing this signal.

34 158004.B00

3.11 VIDEO PLAYBACK

The Geode GX1 architecture provides hardware support for the playback of video recordings. This substantially improves the pict ure quality and playback frames per second when decoding MPEG and other video files.

Video playback logic present within the Geode GX1 chip set includes colour-space conversion logic, scaling hardware, X/Y video filt ers, overlay colour-key and gamma correction.

Drivers that make use of this hardware are loaded when the Windows 95/98 graphics drivers are installed.

3.12 AUDIO RECORDING AND PLAYBACK

The Geode GX1 architecture provides a SoundBlaster-compatible sound system. This includes logic to record and playback .W AV files and .MID files. Drivers for the audio functions are loaded when the Windows 95/98 display drivers are loaded. Separate drivers are provided for Windows NT.

Due to a lack of connectors the analog to digital convertor chip shares pins on connector J6 with the SoundBlaster audio circuitry. Appendix B describes how pins on this connector can be assigned to one function or the other.

The TP400’s external connections are for Line In and Line Out (stereo) and Microphone In (mono). The PC speaker (PC Beep) is also routed through the sound system circuitry, and can be mixed with other audio streams and sent out the Line Out outputs.

The TP400 provides power for the microphone. A voltage of about 2.2V is applied to the microphone through a 2k2 resistor.

3.13 SPEAKER

A PC compatible loudspeaker port is implem ented within the Geode GX1. This allows for production of tones, tunes, keyboard clicks etc. PC software that uses the speaker to generate sound will therefor e operate as expected with the TP400. The TCDEVPLUS has a small loudspeaker mounted to it and connection is made to the TP400 via the J4 I/O cable assembly. External speakers should be connected between the J4 signal called SPKR and VCC (+5V).

The speaker circuit is very simple: the logic level from the core logic drives the gate of an open drain MOSFET which has its source pin connected to GND. The speaker connects between the source and VCC, through a current limiting resistor.

The speaker signal is also sent to t he audio codec, so that the PC’s beeps will be fed to external speakers, through the LINE OUT signals (see section 3.12 for further details).

158004.B00 35

3.14 USB PORTS

The TP400 provides two USB ports. USB stands for Universal Serial Bus, and is designed to rationalise connect ions on PCs by providing a single port that is able to connect to a wide range of peripherals: keyboards and mice, printers and modems, scanners, video cameras and data acquisition systems, to name a few.

Access to the USB ports on the TP400 is throug h the eight-way connector J9. DSP Design manufacture a small print ed circuit board, carrying a dual USB connector and EMC filtering components, which can be connected to the J9 connector by a short cable assembly. The USB printed circuit board is called the TP300USB and the cable assembly is the TP400ET-CAB. The TP300USB is designed to be mounted on an enclosure; this location allows EMC filtering to be optimised.

The TP300USB and TB486-ET are sold as optional extras, although equivalent circuitry exists on the TCDEVPLUS (but not on the TCDEV). See Appendix D for ordering information.

A circuit diagram and mechanical drawing of the TP300USB are given in Appendix K. USB keyboards can be connected to the USB por ts, and can operat e simultaneously

to the PS/2 keyboard. Thus up to three keyboards can be active at once. Windows operating systems r ecognise the USB device (as a Compaq USB hub) and

install the correct drivers. Thereafter as Windows sees new USB devices being plugged in (such as cameras) it will ask for the drivers for those devices to be added.

In accordance with the requirements of t he USB specification, power is supplied to a USB peripheral through a current limiting circuit. There is such a circuit on the TP400, which limits current to about 500mA per USB channel. Some users have reported that some USB devices do not operate correctly when directly plugged into the TP30, but that they do when plugged in via a powered hub. This leads us to believe that these USB peripherals may be exceeding the power output of the TP400.

By default the BIO S disables the USB port s. T hey should be enabled using the BI OS Setup program. T he USB control can be found in the Advanced / Advanced Chipset Control Menu. For W indows it is only necessary to enable the "USB Host Controller" option. The "USB BIOS Legacy Support" is only f or use with USB keyboards under MS-DOS, and should not be enabled otherwise.

The USB controller is treated as a PCI device. It is PCI slot 1 (see sect ion 4.3). It is allocated an interrupt, often IRQ11, by the BIOS’s Plug and Play software (see section 4.5 for details).

3.15 ETHERNET

The TP400 includes a 10/100Base-T Ethernet controller chip. T his allows the TP400 to form part of a Local Area Network (LAN).

The chip is the National Semiconductor DP83815, and it is connected to the on-board PCI bus as the slot 4 device (see 4.3). The chip is conf igured by the Plug and Play

36 158004.B00

BIOS during the POST process, following reset. It is both I/O and memory mapped and uses one interrupt. The memory and I/O addresses, and the interrupt, are allocated by the Plug and Play BIOS so as to avoid clashes with other resources. The chip is typically configured to use 256 bytes at I/O address 0ff80h, 4k bytes at memory address 0fedff000h and I RQ10. The chip can act as a PCI bus master, for fast and efficient transfer of data across the PCI bus.

Drivers are available for a number of operat ing systems, including DOS, Windows, Netware, VxWork s and Linux. These are found on the TP400 Utilities Disks. Drivers for other operating systems may also available. Contact DSP Design for details.

The Ethernet chip is connected to the network’s twisted pair cable throug h a small printed circuit board called the TP400ET. This is joined to the TP400 with a short length of unshielded twisted pair cable. The T P400ET contains the Ether net isolation transformer, EMC filters and an RJ45 connector with status LEDs. The cable assembly is the TB486ET-CAB. The TP400ET is designed to be mounted on the enclosure; this location allows EMC filtering to be optimised.

The TP400ET and TB486ET-CAB are sold as optional extras, although equivalent circuitry exists on the TCDEVPLUS (but not on the TCDEV).

A circuit diagram and mechanical drawing of the TP400ET are given in Appendix J. The TP400ET has two status LEDs. The green LED connects to the LED10 and

LED100 pins of the DP83815 and glows whenever the DP83815 receives valid 10Base-T or 100Base-T link pulses. T he yellow LED connects to the LEDACT pin of the DP83815 and glows when the DP83815 transmits or receives a frame.

A serial EEPROM is connected to the DP83815. The EEPROM is programmed during the manufacturing process. It contains the 6-byte Ethernet address (IA, or Individual Address), as well as defining other parameters.

3.16 ANALOG TO DIGITAL CONVERTER

The TP400 includes a four channel 12-bit analog to digital converter chip. The converter allows analog signals to be monitored.

The analog to digital converter is a Maxim MAX1247 device. Communication with the A/D chip is throug h a serial link that is im plemented in the Utility Register . Using this communications link the processor may configure the A/D converter or make conversions.

The A/D converter has four inputs, called ADC0, ADC1, ADC2 and ADC3. These inputs can be between 0V and +5V. T he input voltages must not extend beyond this range, or else internal protection diodes will begin conducting . If there is a chance of the supply voltages exceeding the supply rails then current limiting resistors m ust be added external to the TP400, to limit this current to 4mA. This same restriction applies when the power is switched off - if the analog voltage is still applied to the A/D chip when the TP400 is powered off then the internal protection diodes will conduct, and so the current limiting resistors must be used.

The voltages are measured as a proportion of a reference voltage, VREF. VREF defines the input voltage t hat provides the f ull-scale dig ital reading. The VREF pin on

158004.B00 37

the A/D chip can be driven from an external voltage source, or from the on-board VCC supply voltage. A solder link allows this selection to be made. The accur acy of the measurement of course will be limited by the accuracy of the VREF voltage.

Measurements can be made as “single-ended” or “differential” measurements, as programmable options. In single- ended mode each of the four inputs are measured with respect to the AGND (0V) pin. (AGND is connected to the digital GND at a single point on the TP400). In differential mode the difference between two inputs is measured. The differ ence between ADC0 and ADC1 can be measured, as can the difference between ADC2 and ADC3.

Measurements can also be made as unipolar or bipolar, as programmable options. In Unipolar mode an input voltage of AGND will give a digital output of 0000h, and an input voltage of VREF will give a digital out put of 0FFFh. In bipolar mode an input voltage of VREF/2 will give a digital output of 0000h, an input voltage of VREF will give a digital output of 07FFh, and an input voltag e of 0V will give a digital output of 800h. Voltages between 0V and VREF/2 are treated as negative voltages, and converted into twos complement negative numbers. It is probably only sensible to use bipolar mode in conjunction with differ ential mode, where the dif ference between two inputs can be negative as well as positive.

Sample software for the A/ D converter is provided on the TP400 Utilities Disk. This software makes measurements using the A/D converter. The software may be used as a guide to users who wish to write their own A/D code.

A temperature sensor is provided on the TP400. This is mounted underneath the Geode GX1 processor chip, and thus measures a tem perature that will be related to that of the Geode GX1 package. Thus the temperature of the G eode GX1 can be estimated. This feat ure was added to allow the power management software to slow the processor down if it got too hot. At the time of writing this power management feature has not been implemented.

The temperature sensor is connected via a solder link t o ADC3. If ADC3 is required to measure an off-board voltage then the solder link can be removed.

The temperature sensor is the National Semiconductor LM60C. It has a voltage output given by:

V = (T x 0.00625) + 0.424 where T is temperature in degrees C. Expressed differently, the output is 6. 25mV per degree C, with an offset such that 0

degrees C gives 424mV. Alternatively: T = (V - 0.424) x 160 The data sheets for the MAX1247 and the LM60C are on the TP400 Utility Disks. Due to a lack of connectors the analog to digital convertor chip shares pins on

connector J6 with the SoundBlaster audio circuitry. Appendix B describes how pins on this connector can be assigned to one function or the other.

38 158004.B00

3.17 SERIAL EEPROM

The TP400 has a ser ial EEPROM chip fitted. This is used primarily to store set-up parameters in systems t hat lack a battery to retain config uration data in the CMOS SRAM. There is some space available in the serial EEPROM for users’ data. The serial EEPROM chip also contains the watchdog timer, which is also accessed through the EEPROM's serial interface.

See section 6.7 and 6.8 f or information on using the serial EEPROM utility progr ams. See section 5.2 for details of the watchdog timer.

3.18 UTILITY REGISTER

The TP400 has a Utility Register that controls a number of peripheral functions including the serial EEPROM, analog to digital converter interf ace and Flash memory programming. The Ut ility Register is f ormed by a number of the GPIO pins within the PC97317 Super I/O chip and appears in the I/O address space. The Utility Register occupies eight 8-bit I/O locations at addresses 0E0h - 0E7h.

T he Utility Register is used extensively by the Flash File System driver software and

the serial EEPROM and analog to digital convertor sof tware, and will not normally be accessed by the user.

Table 7 gives the function of each bit in the Utility Register.

Following reset all bits are set to logic 1. They have internal pull-up resistors f itted. The BIOS config ures the pins as output s or inputs. W hen writing to the r egisters the user should read the current state, change only the required bits, and write the results back. Users should not change bits they do not understand, or the TP400 may stop working.

Note that two bits are present at address E4h, bit 7. T he SO bit is normally present in this location. The Flash File System software may sometimes change the function of this bit to BA22, but it will restore the f unction to that of SO when the flash operation is complete. (Users who want to fully understand this should read the GPIO section of the PC97317 Super I/O data sheet, and note that the eight bits at address E0h are GPIO port 1 ( in G PIO bank 0), the next eig ht bit s at address E4h ar e GPI O Port 2 (in GPIO bank 0) and the BA22 bit is bit 7 of GPIO Port 3 (in GPIO bank 1), which is also accessed at address E4h).

158004.B00 39

PORT BIT FUNCTION E0h 0 BA14 (For Flash memory bank switching)

E0h 1 BA15 (For Flash memory bank switching) E0h 2 BA16 (For Flash memory bank switching) E0h 3 BA17 (For Flash memory bank switching) E0h 4 BA18 (For Flash memory bank switching) E0h 5 BA19 (For Flash memory bank switching) E0h 6 (not used) E0h 7 BA20 (For Flash memory bank switching) E4h 0 BA21 (For Flash memory bank switching) E4h 1 /ENFLASH (Enables access to the Flash memory chips when 0) E4h 2 (not used) E4h 3 /CSADC (To CS pin of the A/D converter. Active low.) E4h 4 /CSEEPROM (To serial EEPROM. Active low.) E4h 5 SK (Clock to serial EEPROM and A/D Converter.) E4h 6 SI (Data to serial EEPROM and A/D Converter.) E4h 7 SO (Data from serial EEPROM and A/D converter.) E4h 7 * BA22 (For Flash memory bank switching)

* Note - see text for descrip ti o n o f this bit.

TABLE 7 - UTILITY REGISTER BIT A LLOCATIONS

40 158004.B00

4 STAND-ALONE OPERATION AND EXPANSION BUSES

The TP400 will operate as a stand-alone single board computer, or it can use the PC/104 bus interface to expand its capabilities with the wide range of PC/104 bus I/O cards currently available. The PC/104-Plus bus allows for expansion using high speed PCI chips. This section of the manual descr ibes f irst t he stand alone oper ation and then operation on the PC/104 and PC/104-Plus buses.

4.1 STAND-ALONE OPERATION

The TP400 will operate as a single board computer with the addition of the appropriate peripherals and a sing le +5V power supply. In stand-alone operat ion the TP400 need not be plugged into a bus.

The TP400 requires a +5V power supply. Power can be supplied in one of three ways.

The best option is to use the power connector J101. This is a four pin right-angle AMP HE14 shrouded header located near the Geode GX1 processor chip. Appendix E includes pin assignments of this connector and part numbers of suitable mating connector.

The second option is to use the PC/104 or PC/104-Plus buses. The PC/104 bus connectors include a number of +5V and GND pins. Some or all of these pins can be connected in parallel and the resulting +5V and GND connected to t he power supply. This is the way the T P400 would be powered if it was inserted into a mother board of the user’s own design.

The third option is to provide power to the board through the 50-way I/O connector J4. This also includes a number of +5V and GND pins.

Users should take care to provide power to the TP400 through cables that are as short and thick as possible, and to mak e use of as many of the power and ground pins as possible, connecting them in par allel. This is to minimise the voltage drop that will occur through the resistance of the power cables.

The battery pin must not be connected to +5V and must not be left floating. See section 3.6 for further details.

4.2 PC/104 BUS

The PC/104 bus is the same from an elect rical and timing point of view as the ISA bus found in PC computers. However it is mechanically different, using a stacking connector instead of the gold-plated edge connector used in the PC.

The PC/104 interf ace is via the J1 and J2 connectors along the bottom edge of t he TP400. The 64-way J1 connector provides the 8-bit data bus and the 40-way J2 connector provides the 16-bit sig nals. The TP400 is able to interface with both the 8-bit and 16-bit modules that meet the PC/104 specification.

158004.B00 41

Pull up resistors of 10k ohms have been added to the SD0 - SD15 data bus signals. The IOCHRDY, /IOCS16, /MEMCS16 and /ZEROWS signals have 330 ohm pull up resistors. There are 4K7 pull-up resist ors on all IRQ signals on the PC/104 bus and also on the /IOCHCHK pin. The DREQ signals have 4K7 pull-down resistors.

The TP400 is PC/104 compliant. That is, the TP400 conf orms to both the electrical and mechanical specifications laid down by the PC/104 V2.3 document. There are some minor limitations on TP400 PC/104 bus operation, which are discussed below.

The TP400 has male PC/104 pins only, and so must be positioned at the top of a PC/104 stack. This is because the provision for cooling the Geode GX1 chip prevents a board being stacked on top of it.

The TP400 complies with the mechanical aspects of the PC/104 V2.3 specification. This includes the use of polarizing pins on the J1 and J2 connectors. Some earlier versions of the PC/104 specification did not use polar izing pins and it was seen that this could result in possible misalignment and subsequent product failure if power was applied before the error was discovered. “Key” positions have been assigned to the J1 and J2 connectors. These can be seen on the J1 and J2 pin assignment diagrams detailed in Appendix E. The key positions have had their pin removed and the socket hole has been blocked to prevent entry by any adjacent pin.

Users should note that any boards produced to PC/104 specif ications prior to V2.2 might not mate with V2.2 or V2.3 boards. Prior to the V2.2 specification the key positions were not present, and J2 could optionally have been a right-angled connector. The V2.2 and V2.3 specifications do not allow the right-angled J2 connector. Both the J1 and J2 connectors on the TP400 are mounted vertically.

The PC/104 specification (version 2.3) is available on DSP Design's web site (www.dspdesign.com).

4.3 PC/104-Plus BUS

The PC/104-Plus specification extended the ear lier PC/104 specification by adding a PCI bus interface. This is elect rically the same as the PCI bus used in desk-t op PCs, but it uses a high-density 120-pin connector along t he opposite edge of the PCB to the PC/104 (ISA bus) connectors.

The PC/104-Plus bus standard allows existing PC/104 expansion boards to be used, but also allows for high-perform ance expansion boards using PCI bus logic chips. An example of this is the TCVI DEO board from DSP Design, a real-time video capture board that digitises PAL or NT SC video and bursts the data across the PCI bus in real-time into the memory of the Geode processor.

The PC/104-Plus specification allows for t he addition of up to four expansion boards using the PCI bus. PC/ 104 boards can be included in t he system as well. The boards can be configured by a switch or similar to occupy one of four "slot s", slot 1 to slot 4. (Note that in early BIOSes Slot 1 is not supported, so boards must be configur ed as slot2, slot 3 or slot 4.) The on-boar d Ethernet chip is normally configured as the slot 4 device.

The Geode GX1 pr ocessor used on the TP400 has 3.3V PCI bus signals which are

42 158004.B00

not 5V tolerant. This means that t he TP400 cannot be used with PC/104-Plus or PCI boards which have 5V signal levels. It will operate with 3.3V boards and with boards which support either 3.3V or 5V operation. The TCVI DEO video capture board from DSP Design can be used with the TP400. The TP400’s VI/O power supply pins are configured to be at 3.3V.

Most of the PCI bus signals are bussed to all PCI boards in the system. Some signals however are unique to each board. These are the IDSEL, clock, bus request and grant pins. The interrupt pins also receive special treatment.

Each board receives a different address pin rout ed to its IDSEL pin. This allows each PCI board to be allocated an individual "PCI Device" number. T he IDSEL pin is used during the configurat ion of each PCI Device. The PC/104-Plus spec states that the four IDSEL signals should be connected to AD20-23.

There is a separate 33.3MHz clock for each board. The bus request/bus grant signals are also routed to each board separately. Note

however that the TP400 only supports bus request/bus g rant signals to the first two PCI expansion boards.

The interrupt pins are "rotat ed" one position with every board. The means that if four PCI boards are each asserting a single interrupt request (on their I NTA# pin), the PCI bridge (in the CS5530A chip) receives four diff erent interrupt requests, one on each of its four INTx# pins.

Table 8 describes the allocation of these point-to-point signals within a TP400 system. This table also notes the allocation of the IDSEL sig nals to the PCI f unctions within the CS5530A chip. (The CS5530A incorpor ates two PCI functions - the USB Controller and the "Chip set registers", which include the PCI to ISA bus bridge, audio, video, IDE and power management functions).

PC/104+ MODULE SLOT

SWITCH POSITION

IDSEL ADDR.

PCI DEVICE

CLK PIN REQ/

GNT PAIR

5530A INTA#

5530A

INTB#

5530A INTC#

5530A INTD#

1 0 or 4 AD20 Ah CLK0 0 INTA# INTB# INTC# INTD# 2 1 or 5 AD21 Bh CLK1 1 INTB# INTC# INTD# INTA#

3 2 or 6 AD22 Ch CLK2 - INTC# INTD# INTA# INTB# 4 3 or 7 AD23 Dh CLK3 - INTD# INTA# INTB# INTC# 5 - AD24 Eh - 1 INTA# - - CS5530A Chip

Set Registers

- AD28 12h - - - - - -

CS5530A USB Controller

- AD29 13h - - INTA# - - -

TABLE 8 - PCI BUS RESOURCE A LLOCATIONS

The on-board Ethernet chip is normally configured as slot 4, although it could be configured as a slot 5 device (see Appendix B for conf iguration options). The slot 5 entry in the above table is for the Ethernet chip when it is configured as slot 5.

For a f ul l d es c ri pt io n o f t he PC I bu s, se e th e P CI bu s sp ec if i ca t io n ( www. pc is ig . co m ). The PC/104-Plus specification (version 1.1) is available on DSP Design's web site (www.dspdesign.com).

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4.4 PC/104 AND PC/104-Plus CLOCK AND RESET SIGNALS

4.4.1 PC/104 Clock and Reset Signals

Two PC/104 clocks are provided: the bus clock (BUSCLK) and an oscillat or (OSC). The BUSCLK runs at 8.33MHz. The OSC signal is a clock running at 14.3181MHz.

The TP400 can reset the PC/104 bus. See section 5 for details. The TP400 drives the PC bus RESETDRV signal but cannot be reset by the RESETDRV signal.

The TP400 can be reset by issuing a low going pulse on the /RESET line of the J4 connector. In this way a system reset can be generated by an external signal or switch. The TP400 will then force the RESETDRV signal of the PC/104 bus to be driven. The TCDEVPLUS has a push button switch connected between /RESET and GND. Pressing this switch momentarily will reset the system.

4.4.2 PC/104-Plus Clock and Reset Signals

The PC/104-Plus bus provides four 33.3MHz clocks, one for each of the possible expansion boards.

The TP400 can reset the PC/104-Plus bus. See section 5 f or details. The PC/104Plus bus provides an active low reset signal, PCIRST#, which is asserted whenever the on-board hardware reset signal is asserted. The TP400 cannot be reset by asserting the PCIRST# signal.

The TP400 can be reset by issuing a low going pulse on the /RESET line of the J4 connector. In this way a system reset can be generated by an external signal or switch. The TP400 will then force the PCIRST# sig nal on the PCI bus to be driven. PCIRST# can also be asserted by system software, and in fact this happens during the BIOS POST. The TCDEVPLUS has a push button switch connected between /RESET and GND. Pressing this switch momentarily will reset the system.

44 158004.B00

4.5 INTERRUPTS

The Geode GX1 chip set contains the same inter rupt controller circuit as is present on all PC computers. This consists of t wo 8259 type interrupt circuits, each with eight interrupt inputs. One 8259 is connected in cascade with the other, leaving 15 interrupts available.

Some of these 15 interrupts are used internally to the Geode GX1 chip set. Other interrupts are connected to on-board peripherals ( serial ports and disk contr ollers for example). Further interrupts can come f rom the PCI bus. In the case of most of the on-board interrupts, if the on-board peripheral is not programmed to generate interrupts then the interrupt may be used on the PC/104 or PC/104-Plus buses.

4.5.1 On-Board and PC/104 Bus Interrupts

Table 9 shows how the interrupts are assigned. The sixteen entries in the table are the “usual” PC interrupts. The next column is either mark ed “internal”, indicating that the interrupt is routed entirely within the Geode GX1 chip set, or "on-board", indicating that it is connected to an on-board TP400 peripher al but may be available on the PC/104 or PC/ 104-Plus buses, or else "external", indicating the int errupt has no on-board use. The next column indicates whether the Plug and play (PnP) BIOS is aware of the interrupt requirement of the peripheral. The last column indicates whether the IRQ pin is connected to the PC/104 bus connectors.

Note that this table mentions the on-boar d interrupt from the USB contr oller and the SoundBlaster-compatible audio circuitry. These sub-systems, internal can to the Geode chipset, can be set to a variety of interrupt levels, or disabled.

The SoundBlaster-compatible audio sub-system uses an int errupt (IRQ5 by default, but alternatively IRQ9, IRQ5, IRQ7 or IRQ10). This interrupt can be changed, or the SoundBlaster system can be disabled, which frees the interrupt for other purposes.

The USB controller uses an interrupt (normally IRQ11) but this interrupt can be changed, or the USB controller can be disabled, which fr ees the interrupt for other purposes. Similarly the Ethernet controller can be allocated a different interrupt.

The allocation of inter rupts to PCI bus devices, which includes the USB and Ethernet controllers, is discussed in section 4.5.2.

158004.B00 45

PC IRQ

INTERNAL/ EXTERNAL

PnP AWARE? PC/104

BUS?

ALLOCAT ION

0 Internal Yes No Timer 1 On-Board Yes No Keyboard in PC97317 Super I/O

chip 2 Internal N/A No Cascades second 8259 chip 3 On-Board Yes Yes COM2 in PC97317 Super I/O chip 4 On-Board Yes Yes COM1 in PC97317 Super I/O chip 5 On-Board Yes

(SoundBlaster)

Yes COM3 in extra UART chip, or

SoundBlaster

(See text above). 6 On-Board Yes Yes Floppy Disk drive in PC97317 7 On-Board Yes Yes Printer port in PC97317 Super I/O

chip 8 On-Board Yes No Alarm interrupt from RTC in

PC97317 9 On-Board No Yes COM4 in extra UART chip. 10 Internal

(normally)

No Yes Normally allocated to Ethernet chip.

IRQ10 is present on PC/104 bus. 11 Internal

(USB) or External (no USB)

No, except PnP is aware of USB

Yes USB default (See text above)

12 On-Board Yes Yes Mouse in PC97317 Super I/O chip 13 Internal Yes No Floating-Point Processor in Geode

GX1 14 On-Board Yes Yes IDE Disk Drive 15 External No Yes

TABLE 9 - INTERRUPT A LLOCATION

Note that the ser ial ports and printer have individual interrupt enable bits, within their register sets. The def ault is for these interrupts to be disabled. T his m eans that IRQ3, IRQ4, IRQ5, IRQ7 and IRQ9 can be used by other PC/ 104 or PC/104-Plus boards if the interrupts are not being used by the serial and printer ports. IRQ12 is available if the mouse controller is disabled. IRQ14 is available if no IDE drives are fitted.

All the PC/104 bus interrupts are progr ammed to gener ate an interrupt on a positivegoing edge.

The Geode GX1 does not have a dedicated NMI pin, so non-mask able interr upts are not available on the TP400’s PC/104 bus. The SERR# and PERR# pins however may generate non-maskable interrupts, which are emulated by SMI code.

4.5.2 PC/104-Plus Bus Interrupts

The PC/104-Plus bus (PCI bus) has four interrupt pins, INTA#, INTB#, INTC# and INTD#. These can be programmed by the BIOS Setup program to cause int errupts on any of the fifteen IRQ levels.

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The PCI bus interr upts are active-low level-sensitive interrupts. In principle, several cards can drive the same INTx# pin low, and one board may drive more than one interrupt line. In practice, few boards drive more than one INTx# line, and a rotation of the INTx# pins fr om one slot to the next ensur es t hat if each of four boards drive their INTA# pin, the T P400 will see one interrupt on each of INTA#, INTB#, INTC# and INTD#.

Table 8 lists the interrupt pin allocation for each PC/104-Plus slot. The on-board Ethernet chip is normally config ured as INTD#, although a solder link

option allows it to be set as INTA# (see Appendix B for configuration information). The internal USB controller within the Geode GX1 chip set is treated as though it

were a PCI bus peripheral. It is connected (internally) to the INT A# line. Its interrupt can also be allocated by the BIOS Setup program (see section 4.5.3 below).

If the USB controller is being used t hen it is not possible to install a PC/104-Plus card that will generate interrupts in the Slot 1 position. This is because both the USB controller and the Slot 1 PC/104-Plus card will attempt to drive the INTA# line. (Current versions of the BIOS do not support any card in Slot 1, but later BIOSes may allow a card so long as it does not conflict with a USB controller interrupt).

When a PCI device (which includes the on-board USB controller and Ethernet chip) is detected by the BIOS during the power-on self test (POST) process, the BIOS allocates an IRQ level to it, from what the BIOS understands to be the pool of unallocated interrupts. It is possible to use a BI OS Setup menu option to influence this allocation. This is discussed in section 4.5.3 below.

4.5.3 Plug and Play Control of Interrupts

The PnP BIOS is aware of most of the interrupt requirements of the on-board peripherals. It uses this information to try to eliminate conflicts between different devices requiring the same IRQ. This is most evident with PCI bus devices, which normally have their IRQ level allocated to them by the PnP BIOS during power-on self test (POST). The PnP BIOS allocates an IRQ level that is believes is unused.

This gives rise to a few anomalies. Firstly, the PnP BIOS is not aware of the existence of COM3 or COM4. It is therefore possible for their interrupts (IRQ5 or IRQ9) to be allocated t o other PnP devices (internal devices or PCI boards) without the PnP BIOS being aware of a conflict. Secondly, the PnP BIOS thinks that the COM1, COM2 and printer ports always require their interrupt s (IRQ4, IRQ3 or IRQ7) , and will not allocate these to other devices, or will flag a conflict if these interrupt s are allocated manually.

The BIOS Setup prog ram allows a considerable degree of manual control over the allocation of interrupts. This can overcom e the PnP anomalies r ef err ed to above. The Advanced / PCI Configuration / ISA Resour ce Exclusion menu allow interrupts to be reserved for COM3 and COM4 if required. The Advanced / PCI Configur ation / USB IRQ and / PCI IRQ menus allow specif ic interrupts to be allocated to the USB and

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Ethernet controllers and to PCI boards. The Advanced / Audio Options menu allows the SoundBlaster audio sub-system to be disabled, or its interrupt to be changed.

4.6 DMA

The Geode GX1 processor contains the same DMA controller circuit as is present on all PC computers. This consists of two 8237 type interrupt circuits, each with four DMA Request (DREQ) inputs and four DMA acknowledge (DACK) outputs. One 8237 is connected in cascade with the other, leaving seven DMA channels available.

DMA channels 0, 1, 2 and 3 can be used for 8-bit DMA transfers, and DMA channels 5, 6 and 7 can be used for 16-bit DMA transfers.

One pair of DMA pins (DRQ2 and /DACK2) is connected to the on- board floppy disk controller, as well as to DRQ2 and /DACK2 pins on the PC/104 bus. I f the floppy disk controller is disabled then these pins can be used f or DMA devices on the PC/104 bus.

The SoundBlaster-compatible audio circuitry within the Geode GX1 chip set also requires DMA channels. These may be set up using the BIOS Setup program.

The PC/104-Plus bus (PCI bus) has no DMA signals.

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5 HARDWARE RESET OPTIONS

A full set of hardware reset options exist for the TP400. The reset circuit is built around the X5043 serial EEPROM chip, which provides reset functions as well as memory. This chip includes a power supply monitor and a watchdog timer. T o avoid glitches on the reset signal, the X 5043 will always hold the reset signal asserted for approximately 200ms. This ensures all circuitry is properly reset, and conforms to the PC/104 bus specification.

The X5043 resets the CS5530A chip, on-board circuitry and the PC/104 bus. The CS5530A chip responds to its r eset by resetting the Geode GX1 processor and the PCI bus.

5.1 POWER SUPPLY MONITOR

The X5043 monitors the +5V supply voltage. W hen the supply drops below about

4.5V the X5043 will assert the TP400 reset signal. Once the power supply returns to within specification, the reset signal will be released af ter further 200ms. This circuit prevents power "brown-out" causing unpredictable behavior.

Users should note that if the voltage drop across the cables that link the power supply to the TP400 is excessive then the power supply monitor may reset the T P400. This may also happen if there are noise spikes on the power supply. It is recommended that all power supply cables be as thick and shor t as possible to m inimize the voltage drop across them.

5.2 ONBOARD WATCHDOG TIMER

A watchdog timer exists on the X5043. The f unction of a watchdog timer is to r eset a computer if the software has crashed. The correct operation of the timer relies on software to access the watchdog timer hardware on a regular basis. If the software crashes, the watchdog timer will not be "kick ed" and so eventually it will time-out and reset the computer. The watchdog timer function is accessed via the Utility Register.

The Utility Register is a multi-function register that among other things g ives access to the four control signals on the X5043 serial EEPROM. The Utility Register is described in section 3.18. The watchdog is enabled by writing an enable command to the X5043 via the Utility Register. Once this has been initiated, an internal clock to the X5043 starts counting and will continue to count until it times out, until the watchdog timer is “kicked” by the user’s application software, or until the watchdog timer is disabled by a disable command sent to the X5043.

The watchdog timer period can be set to approximately 1.4s, 600ms or 200ms, or it can be disabled, by writing different command words to the serial EEPROM command register. Once it has been enabled the watchdog t imer must be accessed repeatedly by the user’s software. If the watchdog timer is allowed to time out the X5043 chip will issue a hardware reset to the TP400 (and to the PC/104 and PC/104 buses).

The watchdog timer is “kicked” by taking its chip select (/CS) pin low then high. T he /CS pin is driven by bit 4 of the Utility Register at I/O address 0E4h. T he TP400 Utility

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Disks has documented sample code illustrating t he use of the watchdog function, and also includes the data sheet of the X 5043. Note t hat it is t he responsibilit y of t he user to design code that will reliably kick the watchdog timer.

The BIOS includes code that disables the watchdog timer immediately after a reset , and thus if a watchdog t ime-out occurs the watchdog timer is disabled unt il after the operating system is loaded and the application software re-enables it. See section 6.9 for further information on the watchdog timer.

The watchdog timer is disabled prior to entering Standby or Suspend modes. After resuming operation the watchdog timer is restored to its previous state.

5.3 RESET SWITCH

The TP400 can be reset by issuing a low going pulse on the /RESET line of the J4 connector. In this way a system reset can be generated by an external signal or switch. The reset switch connects between J4 pins 23 and 24. (Pin 24 is the /RESET input, and pin 23 is a GND pin). The TP400 will then force the RESETDRV signal on the PC/104 bus and the PCIRST# signal on the PC/104-Plus bus to be asserted.

The TCDEVPLUS has a push button switch connected between /RESET and GND. Pressing this switch momentarily will reset the system.

5.4 RESETTING THE PC/104 AND PC/104-Plus BUSES

The TP400 always resets the PC/104 and PC/104-Plus buses whenever the X5043 is driving the TP400 on-board reset signal - that is, in response to a power failure, watchdog timer time-out, or a low going pulse on the /RESET line of the J4 I/O connector.

It is not possible to r eset the TP400 by driving the RESET DRV signal on the PC/104 bus or the PCIRST# signal on the PC/104-Plus bus.

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6 SOFTWARE

The TP400 offers a very high degree of PC compatibility. The vast majority of software (both operating systems and applications software) that will run on a conventional PC will also run satisfactorily on the TP400.

Most users will wish to use the MS-DOS or Windows operating systems (booting from a hard disk, f loppy disk or Flash File System) and t hen run off-the- shelf software, or their own application. Other users will want to use Linux or one of the real-time operating systems, several of which have TP400 Board Support Packages.

DSP Design offers a number of software products to ease software development.

6.1 SYSTEM BIOS

The system BIOS is a program that interfaces between the TP400 hardware, the operating system and application code. It is responsible for controlling the TP400 hardware and providing a standard interface to the higher levels of software. The BIOS also deals with functions such as initialisation and testing of the TP400 hardware following power-on.

The TP400 uses a system BIOS supplied by Phoenix Technologies. Users should note that the BIOS is the copyright of Phoenix.

The BIOS has an in-built Setup program, which can be invoked by typing the F2 key at the keyboard during the boot sequence. Section 6.2 contains more inform ation on the Setup program.

The BIOS is programmed into t he Flash memory chip as part of the manufacturing process. Note that the system BIOS and BI OS extensions are combined in a single 256k byte file, which is programmed into the top 256k bytes of the Flash memory chip. The contents of the Flash memory chip can be changed by the user if necessary, as described in section 6.5. The default is for a system BIOS, a VGA BIOS and the Flash File System BIOS Extension to be program med into the Flash memory.

A number of pre-configured BIOS files are available on the TP400 Utility Disks. These differ in t he BIOS extensions that they contain. See the README.TXT f ile in the BIOS directory of the TP400 Utility Disks for further details.

Under some circumstances the TP400 BIOS may need to be m odified or additional BIOS code may need to be added to the BIOS EPROM. Tools exist to deal with these issues, so contact DSP Design for details.

6.2 BIOS SETUP PROGRAM

The BIOS has an in-built Setup program, which can be invoked by typing the F2 key at the keyboard during the boot sequence. The setup program allows many system parameters to be changed, and then stored in CMOS memory. Amongst the parameters that can be changed are the current time and date, disk drive types, enabling and disabling peripheral devices, security and power management.

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6.2.1 Operation of the Setup Program

The Setup program is menu driven, and its operation should be self-explanatory. Users are advised not to change parameters that they do not understand.

Setup parameters are stored in the on-board CMOS memory, and it is backed-up if an external battery is provided. If no external battery is present then the Setup parameters can be stored in an on-board serial EEPROM, as described in section

6.7. If neither the CMOS SRAM nor the serial EEPROM contain valid data then default settings will be loaded from the BIOS. This will load in default values suitable for operation with the TCDEVPLUS Development System.

The default values can also be restored by an option in the Setup program’s Exit menu. In addition, the F9 key can also be used to reset only those settings on the currently displayed Setup menu.

Many on-board peripheral devices can be enabled or disabled by the Setup program, in the Advanced/Integrated Peripherals menu. W hen peripherals are disabled they are placed into a low power mode, and their I/O addresses and interrupt signals become available for other PC/104 boards. This could be required, for example, to allow the TP400 to co-exist with other PC/104 boards that are already using the standard COM1, COM2 and PRN I/O addresses.

The IDE and floppy disk controllers are amongst those devices that can be enabled and disabled using the Setup program. I f the floppy and IDE disk controllers on the TCDEVPLUS development system are to be used then the on-board controllers should be disabled. The default is for the on-board disk controllers to be to be enabled, to facilitate use of the TCDEVPLUS Development System.

We recom mend that you do not att empt to use one on-board disk controller and one off-board disk controller, as the floppy and IDE disk cont rollers share the use of one I/O address.

The BIOS interrogates t he drives attached to the IDE port and attempts to optimise the parameters for speed and drive format. However, these values can be overridden by the Setup program t hat allows hard disk drive parameters to be manually defined.

The Setup menu includes a security menu. T his allows access to the Setup pr og ram, floppy disk and hard disk boot sector to be password protected. Care should be taken with this, as if the password is forgotten the battery on the CMOS RAM must be removed to reset the password protection. Worse still (or better still!), if the serial EEPROM is being used to save the CMOS settings in the event of batt ery f ailure, the EEPROM will need to be erased or removed bef ore the password protection can be removed.

The Setup program also provides control of the power management features of the TP400. This is described in detail in section 7.

Options exists to allow the BIOS to issue reminders concerning virus checking and disk backup.

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6.2.2 Reducing Boot Time

In later versions of the BIOS options will exist within the Setup program to greatly reduce the amount of time the BIO S spends testing the hardware prior to booting the operating system. T his will result in a reduction in time between resetting the T P400 and running your application. At the same time, m essages printed on the screen by the BIOS can be reduced.

The current version of the BIOS there is one option that affects the boot time. By default a summary screen is displayed prior to booting an operating system. This summary screen can be disabled by the BIOS Setup pr ogram, using the Main / Boot Options menu.

6.3 VGA BIOS AND OTHER BIOS EXTENSIONS

As well as the system BIOS, the Flash memory chip can (and usually does) contain other BIOS extensions. These include the VGA BIOS and the Flash File System BIOS.

6.3.1 Principles of Operation

The system BIOS and the BIOS extensions are combined into a sing le 256k byte file, which is programmed into the Flash memory chip using a Flash prog ramming utility, as described in section 6.5. A number of these pre- configured BIOS image f iles are present on the TP400 Utilities Disk . The pre- configur ed files include options with and without the Flash File System driver.

As well as executing BIOS extensions cont ained within the Flash chip, the BIOS also searches the PC/104 and PC/104-Plus buses for BIOS extension EPROMs that might be present elsewhere in the system. The BIOS searches on every 2k byte boundary from C0000h to just below the system BIOS at E0000h. If valid BIOS extension EPROMs are found on the PC/104 or PC/104-Plus buses then they are executed.

The system BIOS is shadowed, and BIOS extension code in the Flash chip, such as the VGA BIOS and the Flash File System BIOS Extension, is also shadowed. BIOS extensions that may reside on other PC/104 modules (such as VGA boar ds or LAN boards) may also be shadowed. This shadowing is enabled or disabled by the TP400 Setup program, in the Main/Memory Shadow menu.

6.3.2 The VGA BIOS Extension

The standard TP400 boar ds are shipped with a BIOS imag e that includes two BIOS extensions. One is for the VGA controller present on the TP400. The VGA BIOS extension is 32k bytes in size, and is located at address C0000h.

By default the VGA BIOS drives a CRT only. However, the BIOS Setup program allows TFT flat panels to operate as well. The f lat panels can be switched on using the Advanced / Geode GX1 LCD menu item.

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There is a special case relating t o VGA BIOS extensions. Before the TP400 BIOS installs a VGA BIOS f or the on-board gr aphics logic from within the Flash chip it first examines the PC/104 and PC/104-Plus buses, looking for any other VGA BIOS that may be present. If another VGA BIOS exists (because the user is using another graphics controller, or because the TCDEVPLUS’s on-board VGA controller is enabled) then this other VGA BIOS and its associat ed VGA controller hardware may used, depending on BIOS Setup settings.

If a second graphics controller is present then there are three options. In the first option the Geode GX1 graphics controller is disabled and the external adapter is used. In the second case the external adapt er is used as the "prim ary" controller, but the Geode GX1 g raphics controller is retained as a secondary controller, for use by operating systems such as Windows 98 which support multiple screens. The third option is for the Geode GX1 g raphics controller to be used as the primary controller and the external adapter is used as the secondary controller. The select ion between these choices is made by the Advanced / Multiple Monitor Support BIOS Setup menu.

6.3.3 The Flash File System BIOS Extension

The standard TP400 boar ds are shipped with a BIOS imag e that includes two BIOS extensions. The second BIOS extension is the Flash File System BIOS extension. The FFS BIOS Extension is 16k bytes in size and is located at address CC000h.

The Flash File System device allows the Flash mem ory to be configured as a disk drive, as described in section 6.6.

The Flash File System is designed for MS-DOS and related operating systems. It is likely that the Flash File System BIOS extension will not operate with some other operating systems, and may need to be disabled.

The Flash File System BIOS extension can be enabled or disabled by a switch in the BIOS setup menu. By default the FFS BIO S extension is disabled. You should format the FFS as described in section 6.6 before enabling the Flash File System BIOS extension.

The Flash File System driver will cause the Windows 95/98 disk system to run slowly. This is because when the Flash File System is installed Windows 95 uses the 16-bit DOS file system, rather than its faster 32-bit native file system. It is unlikely that Windows 95/98 users will want to use the Flash File System, so these user s should disable the Flash File System BIOS extension.

6.4 MS-DOS AND OTHER OPERATING SYSTEM S

The TP400 will MS-DOS, Windows 95/98, Windows NT, Windows CE and should run any other operating system that will run on a PC. T he computer will boot MS-DOS from a floppy disk, from a hard disk or from the Flash File System.

DSP Design can supply Microsoft’s MS-DOS operating system, and the ROM-DOS operating system f rom Datalight. Bootleg copies of the operating system of course may not be run on the TP400.

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Any other operating system that will run on a 386, 486 or Pentium-based desktop computer should also run on the TP400. For example Windows 3.x, Windows 95, Windows 98, Windows NT, Windows NTE, and W indows CE 3.0 run successf ully on the TP400.

A number of other operating systems work well with the TP300. These include Linux, QNX and VxWorks. Contact DSP Design if you are interested in these operating systems.

Users who are running non-DOS operating systems, including Linux and W indows 95/98, may need to disable the Flash File System BIOS Extension using the BIOS Setup program.

6.5 FLASH MEMORY PROGRAMMING

Flash programming utility programs provide facilities for programming data into the Flash memory chip on the TP400. The program s can erase some or all of the Flash chip, and can write a file from disk to the Flash chip. The most com mon use of these programs is to safely program the BIOS image file into the Flash memory chip.

The Flash programming utility is normally used to write a new BIOS to the Flash memory. It is not required t o create the Flash File System disk in the Flash chip. Care must be taken when using this program to program the Flash chip, since an err or can erase the BIOS, which means the TP400 will stop working. Should this happen the TCDEVPLUS development system can be used to restore the contents of the Flash chip. See the TCDEVPLUS Technical Reference manual for details.

By default a single 2M byte 29F016 Flash chip is installed. The TP400 can be f itted with a second 2M flash chip, or with one or two 4M byte flash chips, as a special order. Flash programming instructions vary, depending on the type of Flash chip installed.

6.5.1 Programming the 2M byte 29F016 Flash Chips.

The following describes t he pr ocess of programming the AMD or Fujitsu 29F016 chip installed as standard on the TP400.

The 29F016 flash device is arranged as 32 sectors of 64k bytes each. Each sector is erased separately, and it is not possible to erase less than 64k bytes at a time. The TP3F016.EXE programming utility used to program the 29F016 device is available on the TP400 Utility Disks.

The program can be run two ways - most commonly to safely program a BIOS image file into the Flash chip, and also in a more flexible way, to allow any file to be programmed at any location in the Flash chip.

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In the safe BIOS programming mode TP3F016 is run with the following single parameter:

TP3F016 -u<filename>

-u -u<filename> (u for ’update BIOS’). Program the specified BIOS image file into the device. In this safe mode the program checks to see if the file is present on the disk, and is a plausible BIOS image (i.e. it is 256k bytes in size). The program then erases t he top 256k bytes in the Flash mem ory, and programs and verifies the file.

In the flexible mode TP3F016 is run with any or all of the following parameters: TP3F016 -e -sxx -p<filename> -v<filename> -oxxxxx -lxxxxx -q -dxxxxx -cx -h

-e If -e is specified the entire device will be erased. If -e is not specified the device will not be erased. The default is to not erase.

-s If -sxx is specified then the sector specified by xx is erased. The value for xx is a hexadecimal number between 0 and 1F. The BIOS is in sectors 1C, 1D, 1E and 1F.

-p -p<filename> program the specified file into the device. This parameter defaults to "do not program”.

-v - v<filename> verifies the contents of the flash device against the data in the file specified by <f ilename>. If the chip and the file dif fer the address of the first byte that diff ers is printed, toget her with the values of the differing bytes. The default is not to verify.

-o -oxxxxxx. St art progra mming the f ile at this o ffset f rom the start of the flash device. xxxxxx is a 21 bit (6 hex digit) hexadecimal number. This parameter defaults to 0. For progr amm ing t he 256k byte BI OS imag e f ile you should use the parameter -o1C0000.

-l -lxxxxxx. This is the maximum numb er of bytes o f data to pr ogram into t he Flash chip. The number of bytes progr ammed will be the either the f ile length or the number of bytes specif ied by this parameter, whichever is the smaller. This parameter def aults to the size of the Flash device (200000h bytes in the case of the 29F016).

-q Quiet. This parameter minimizes screen output. The default is “not quiet”.

-d -dxxxxxx. This opt ion displa ys the cont ents of t he Flash chi p at the 21- bit (6 hex digit) hexadecimal address xxxxxx. T he output is 16 lines each of 16 hex bytes. The default is not to print data.

-c -cx. This option allows one or other of the t wo Flash chips to be selected. T he parameter x can be 0 or 1. Flash chip 1 is defined as the chip containing the BIOS image. This is the chip that is present if only one chip is fitted. The default value is 1.

-h Displays a help menu.

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The TP3F016.EXE program can be used t o write one or more files to the Flash chip, by running the program several times with different -p, -s and -o options each time.

6.5.2 Programming the 4M byte 29F032 Flash Chips.

The following describes t he pr ocess of programming the AMD or Fujitsu 29F032 chip if that is what is installed on your TP400.

The 29F032 flash device is arranged as 64 sectors of 64k bytes each. Each sector is erased separately, and it is not possible to erase less than 64k bytes at a time. The TP3F032.EXE programming utility used to program the 29F032 device is available on the TP400 Utility Disks.

In the safe BIOS programming mode TP3F032 is run with the following single parameter:

TP3F032 -u<filename>

In the flexible mode TP3F032 is run with any or all of the following parameters: TP3F032 -e -sxx -p<filename> -v<filename> -oxxxxx -lxxxxx -q -dxxxxx -cx -h

-e If -e is specified the entire device will be erased. If -e is not specified the device will not be erased. The default is to not erase.

-s If -sxx is specified then the sector specified by xx is erased. The value for xx is a hexadecimal number between 0 and 3F. The BIOS is in sectors 3C, 3D, 3E and 3F.

-p -p<filename> program the specified file into the device. This parameter defaults to "do not program”.

-l -lxxxxxx. This is the maximum numb er of bytes o f data to pr ogram into t he Flash chip. The number of bytes progr ammed will be the either the f ile length

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or the number of bytes specif ied by this parameter, whichever is the smaller. This parameter def aults to the size of the Flash device (400000h bytes in the case of the 29F032).

-q Quiet. This parameter minimizes screen output. The default is “not quiet”.

-d -dxxxxxx. This opt ion displa ys the cont ents of t he Flash chi p at the 22- bit (6 hex digit) hexadecimal address xxxxxx. T he output is 16 lines each of 16 hex bytes. The default is not to print data.

-h Displays a help menu. The TP3F032.EXE prog ram can be used to write one or more f iles to the Flash chip,

by running the program several times with different -p, -s and -o options each time.

6.5.3 Steps to Perform after Programming BIOS

Once you have re-programmed your system BIOS there are several steps that MUST be undertaken to complete the BIOS update process. These steps are listed below.

1. Re-program the system BIOS as discussed above.

2. Re-boot by powering the TP400 system off and on. Do not use a push button reset or a Ctrl-Alt-Del reset.

3. Enter the Setup program by pressing the F2 key.

4. Once in Setup, make whatever changes are appropriate.

4. If you have a hard disk, ensure you set the correct drive parameters.

6. Save the new settings to CMOS memory and exit. This will cause the TP400 to re-boot using the new BIOS parameters.

7. If you have pr eviously run TP3EE.EX E -C (to save CMOS to EEPROM),

then you MUST do this again to save the new BIOS parameters into the serial EEPROM.

6.6 FLASH FILE SYSTEM

This section describes the Flash File System, or FFS. The Flash File System is intended for ROM-DOS, MS-DOS and Windows 3.xx. Users

of other operating systems may not be able to use the Flash File System, or may suffer slower disk operation as a result. In principle Flash file systems could be created for other operating systems, such as Linux, QNX, OS/9 and VxWork s, but at the time of writing this work has not been done and DSP Design cannot support

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these operating systems. This sit uat ion m ay chang e in t he future, so contact us if you have an interest in these operating systems.

6.6.1 Overview

The ability to operate without mechanical disk drives is a key feature of the TP400. To do this you can make use of the Flash File System (FFS) that is provided with every TP400. As well as being more robust than mechanical drives they are also faster, at least for read operations.

The FFS provided with the TP400 is the FlashFX product f rom Datalight Inc. DSP Design have paid a license fee for every standard TP400, so you may use the Flash File System on every standard TP400 you buy. (Some volume users who do not require the FFS may ask for TP400 boards without the license, to reduce costs).

The Flash File System driver is implemented as a BI OS extension or as a loadable

device driver. In order to boot the operating system f rom the Flash File System disk drive the BIOS Extension option must be chosen, as a loadable device driver can only be loaded after DOS has booted from another disk (such as a floppy disk). However, the loadable device driver option can be used when another device (an IDE drive for instance) is the boot device. The loadable device driver is also required during the initial formatting of the Flash disk.

The Flash File System driver is normally implemented as a BIOS extension. This driver must be program med into the Flash memory, and then it is located every time the TP400 boots. The standard TP400 is shipped with the FFS device driver already present in the Flash memory as a BIOS extension and it can be enabled or disabled in the Setup progr am, using the Main menu. By default the FFS BIO S extension is disabled in the Setup program.

The loadable device driver requires the driver to be placed on the boot disk, and it is activated by an appropriate entry in the CONFIG.SYS file.

In normal use you should use either t he BIO S extension or the loadable device driver

- not both. The only time it is permissible to use both is during initial formatting as explained in section 6.6.2.

In either case, the FFS driver operates by intercepting calls t o the BIOS disk drive

sub-system, which uses software interrupt INT13. Calls t hat are not intended for the FFS are passed through to the BIOS. Calls that are intended for the FFS are performed by the FFS driver.

The FFS BIOS extension requires 16k bytes of memory, f rom CC000H - CFFFFH. A small amount of RAM within the 640k bytes available to MS-DOS is also used by the FFS. W hen accessing the Flash memory chip, the FFS driver software does so at memory addresses E0000h - E7FFFh.

The Flash File System driver will cause the W indows 95 disk system to run slowly. This is because when the Flash File System is installed Windows 95 uses the 16-bit DOS file system, rather than its faster 32-bit native file system. It is unlikely that

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Windows 95 users will want to use the Flash File System, so these users should disable the Flash File System BIOS extension using the BIOS Setup program.

6.6.2 Operation of the Flash File System

The standard TP400 is shipped from DSP Design with the FFS BIOS Extension

installed in the Flash mem ory, and the Flash disk already formatted. Thus most of this section is for information only, as steps 2 - 5 below have already been performed.

T he Flash File System software referr ed to here is on the TP400 Utility Disks, in the

FFS directory. To operate with a Flash File System, perform the steps below: 1 Enable the Flash File System using the BIOS Setup menu. This is done in the

Main menu. If you also have ATA disk drives present the FFS can be configured to operate as the first of the last disk drive.

2 Boot your computer from a floppy disk containing the FFS driver in its

loadable device driver form and a suitable entry in the CONFIG.SYS file. The loadable device driver is FTP3AMD.SYS and the corresponding entry in CONFIG.SYS is:

DEVICE=FTP3AMD.SYS

When the Flash File System dr iver loads it will display a sign-on message to confirm that it has been located.

3 Before the Flash File System can be used the Flash disk must be formatt ed,

using a dedicated formatting program called FXFMT.EXE. The syntax of t he

FXFMT program is: FXFMT <drive> /P256 /T<size>M [/options] <drive> is the drive letter, usually C:

<size> is the size of the flash array to format in Mbytes, usually 2. [/options] can be any or all of the following:

/C This is an optional parameter, and tells the program to format the drive

without prompting the user for input (not recommended).

/V This is an opt ional parameter and allows a volume label to be placed

on the disk. After a format, the program will prompt the user for a volume name.

Most users will type: FXFMT C: /P256 /T2M

4 At this point you have a functioning Flash disk, although the disk will not be

bootable and will have no files on it.

60 158004.B00

5 Now the DEVICE=FTP3AMD.SYS entry should be removed from the

CONFIG.SYS file on the boot disk. Note that the FTP3AMD.SYS device driver is only used for formatting the Flash File System.

6 Once the Flash disk has been formatted the user can use the DOS SYS

command to place DOS on the Flash disk. (Note t his step is optional, but the operating system must be added if the Flash disk is to be the boot disk). T o

copy the MS-DOS operating system to the Flash Disk type: SYS C: 7 At this point the TP400 can be re-booted. If all has gone well the Flash File

System BIOS Extension will print a sign-on message and the T P400 will boot

DOS from the Flash disk. In a system without hard disk drives the Flash disk will be allocated the drive lett er C: .

It will be the boot disk (provided that the boot sequence in the Setup utility has C: selected as the boot disk ). If IDE drives are included in the system then the Flash disk can be allocated either the C: drive letter , or the drive letter following the last IDE drive. This allows the IDE drive or the FFS to be the boot drive. This selection is made in the Setup program, Main menu.

The FFS implements a wear-leveling algor ithm, to ensure that all parts of the Flash

chip are equally used. The Flash File System automatically adjusts for the amount of Flash memory fitted

(one or two chips, 2M bytes or 4M bytes each).

6.6.3 Write Operations and Garbage Collection

Writes t o the Flash disk take longer t han reads. This is due to the time tak en by the Flash memory chip itself to write data into its memory cells.

When files are deleted the FFS driver does not immediat ely erase the corresponding

Flash memory. Instead, it marks that memory as being “garbage”, and when the Flash memory approaches its capacity the FFS performs a garbage collection process, in which data which is still required is copied into a spare 64k byte sector, freeing another sector to be erased. The nature of the Flash memory is that it can only be erased in 64k byte sectors. The FFS driver t hus has the task of allocating logical disk sectors to physical areas of Flash memory.

As a consequence of the garbage collection process, some writes will take longer

than others, if they force the FFS to perform its garbage collection operation. This garbage collection process during Flash writes can increase write t ime by as much as sixty percent, as the number of garbage areas grow. This is described in detail on t he Datalight Web site, at http://www.datalight.com/wp-flashfx-perform.htm.

The TP400 Utilities Disk contains a g arbage collection utility called FXRECLM.EXE. This utility can be used to force the FlashFX FFS to perform a garbage collection operation at any time, when executed. Placing an appropriate entry in autoexec.bat would force garbage collection each time the T P400 boots, helping to keep t he flash array performance higher than normal.

158004.B00 61

FXRECLM.EXE usage: FXRECLM.EXE <drive> [<count>] Where <drive> is the drive letter of the flash disk (e.g. C: ), and

<count> is the number of successive garbage collection oper ations to perform on the flash disk. One garbage collection operation will reclaim one 64k sector of flash memory.

The FXRECLM.EXE utility stops the garbage collection process either when <count>

has been reached or when there is no more flash memory to recover, whichever comes first.

For 2M bytes of Flash memory there are 32 sectors of 64k bytes each, four of which

are reserved for system BIOS use. The r emaining 28 sectors are available for flash disk use. Thus to perform garbage collection on all 28 64Kbyte sectors of f lash disk memory use the FXRECLM.EXE utility as follows:

FXRECLM C: 28

6.6.4 Flash File System Statistics

The TP400 Utilities Disk also contains a usef ul utility for reporting the status of the

flash disk. It can be used to f ind out how much flash memory is available, has been

used, and is recoverable through the garbage collection process. FXINFO.EXE usage: FXINFO.EXE <drive> Where <drive> is the drive letter of the flash disk (e.g. C:) T he FXINFO utility provides a detailed flash disk r eport, most of which is of little use

to TP400 users. However the final section (an example of which is displayed below),

is of use in determining f lash memory usage, in particular the ‘Recoverable Space’,

information. The following is an extract from a typical FXINFO display:

... Media Usage Data Used : 639K Free Space : 912K Recoverable Space : 150K

The recoverable space is the amount of memory that can be recovered through t he

garbage collection process. In the example above the recoverable space is reported

at 150K bytes.

62 158004.B00

6.7 SAVING CMOS RAM DATA IN THE SERIAL EEPROM

A serial EEPROM chip on the TP400 provides non-volatile memory storag e and also

incorporates a watchdog timer. The non-volatile memory can be used to back -up the CMOS SRAM, in systems without batteries, or where the battery may go flat. The serial EEPROM chip used is the Xicor X5043. This chip contains 512 bytes of nonvolatile serial EEPROM. The serial EEPROM is accessed through the Utility Register in the PC97317 Super I/O chip.

The BIOS includes a feature that check s to see if the contents of the CMOS memory are valid during the boot sequence. If the CMOS memory does not have valid contents (since there was no battery back-up, f or instance) then the BIOS will check whether the serial EEPROM contains valid CMOS data. If it does then t he data in the serial EEPROM memory will be copied into the CMOS memory and used.

It is the responsibility of the user t o program the serial EEPRO M. A utility program is provided to do this. It is called TP3EE.EXE and is available on the TP400 Utility

Disks. It should be run with the -C parameter, like this: TP3EE -C (Note that the TP3EE program has other uses - see 6.8 and 6.9).

The TP3EE program should be run once the CMOS memory contains valid data -

after running the BIOS Setup program for instance. The contents of the CMOS

registers are then copied into the serial EEPROM. T hese values will be returned to

the CMOS memory by the BIOS if the CMOS memory contains invalid data during

subsequent boot operations.

When the TP3EE.EXE program is run all of the first 128 locations in the CMOS

SRAM module are copied to the EEPROM. Note the 128 locations are made up of

114 CMOS RAM locations, ten real-time clock time and date registers and four

control registers. All 128 are copied to the serial EEPROM. A checksum is added

then appended to the CMOS data in the serial EEPROM. (There are a f urther 128

CMOS memory locations that can be accessed in a diff erent bank in the PC97317.

These locations are not copied to the serial EEPROM.)

During the restore process, when the contents of the serial EEPROM are copied back

to the CMOS RAM, all 128 bytes are copied. This restores the time and date, the

control registers and the memory locations containing data. The BIOS makes use of all of the f irst 114 CMOS memory locations. T here is f urther

CMOS SRAM available, which can be accessed by setting the bank select bits in the

PC97317 Super I/O chip. This is discussed in the PC97317 data book. Users who

require additional SRAM may use the SRAM in other banks. Althoug h only the first 130 locations in the serial EEPROM are currently used by the

BIOS to store the CMOS registers, DSP Design strongly recommends that 256

locations in the serial EEPROM up t o and including address 0FFh are reserved for

possible future BIO S use. This leaves a furt her 256 bytes in the serial EEPROM (at

addresses 100h - 1FFh) available for users. Section 6.8 describes a program that can

be used to read and write CMOS EEPROM locations.

158004.B00 63

6.8 SERIAL EEPROM PROGRAMMING

The X5043 serial EEPROM has 512 (200h) bytes on non-volatile memory. Section

6.7 describes using the serial EEPROM for saving CMOS RAM settings. Addresses 00h - 7Fh in the serial EEPROM are reserved for holding CMOS RAM data, addresses 80h and 81h contain a checksum for the CMOS data, and addr esses 82h

- 0FFH are reserved for future DSP Design use. Addresses 100h - 1FFh remain available for users.

The TP3EE.EXE program allows individual bytes in the EEPROM to be written and read. It also provides a way of testing the EEPROM, enabling and testing the watchdog timer, and copying the CMOS SRAM into the EEPROM. It has the following parameters:

-rxxx - r reads t he data f r om t he ser ial EEPROM at t he address <xxx>, and displays it on the screen. T he xxx par amet er is a hexadecim al number in the rang e 0 - 1FFh.

-wxxx - w writes data into the serial EEPROM at the address def ined by the <xxx> parameter. The data written is the hexadecimal byte specified by the -d parameter. The xxx parameter is a hexadecimal number in the range 0 1FFh.

-dxx -d defines the data value to be written to the serial EEPROM by the -w parameter. The xx parameter is a hexadecimal number in the range 0 - FFh.

-t -t tests the serial EEPROM, by writing to every location. T he previous data is destroyed.

-c -c copies the contents of the CMOS SRAM into the serial EEPROM.

-s -s saves the contents of the serial EEPROM into a file on the current drive

called TP3CMOS.DAT. All 512 bytes are saved. Together with the –p command this can be used to save and restore known CMOS memory configurations prior to putting TP400 systems into production.

-p -p programs the serial EEPROM with the contents of a file on the current drive

called TP3CMOS.DAT. All 512 bytes are written. Together with the –s command this can be used to save and restore known CMOS memory configurations prior to putting TP400 systems into production.

-e -e enables the watchdog timer. The TP400 will be reset unless the watchdog

is kicked (see the -k parameter). This is only used for testing purposes.

64 158004.B00

-kxxx -k kicks the watchdog timer for <xxx> seconds. The xxx parameter is a hexadecimal number in the range 0 - 1FFh.

6.9 WATCHDOG TIMER PROGRAMMING

The watchdog timer is contained within the serial EEPROM chip and is controlled through four pins of the Utility Register. Once it is enabled, the watchdog timer will reset the TP400 if it is not accessed (or “kicked”) regularly. It is up to the user to write code to enable and kick the watchdog timer. As an example, t he source code of a watchdog timer test program is included on the T P400 Utility Disk s. T he test prog ram is called TP3 WDOG.EXE.

The TP3WDOG program has a number of command line options. These can be reviewed by executing the program with the following command-line:

TP3WDOG –H Or: TP3WDOG -? or just: TP3WDOG To start the watchdog timer test type this: TP3WDOG -T TP400 (you must include the spaces) The program enables the watchdog timer, and kicks it regularly, until you type S (in

which case the watchdog times out) or anything else, in which case the watchdog timer is disabled.

The general purpose ser ial EEPROM program, TP3EE.EXE, can also be used to t est

the watchdog timer - see section 6.8. The watchdog timer is kicked by the toggling of its chip select pin (/CS), which is

driven by the Utility Register bit 4 at I/O address 0E4h. Users might consider taking the /CS pin low at one point in their program and ta king it high again in a different point. This reduces the likelihood that a cr ashed program could end up executing a small loop that both set and cleared the /CS pin. Similarly, the watchdog accesses should not be part of a timer-based inter rupt service routine, since a program could possibly crash and leave a timer interrupt correctly operating.

Care needs to be taken if the TP400 power management is to be used. Power management can slow down the processor clock, or even stop it, so that software loops will execute slowly, or even stop entirely. Thus the possibility exists that watchdog timer would time out.

Consequently, the BIOS disables the watchdog timer before entering Standby or Suspend modes, and re-enables it after r esuming high speed operation. Users must be aware of this. In low speed mode the watchdog timer remains operational. User s must confirm that the slow CPU speed still allows the watchdog to be kicked.

158004.B00 65

7 POWER MANAGEMENT

The TP400 includes sophisticated power management hardware and software, which allows the power consumption of the TP400 to be reduced at times when the full performance of the board is not required. This can extend battery life in batteryoperated systems and allow for cooler operation, and thus greater product reliability.

The BIOS can manage power autonomously, without intervention from higher levels of software. It is also compliant with the Advanced Power Management (APM) specification, version 1.2, which can allow APM-aware applications and operating systems to influence the power management of the TP400.

The BIOS work to support power management has not been completed at the time of writing. Later BIOSes will support power management.

66 158004.B00

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158004.B00 A1

APPENDIX A : SPECIFICA TION

Product: TP400

Description: Highly integrated PC/104-Plus format, single board PC

compatible computer.

Processor: National Semiconductor Geode GX1. Clock speed of 300MHz

maximum, with lower clock speeds available for power savings. (300MHz processor fitted as standard).

SDRAM: 32M, 64M, 128M or 256M bytes SDRAM implemented using

144-pin SODIMM memory modules.

Flash Memory: 2M byte of AMD 29F016 Flash memory. (The def ault is f or 2M

bytes of Flash memory; the TP400 can be fitt ed with 4M bytes or 8M bytes as a special order).

Graphics Controller: Internal VGA compatible graphics controller with 2D

accelerator. Up to 4.5M bytes video RAM taken from main system memory. Can drive CRT displays up to 1280 x 1024 and flat panel displays up to 1024 x768. PaneLink transmitter.

Floppy Disk Controller: Drives single 3.5 inch floppy disk drive through 26-way flat

flexible cable. IDE Disk Controller: Drives two IDE devices - hard disk drives or CD-ROMs. Ethernet Controller: National Semiconductor DP83815. 10/ 100Base-T with external

RJ-45 module. Serial interface: RS-232 (COM1, COM2 and COM3). RS-485 full-duplex or

half-duplex option for COM2. COM4 is TTL, TxD and RxD

only. Infrared Comms: COM2 can be configured to operate as an IrDA port. (BIOS

support not yet available for IrDA). Other Infrared modes are

also available. Printer port: Centronics compatible (PRN). Bi-directional. EPP and ECP

compatible. Keyboard port: IBM AT compatible. PS/2 keyboards can also be used. Mouse port: PS/2 compatible. USB ports: Two USB ports. Speaker port: PC compatible. Drives a small external speaker. Audio: SoundBlaster-compat ible audio logic. Ster eo line in and lineout

signals, and mono microphone input signal.

A2 158004.B00

Analog to Digital Converter: Four channel, 12-bits. External reference. 0V to +5V

input range.

Reset circuit: Power supply monitor, PC/104 bus reset, watchdog timer and

external reset switch capability.

Bus interfaces: PC/104 V2.3 16-bit (ISA bus) and PC/104-Plus 32-bit (PCI bus).

Interrupts: Standard PC and PC/AT inter rupts are available for on-board

peripherals or the PC/104 bus: (IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, IRQ9, IRQ10, IRQ11, IRQ12, IRQ14 and IRQ15).

DMA: Standard PC and PC/AT DMA request and acknowledge pairs

available on PC/104 bus. Multiple bus masters (using the /MASTER signal) are not supported.

Connectors: Standard PC/104-Plus expansion bus connectors - male only -

TP400 must be the top boar d in a stack. 14-way, 16-way and 50-way right-angle headers for I/O. A 26-way flat flexible cable for a floppy drive. A 44-way 2mm straight connector for IDE drives. A 40-way 0.05" connector for flat panels. T wo 8-pin SIL headers for Ethernet and USB. A 4-way right angle power connector and 3-way fan connector. SIL PanelLink connector.

Dimensions: PCB - 3.550 inches x 3.775 inches, (91.7 mm x 95.8 mm

approx.). Overall dimensions including connectors, 4.25 inches x 3.775 inches x 1.05 inches, (108mm x 102mm x 27mm approx). Maximum height on the component side of the PCB is

4.35 inches (13.7mm). Weight: 180g Approx. Operating temperature: 0 - 60 degrees C. Humidity: 10% - 90% non-condensing. Power Supplies: +5V only required.

1.03A typical (300MHz, graphics on)

158004.B00 B1

APPENDIX B: TP400 SET-UP PROCEDURE.

This appendix describes fitting SDRAM to the TP400, and solder link settings. The component placement diagrams in Appendix C may be of help in locating the

solder links referred to in this appendix. A number of f unctions can be configured with solder link s on the TP400 board. The

board layout is so dense we have implemented these configuration options with solder links that take less space than jumpers, as well as being more reliable.

Care must be tak en when changing these link ar eas so that no accidental shorts ar e produced. Default settings are noted below.

B.1 PROCESSOR COOLING

The TP400 dissipates up to 5W , most of which is generated in the pr ocessor. Some cooling should be provided, or t he processor may overheat. DSP Desig n can provide a passive heatsink and a heatsink/f an combination, which may be useful. Ultimately cooling is a system desig n issue, and must remain the responsibility of the system design engineer.

B.2 SDRAM CONFIGURATION

The TP400 uses 144-pin SODIMM SDRAM modules for memory. The standard TP400 product is delivered as standard with no SDRAM modules fitted. Users may buy SODIMM modules from DSP Design or fit their own. DSP Desig n carry stock of the SODIMM modules. These modules have been selected to operate correctly with the TP400.

SDRAM should be PC100 compliant. Table B1 lists t he DSP Design part numbers for various memory sizes.

SDRAM SIZE DSP DESIGN PART 32M Bytes SD32 64M Bytes SD64 128M Bytes SD128 256M bytes SD256

TABLE B1 - SODIMM MODULES

Install your SDRAM SODIMM module in the TP400 SDRAM socket, observing its polarity, and observing proper anti-static precaut ions. The SODIMM socket has a lug that engages with a cut-out on the module, which prevents incorrect installation.

B2 158004.B00

B.3 SOLDER LINK AREAS

A number of f unctions can be configured with solder link s on the TP400 board. The board layout is so dense we have implemented these configuration options with solder links that take less space than jumpers, as well as being more reliable.

Care must be tak en when changing these link ar eas so that no accidental shorts ar e produced or created. Default settings are noted below.

Two versions of the TP400 have been shipped. The Rev B board has two additional solder links.

The board revision can be determined by locating the DSP Design document number that appears at various places on the copper and silk screen ident of the TP400. The number 158001.A00 or 158101.A00 identifies a Rev .A00 board. The number

158001.B00 or 158101.B00 identifies a Rev .B00 board.

LK1 - LK4 Not Present

LK1 – LK4 are not present on the TP400.

LK5 PME# Connection

The PCI specification has been extended to include a new signal, PME# (power management event). This signal is not defined on the PC/104-Plus specification. DSP Design have proposed that a previously reserved pin on the PC/104-Plus connector be allocated to this new signal. The pin we recommend is pin C30. In case this pin should be need to be used for a diff erent purpose we have provided a solder link to allow this pin to be disconnected from the TP400's PME# signal.

Pin C30 is PME#: Fit link (default) Pin C30 is not connected: Omit link.

LK6 VREF or Microphone

This link determines whether Connector J6 pin 1 is used for the analog to digital convertor VREF input or output, or the audio codec microphone input. See also LK14.

Pin 1 is A/D convertor VREF: Fit link Pin 1 is audio codec microphone input: Omit link (default)

LK7 ADC0 or LINE_IN_R

This link determines whether Connector J6 pin 2 is used for the analog to digital convertor channel 0 input, or the audio codec Line In Right input.

Pin 2 is A/D convertor ADC0: Fit link Pin 2 is audio codec Line In Right input: Omit link (default)

158004.B00 B3

LK8 ADC1 or LINE_IN_L

This link determines whether Connector J6 pin 4 is used for the analog to digital convertor channel 1 input, or the audio codec Line In Left input.

Pin 4 is A/D convertor ADC1: Fit link Pin 4 is audio codec Line In Left input: Omit link (default)

LK9 ADC2 or LINE_OUT_R

This link determines whether Connector J6 pin 6 is used for the analog to digital convertor channel 2 input, or the audio codec Line Out Right output.

Pin 6 is A/D convertor ADC2: Fit link Pin 6 is audio codec Line Out Right input: Omit link (default)

LK10 ADC3 or LINE_OUT_L

This link determines whether Connector J6 pin 8 is used for the analog to digital convertor channel 3 input, or the audio codec Line Out Left input.

Pin 8 is A/D convertor ADC3: Fit link Pin 8 is audio codec Line Out Left input: Omit link (default)

LK11 A/D Converter Reference

This link is used to select the source of the VREF input voltage to the analog to digital converter. Note that when the link is fitt ed the on-board +5V power supply is not only connected to the A/D converter VREF pin, but is also tak en out to the VREF pin on connector J6 (provided that LK6 is also fitted)

VREF is supplied by on-board +5V: Fit Link (default). VREF is supplied from an external source via J6: Omit Link.

LK12 Clock Shutdown

This link is factory fitted and must not be changed.

LK13 Super I/O Configuration

This link is factory fitted and must not be changed.

B4 158004.B00

LK14 VREF or Microphone

This link determines whether Connector J6 pin 1 is used for the analog to digital convertor VREF input or output, or the audio codec microphone input. See also LK6.

Pin 1 is A/D convertor VREF: Omit Link. Pin 1 is audio codec microphone input: Fit link (default)

LK15 COM2 RS-232/RS-485 Selection

This link is used to select whether COM2 is RS-232 or RS-485. RS-232: No link installed. (Default setting)

RS-485: Link installed.

LK16 Remote Bootstrap

This link needs to be set according to the location of the BIOS. It is normally only

used in the manufacturing process. BIOS is in the Flas h me mo ry: Install link. (Default setting)

BIOS is in off-board EPROM: Do not install link.

LK17 Not Present

There is no LK17 on the TP400.

LK18 PC/104-Plus VI/O Selection

Sets the VIO voltage on the PC/104-Plus connectors. Set V/IO to 3V3: Link 1 - 2 (Default)

Set V/IO to VCC: Link 2 – 3

LK19 PanelLink Disable

Selects how the PanelLink transmitter is to be powered down. Always powered off: Link 1 – 2 Powered off when LCD controller ENAVDD is off:

Link 2 - 3 (Default)

158004.B00 B5

LK20 PanelLink Power

This link is only present on the Rev B TP400 PCB. It is used to r oute either 3.3V or 5V to the 10-way PanelLink connector.

3.3V to J7: Link 1 – 2 (Default)

5V to J7: Link 2 - 3

LK100 - LK102 Processor Clock Speed

These three pins set the Geode GX1 processor clock speed. They are normally factory set and need not be changed. However, users may want to reduce the processor clock speed to reduce power consumption. The 333MHz links are shown here for completeness, although National Semiconductor have not released the processor at this speed. The 133MHz speed should not be used. The changes are made as follows:

CPU SPEED LK100 LK101 LK102

133MHz (test) Fit Link Fit Link Fit Link 133MHz Omit Link Fit Link Fit Link

166MHz Fit Link Omit Link Omit Link 200MHz Omit Link Fit Link Omit Link 233MHz Omit Link Omit Link Fit Link 266MHz Omit Link Omit Link Omit Link 300MHz Fit Link (default) Omit Link (default) Fit Link (default) 333MHz Fit Link Fit Link Omit Link

TABLE B2 - PROCESSOR CLOCK SPEED

LK103 A/D Converter Input ADC3

This link is used to connect the analog to digital converter input ADC3 to the on-board temperature sensor.

ADC3 is connected to on-board temperature sensor: Install link (Default) ADC3 may be supplied externally: Omit link.

B6 158004.B00

LK104 - LK107 Vcore Voltage Selection.

These links are set to select the Vcore voltage for the Geode processor. The Vcore voltage can be chosen to match the processor and the clock frequency.

PROCESSOR CLOCK VCORE LK104 LK105 LK106 LK107

GXm 266MHz 2.9V 2-3 Don’t

Care

Don’t Care

Don’t

Care Geode GXLV 200MHz 2.2V 1-2 OPEN OPEN OPEN Geode GX1 300MHz 2.0V 1-2 LINK OPEN OPEN Geode GX1 266MHz 1.8V 1-2 LINK LINK OPEN Geode GX1 200MHz 1.6V 1-2 LINK LINK LINK

TABLE B3 - VCORE VOLTAGE SELECTION

LK108 Power Supply Clock

This link is factory fitted and must not be changed.

LK109 Ethernet Serial EEPROM

This link is factory fitted and must not be changed.

LK110 Ethernet TxD Circuit

This link is factory fitted and must not be changed.

LK111 Ethernet PCI Slot Selection

This link can be used to select the PCI slot occupied by the Ethernet chip. Slot 4: Link 1 – 2 (Default)

Slot 5: Link 2 – 3

LK112 Ethernet PCI Interrupt Selection

This link can be used to select the PCI interrupt pin used by the Ethernet chip. INTD#: Link 1 – 2 (Default)

INTA#: Link 2 – 3

158004.B00 B7

LK113 SDRAM Clock Feedback

These links are set according to the processor fitted. Geode GX1 Link 1 - 3 (Default)

Geode GXm Link 1 - 2 and 3 - 4

LK114 IDE /PDIAG Pin

This link is only present on the Rev B TP400 PCB. It allows pin 34 of the IDE connector J100 to be connected to GND or to be unconnected. By default it is connected to GND, which is equivalent to the connection on the Rev A board.

Connect /PDIAG pin to GND: Fit Link (Default) /PDIAG is not connected; Omit Link

B8 158004.B00

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158004.B00 C1

APPENDIX C: MECHANICAL DRAWINGS AND SCHEMATICS

The four component placement diag rams that follow may be of help in locating the components referred to in Appendix B. Ther e is one diagram for each side of the two printer circuit boards that make up the TP400.

This Appendix includes mechanical drawings of the TP400, showing the position of pin 1 of each connector.

The drawings are of the REV B00 version of the TP400. The mechanical details are unchanged between the versions, with the exception that the PanelLink connector moves very slightly.

C2 158004.B00

FIGURE C1 - MAIN BOA RD TOP COMPONENT PLACEMENT

158004.B00 C3

FIGURE C2 - MAIN BOA RD BOTTOM COMPONENT PLACEMENT

C4 158004.B00

FIGURE C3 - DAUGHTER BOA RD TOP COMPONENT PLACEMENT

158004.B00 C5

FIGURE C4 - DAUGHTER BOA RD BOTTOM COMPONENT PLACEMENT

C6 158004.B00

FIGURE C5 - MAIN BOA RD MECHANICAL DIMENSIONS

158004.B00 C7

FIGURE C6 - DAUGHTER BOA RD MECHANICAL DIMENSIONS

C8 158004.B00

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158004.B00 D1

APPENDIX D: OPTIONS AND ORDERING INFORMATION

This Appendix lists some of the range of PC/104 products available from DSP Design, and in particular the products related to the TP400. Note that as new products are being released all the time this list may not be complete. Contact DSP Design for a full pric e l ist.

D.1 PROCESSOR BOARDS

Table D1 lists the processor options (only one at this time).

ITEM DESCRIPTION

TP400 Standard TP400 processor board, with 300MHz processor

and without SDRAM.

TABLE D1 - PROCESSOR BOARDS

D.2 SDRAM MEMORY MODULES

Table D2 lists the SDRAM options. The TP400 is shipped without SDRAM so that you can choose the memory capacity that you require. The SDRAM is supplied as a 144pin SODIMM (small-outline dual-in-line package). PC100 chips are used.

ITEM DESCRIPTION

SD32 32M byte SODIMM SDRAM module SD64 64M byte SODIMM SDRAM module SD128 128M byte SODIMM SDRAM module SD256 256M byte SODIMM SDRAM module

TABLE D2 - SDRAM MEMORY MODULES

D2 158004.B00

D.3 TP400 PROCESSOR STARTER PA C K

The best way of starting a TP400 development project is to buy a TP400PAK, which is one of a family of “PAK” products. Each “PAK” product includes the processor itself, the TCDEVPLUS Development System boar d, a TPPSU power supply and a comprehensive set of m anuals, disks, cable assemblies optimized to that particular processor. The PAK products provide most cust omers with all that they need f or their development process, but there are still other accessories that may be of use, and that will need to be ordered separately.

The contents of the TP400PAK product is defined in Table D3. The first five items in the table are common to all of the PAK products.

ITEM DESCRIPTION

TCDEVPLUS Development System TPPSU 45W power supply PSU-xxLEAD Mains Power Lead for TPPSU (specify your

country so we can provide the correct lead) TRM-TCDEVPLUS Technical Reference Manual TCDEVPLUS-UTILS Floppy disk containing software

TP400 Processor board TRM-TP400 Technical Reference Manual TP400-UTILS Utility Disks 2 x TB486ET-CAB Cable assembly for TP400ET, TP300USB TC586HS Heatsink TP300-CRTCAB CRT, audio cable assembly for TP400

TABLE D3 - CONTEN TS OF THE TP400PAK

Note that the T P400PAK does not include DRAM, which must be ordered separat ely. The TP400ET and TP300USB are not req uired since Ethernet and USB connections are on the TCDEVPLUS. A TP400ET and TP300USB would need to be ordered separately if required when the TP400 is rem oved from the TCDEVPLUS. You may also want to order a TFTIF board and LCD cable assembly, and other accessories from the list in section D.5.

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D.4 PC/104 I/O BOARDS

The following list describes a selection of the PC/104 bus cards that are available from DSP Design. Co n ta ct DSP Design for the latest list.

ITEM DESCRIPTION

TADIO12 Analog and digital I/O board. 16 12-bit A/D inputs, 2 12-bit D/A

outputs, 20 digi ta l I/O lines. TPO24 Opto-isolated I/O board. Twelve inputs and twel ve outputs TP406 Parallel I/O and timer board. Forty l i nes of parallel I/O TS400 Four serial interfaces on one board TSYST Board containing a number of functions: floppy and IDE disk

controllers, and serial ports. Can be usef ul to add an extra IDE

disk controller to the TP400. TCBLASTER SoundBlaster-compatible audio I/O board. TCVIDEO Video Capture card with high-speed PC/104-Plus interface. TCM3115B Two slot PCMCIA interface board. TCMDM336 BABT approved modem – to 33k baud TCMM32 16-bit A/D and D/A board.

TABLE D4 - PC/104 I/O BOARDS

D4 158004.B00

D.5 ACCESSORIES

Table D5 lists some or all of the following items may be of use during your development process. Some of the items are included in the TP400PAK product.

ITEM DESCRIPTION

TP400PAK Starter pack for TP400. See section D.3 for full details. The individual items in

Table D3 can also be ordered separately. TP400-UTILS Set of floppy disks containing BIOSes and support software. TRM-TP400 Technical Reference Manual for TP400. TP400ET Ethernet adapter board for TP400 TP300USB USB adapter board for TP400 TB486ET-CAB Cable assembly to connect TP400 Ethernet and USB connectors to the TP400ET

or TP300USB. TP300-CRTCAB Cable assembly - connects TP400 J6 to a 15-way VGA CRT connector. Includes

3.5mm sockets for audio. TP300-COM3CA Cable assembly - connects T P 400 J5 to a 9-way D-type connector. TC586HS Heatsink and thermally conductive doubled-sided adhesive tape, to attach to the

processor.

TCONN Connector Breakout PCB for TP400. Standard PC connectors for keyboard,

mouse, 3 x serial, printer, VGA, power inlet. With EMC filtering. TCONN-PSU Mains power supply for TCON N. 5V, 2.5A output. TPPCI Adapter to allow standard PCI bus peripherals to connect to the PCI connector on

the TP400. TFTIF31 Display adapter board - plugs into Sharp 640 x 480 TFT displays (and others with

compatible pin assignments) and accepts input from TP400. TFTIF41 Display adapter board - plugs into Sharp 800 x 600 TFT displays and some 1024 x

768 displays (and others with compatible pin assignments) and accepts input from

TP400. TFTIFS15 Display adapter board - plugs into Hosiden 1024 x 768 TFT displays and accepts

input from TP400. TFTIF-CAB11 40-way cable assembly for TFTIFxx boards, connector at both ends, length 11

inches. EC586-LCA 40-way cable assembly for flat panel displays, connector at one end, length 10

inches. TFT6KIT 6.4" TFT LCD kit, including 6.4" high-brightness 640 x 480 LCD panel, backlight

inverter, TFTIF31 interface board, TFTIF-CAB11 40-way ribbon cable and cable for

backlight inverter. TS6KIT Touchscreen controller kit for 8.4" TFT LC D. TS8KIT Touchscreen controller kit for 6.4" TFT LC D. U sed w ith T FT 6KIT. TFT10KIT 10.4" TFT LCD kit, including 10.4" high-brightness 640 x 480 LCD panel, backlight

inverter, TFTIF31 interface board, TFTIF-CAB11 40-way ribbon cable and cable for

backlight inverter. TS10KIT Touchscreen controller kit for 10.4" TFT LCD . Used w ith TFT10KIT. TFT12KIT 12" TFT LCD kit, including 12.1" high-brightness 800 x 600 LCD panel, backlight

inverter, TFTIF41 interface board, TFTIF-CAB11 40-way ribbon cable and cable for

backlight inverter. TS12KIT Touchscreen controller kit for 12" TFT LCD . Used w ith TFT12KIT. TS15KIT Touchscreen controller kit for 15" TFT LCD . Used w ith TFT15KIT. TCDOS Microsoft MS-D OS Operating Sy stem. WIN95FL Windows 95 operating system. TCSPACER PC/104 spacer kit - four 0.6 inch spacers plus nuts and screws. TCDISK-xxxx High capacity byte 2.5 inch IDE drive. Capacity may v ary . Inquire before ordering. EC586-IDECA Cable to connect the TP400 to 2.5 inch IDE drives IDE-3020 Cable to convert 2.5inch IDE connector to 3.5 inch IDE connector and vice-versa. DIS26 Slim-line 3.5 inch floppy disk drive with 26-way connector. DIS26-CA 26-way flat flexible cable for DIS26 floppy disk drive. DIS35-26 Adapter to allow connection of a 3.5" floppy disk drive to the TP400, via the DIS26-

CAB flat flexible cable. KBDATPS2 Adapter to allow 5-pin mini-DIN keyboard to plug into the 6-pin mini-DIN keyboard

connector.

TABLE D5 - TP400 ACCESSORIES

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D.6 CF100 COMPACT FLA SH ID E

Compact Flash cards are a useful alternative to I DE drives and floppy disks during development. The are reasonably high capacity, and if you equip your PC with the CFREADER product you are able to transfer files between your development machine and the TCDEVPLUS. The CFREADER is a Compact Flash reader/writer unit that plugs into the printer port of a PC.

The Compact Flash card market is evolving rapidly. Larger devices are becoming available, so if you need a Compact Flash card larger than 128M bytes, please enquire and we will advise you of the current situation.

ITEM DESCRIPTION

CF100 Adapter board allowing Compact Flash cards to be used

as an IDE drive. CF4M 4M byte Compact Flash memory card CF8M 8M byte Compact Flash memory card CF16M 16M byte Compact Flash memory card CF32M 32M byte Compact Flash memory card CF48M 48M byte Compact Flash memory card

CF64M 64M byte Compact Flash memory card CF80M 80M byte Compact Flash memory card CF128M 128M byte Compact Flash memory card CFREADER Compact Flash r eader/ writer unit t hat plug s int o the print er

port of a PC. CF100-EKIT Ejector for the Compact Flash socket CF100-IDECA Optional IDE cable to connect the CF100 to the TP400.

Length 120mm. EC586-IDECA Optional IDE data cable to connect the CF100 to the

TP400

TABLE D6 - COMPACT FLASH ACCESSORIES

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DSP TP400 PC, TP104-plus, 104-plus Reference Manual

Specifications and Main Features

Frequently Asked Questions

User Manual