The DLP-USB245R is DLP Design’s smallest USB-to-parallel FIFO interface module and
utilizes the popular FT245R IC with FTDIChip-ID™ feature from FTDI. In addition to enabling
standard USB-to-FIFO designs, both asynchronous and synchronous bit-bang interface modes
are also available.
The DLP-USB245R is available in a lead-free, RoHS-compliant, compact 18-pin, 0.1-inch
standard DIP footprint.
• Ambient Temperature (Power Applied) -40 to +85°C
• VCC Supply Voltage -0.5V to +6.00V
• DC Input Voltage: Inputs -0.5V to VCC + 0.5V
• DC Input Voltage: High-Impedance Bidirectionals -0.5V to VCC + 0.5V
• DC Output Current: Outputs 24mA
D.C. CHARACTERISTICS (AMBIENT TEMPERATURE: -40 TO 85°C)
• VCC Operating-Supply Voltage 4.0 - 5.25V
• VCCIO Operating-Supply Voltage 4.0 - 5.25V
• Operating Supply Current 15mA (Normal Operation)
• Operating Supply Current 100uA USB Suspend
1.0 GENERAL DESCRIPTION
The DLP-USB245M provides an easy, cost-effective method of transferring data to/from a
peripheral and a host at up to 8 million bits (1 megabyte) per second. Its simple, FIFO-like
design makes it easy to interface to any microcontroller or microprocessor via I/O ports.
To send data from the peripheral to the host computer, simply write the byte-wide data into the
module when TXE# is low. If the (128-byte) transmit buffer fills up or is busy storing the
previously-written byte, the device takes TXE# high in order to stop further data from being
written until some of the FIFO data has been transferred over USB to the host.
When the host sends data to the peripheral over USB, the device will take RXF# low to let the
peripheral know that at least one byte of data is available. The peripheral then reads the data
until RXF# goes high, thereby indicating that no more data is available to be read.
By using FTDI’s Virtual COM Port drivers, the peripheral looks like a standard COM port to the
application software. Commands to set the baud rate are ignored; the device always transfers
data at its fastest rate regardless of the application’s baud-rate setting. The latest versions of
the drivers are available for download from DLP Design’s website at www.dlpdesign.com.
RD# Active Pulse Width
RD# to RD# Pre-Charge Time
RD# Active to Valid Data*
Valid Data Hold Time from RD# Inactive*
RD# Inactive to RXF#
RXF# Inactive After RD Cycle
TXE#
WR
TTIIMMEE DDEESSCCRRIIPPTTIIOONN
T7
T8
T9
T10
T11
T12
*Load = 30pF
WR Active Pulse Width
WR to WR Pre-Charge Time
Valid Data Setup to WR Falling Edge*
Valid Data Hold Time from WR Inactive*
WR Inactive to TXE#
TXE# Inactive After WR Cycle