Notes: 2. Type refers to whether or not pin is an Input, Output, Input/Output or Power supply pin.
Type
(Note 2)
Description
Adjust input (for dc output current control)
Connect to REF to set 100% output current.
Drive with dc voltage (125mV<V
< 1.25V) to adjust output current from 10% to 100%
ADJ
of set value. The ADJ pin has an internal clamp that limits the internal node to less than
3V. This provides some failsafe should they get overdriven
Internal 1.25V reference voltage output
Temperature Adjust input for LED thermal current control
Connect thermistor/resistor network to this pin to reduce output current above a preset
temperature threshold.
Connect to REF to disable thermal compensation function. (See section on thermal
control.)
Shaping capacitor for feedback control loop
Connect 330pF ±20% capacitor from this pin to ground to provide loop compensation
Operation status output (analog output)
Pin is at 4.5V (nominal) during normal operation.
Pin switches to a lower voltage to indicate specific operation warnings or fault
conditions. (See section on STATUS output.)
Status pin voltage is low during shutdown mode
Signal ground (Connect to 0V)
Power ground - Connect to 0V and pin 8 to maximize copper area
Not Connected internally – recommend connection to pin 7, (PGND), to maximize PCB
copper for thermal dissipation
Not Connected internally – recommend connection pin 10 (GATE) to permit wide copper
trace to gate of MOSFET
Gate drive output to external NMOS transistor – connect to pin 9
Auxiliary positive supply to internal switch gate driver
At V
< 8V; a bootstrap circuit is recommended to ensure adequate gate drive voltage
IN
(see Applications section)
At V
> 8V; connect to VIN
IN
>24V; to reduce power dissipation, V
At V
IN
auxiliary power supply (see Applications section). Decouple to ground with capacitor
close to device (see Applications section)
Input supply to device 5V to 60V
Decouple to ground with capacitor close to device (refer to Applications section)
Current monitor input. Connect current sense resistor between this pin and V
The nominal voltage, V
, across the resistor is 218mV fixed in Buck mode and
SENSE
initially 225mV in Boost and Buck-Boost modes, varying with duty cycle.
Flag open drain output
Pin is high impedance during normal operation
Pin switches low to indicate a fault, or warning condition
Digital PWM output current control
Pin driven either by open Drain or push-pull 3.3V or 5V logic levels.
Drive with frequency higher than 100Hz to gate output ‘on’ and ‘off’ during dimming
control.
The device enters standby mode when PWM pin is driven with logic low level for more
than 15ms nominal (Refer to application section for more details)
Gain setting input
Used to set the device in Buck mode or Boost, Buck-boost modes and to control the
sense voltage in Boost and Buck-boost modes
Connect to ADJ pin for Buck mode operation
For Boost and Buck-boost modes, connect to resistive divider from ADJ to SGND. The
GI divider is required to compensate for duty cycle gating in the internal feedback loop
(see Application section). The GI pin has an internal clamp that limits the internal
less than 3V. This provides some failsafe should it become overdriven.
Exposed paddle. Connect to 0V plane for electrical and thermal management
Absolute Maximum Ratings (Voltages to GND Unless Otherwise Stated) (Note 3)
Symbol Parameter Rating Unit
VIN
V
AUX
V
ISM
V
V
I
V
V
V
Current monitor sense voltage (VIN-V
SENSE
GATE
GATE
FLAG
, V
, V
PWM
PWM
ADJ
TADJ
, VGI,
TJ
TST
Stresses greater than the 'Absolute Maximum Ratings' specified above, may cause permanent damage to the device. These are stress ratings only; functional
operation of the device at these or any other conditions exceeding those indicated in this specification is not implied. Device reliability may be affected by
exposure to absolute maximum rating conditions for extended periods of time.
Semiconductor devices are ESD sensitive and may be damaged by exposure to ESD events. Suitable ESD precautions should be taken when handling and
transporting these devices.
ZXLD1371
Document number: DS35436 Rev. 1 - 2
Input supply voltage -0.3 to 65 V
Auxiliary supply voltage -0.3 to 65 V
Current monitor input relative to GND -0.3 to 65 V
ISM
)
-0.3 to 5 V
Gate driver output voltage -0.3 to 20 V
Gate driver continuous output current 18 mA
Flag output voltage -0.3 to 40 V
Other input pins -0.3 to 5.5 V
Maximum junction temperature 150 °C
TJ
GI Gain setting ratio for boost and buck-boost modes
Notes: 3. For correct operation SGND and PGND should always be connected together.
4. Measured on “High Effective Thermal Conductivity Test Board" according to JESD51.
5. Device starts up above 5.4V and as such the minimum applied supply voltage has to be above 5.4V (plus any noise margin). The ZXLD1371 will,
however, continue to function when the input voltage is reduced from ≥ 8V down to 5.0V.
When operating with input voltages below 8V the output current and device parameters may deviate from their normal values; and is dependent
on power MOSFET switch, load and ambient temperature conditions. To ensure best operation in Boost and Buck-boost modes with input
voltages, V
Performance in Buck mode will be reduced at input voltages (V
6. V
not be applied to V
V
7. The device contains circuitry to control the switching frequency to approximately 400kHz. The maximum and minimum operating frequency is not
tested in production.
Auxiliary supply voltage range (Note 6)
AUX
Differential input voltage
External dc control voltage applied to ADJ pin to
ADJ
adjust output current
Reference external load currentREF sourcing current 1mA
Recommended switching frequency range (Note 7) 300 1000 kHz
Temperature adjustment (T
Recommended PWM dimming frequency range
PWM pulse width in dimming mode PWM input high or low 0.002 10 ms
PWM pin high level input voltage 2 5.5 V
PWM pin low level input voltage 0 0.4 V
) input voltage range
ADJ
(Note 5) Reduced performance
operation
VIN-V
, with 0 V
ISM
ADJ
2.5
DC brightness control mode
from 10% to 100%
0
5.08.0
0450mV
0.125 1.25V
V
REF
To achieve 1000:1 resolution 100 500 Hz
To achieve 500:1 resolution 100 1000Hz
Operating Junction Temperature Range -40 125 °C
0.20 0.50
, between 5.0 and 8V a suitable boot-strap network on V
IN
can be driven from a voltage higher than V
AUX
IN
.
in the absence of a voltage at VIN. V
AUX
Ratio= VGI/V
pin is recommended.
AUX
, V
) below 8V. – a boot-strap network cannot be implemented in buck mode.
IN
to provide higher efficiency at low V
IN
AUX
can also be operated at a lower voltage than VIN to increase efficiencies at high
AUX
ADJ
voltages, but to avoid false operation; a voltage should
boost modes selection (Note 9)
IGI GI input current (Note 9)
I
PWM
t
PWMoff
T
SDH
T
SDL
PWM input current
PWM pulse width
(to enter shutdown state)
Thermal shutdown upper threshold
(GATE output forced low)
Thermal shutdown lower threshold
(GATE output re-enabled)
1.25V
ADJ
V
= 5.0V
ADJ
V
= 1.25V
ADJ
V
1.25V
GI
V
= 5.0V
GI
V
= 5.5V
PWM
PWM input low 10 15 25 ms
Temperature rising. 150 ºC
Temperature falling. 125 ºC
100 nA
5 µA
0.8 V
100 nA
5 µA
36 100 µA
V
High-Side Current Monitor (Pin ISM)
I
ISM
V
SENSE_acc
V
SENSE-OC
Notes: 8. UVLO levels are such that all ZXLD1371 will function above 5.4V for rising supply voltages and function down to 5V for falling supply voltages.
9. The ADJ and GI pins have an internal clamp that limits the internal
Input Current
Accuracy of nominal V
voltage
Over-current sense threshold voltage 300 350 375 mV
overdriven.
SENSE
threshold
Measured into ISM pin V
= 1.25V
V
ADJ
node to less than 3V. This provides some failsafe should those pins get
Electrical Characteristics (cont.)(Test conditions: V
SymbolParameter Conditions Min Typ Max Units
Output Parameters
V
FLAGL
I
FLAGOFF
V
STATUS
R
STATUS
Driver output (PIN GATE)
V
GATEH
FLAG pin low level output voltageOutput sinking 1mA 0.5V
FLAG pin open-drain leakage current
V
FLAG
Normal operation4.24.54.8
Out of regulation (V
(Note 11)
STATUS Flag no-load output voltage
(Note 10)
VIN under-voltage (V
Switch stalled (tON or t
Over-temperature (TJ > 125°C)
Excess sense resistor current
(V
SENSE
Output impedance of STATUS outputNormal operation 10 k
High level output voltage
No load Sourcing 1mA
(Note 12)
= 40V
> 0.32V)
IN
= V
= 12V, TA = 25°C, unless otherwise specified.)
AUX
1µA
out of range)
SHP
< UVLO)
IN
OFF
> 100µs)
3.33.63.9
3.33.63.9
3.33.63.9
1.51.82.1
0.60.91.2
10 11 V
V
V
GATEL
V
GATECL
I
GATE
Low level output voltage
High level GATE CLAMP voltage
Dynamic peak current available during
rise or fall of output voltage
Sinking 1mA, (Note 13)
V
= V
= V
IN
I
GATE
AU X
= 1mA
ISM
= 18V
Charging or discharging gate of
external switch with QG = 10nC and
400kHz
0.5 V
12.8 15 V
±300 mA
Time to assert ‘STALL’ flag and
t
STALL
warning on STATUS output
GATE low or high 100 170 µs
(Note 14)
LED Thermal control circuit (T
V
TADJH
V
TADJL
I
TADJ
Notes: 10. In the event of more than one fault/warning condition occurring, the higher priority condition will take precedence.
For more information see the Application Information section about Flag/Status levels.
11. Flag is asserted if V
12. GATE is switched to the supply voltage V
it exceeding 15V.
13. GATE is switched to PGND by an NMOS transistor
14. If t
grounded internally and the SHP pin is switched to its nominal operating voltage, before operation is allowed to resume. Restart cycles will be
repeated automatically until the operating conditions are such that normal operation can be sustained. If t
remain off until normal operation is possible.
Upper threshold voltage
Lower threshold voltage
T
For example ‘Excessive coil current’ and ‘Out of regulation’ occurring together will produce an output of 0.9V on the STATUS pin.
These STATUS pin voltages apply for an input voltage to V
therefore may not report the correct status. For 5.4V < V
Buck-boost modes an over-current status may be indicated when operating at high boost ratios – this due to the feedback loop increasing
the sense voltage.
pin Input currentV
ADJ
SHP
exceeds t
ON
, the device will force GATE low to turn off the external switch and then initiate a restart cycle. During this phase, ADJ is
STALL
) parameters
ADJ
< 1.5V or V
SHP
> 2.5V
AUX
Onset of output current reduction
falling)
(V
TADJ
Output current reduced to <10% of
set value (V
= 1.25V
TADJ
of 7.5V < VIN < 60V. Below 7.5V the STATUS pin voltage levels reduce and
IN
< 7.5V the flag pin still reports any error by going low. At low VIN in Boost and