Halogen and Antimony Free. “Green” Device (Note 3)
Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.
PGND 7 P Power ground - Connect to 0V and pin 8 to maximize copper area
N/C 8 -
N/C 9
GATE 10 O Gate drive output to external NMOS transistor – connect to pin 9
V
AUX
VIN
ISM 13 I
FLAG 14 O
PWM 15 I
GI 16 I
EP PAD P Exposed paddle. Connect to 0V plane for electrical and thermal management
Note: 4. Type refers to whether or not pin is an Input, Output, Input/Output or power supply pin.
11 P
12 P
ZXLD1370
Document number: DS32165 Rev. 5 - 2
Type
(Note 4)
Function
Adjust input (for dc output current control).
Connect to REF to set 100% output current.
Drive with dc voltage (125mV<V
The ADJ pin has an internal clamp that limits the internal
failsafe should they get overdriven.
Temperature Adjust input for LED thermal current control.
Connect thermistor/resistor network to this pin to reduce output current above a preset temperature
threshold.
Connect to REF to disable thermal compensation function. (See section on thermal control.)
Shaping capacitor for feedback control loop.
Connect 100pF ±20% capacitor from this pin to ground to provide loop compensation.
Operation status output (analog output)
Pin is at 4.5V (nominal) during normal operation.
Pin switches to a lower voltage to indicate specific operation warnings or fault conditions. (See section
on STATUS output.)
Status pin voltage is low during shutdown mode.
Not Connected internally – recommend connection to pin 7, (PGND), to maximize PCB copper for
thermal dissipation
Not Connected internally – recommend connection pin 10 (GATE) to permit wide copper trace to gate
of MOSFET
Auxiliary positive supply to internal switch gate driver.
Connect to V
to application section for more details)
Decouple to ground with capacitor close to device (refer to Applications section)
Input supply to device (6V to 60V).
Decouple to ground with capacitor close to device (refer to Applications section)
Current monitor input. Connect current sense resistor between this pin and V
The nominal voltage across the resistor is 225mV
Flag open drain output.
Pin is high impedance during normal operation
Pin switches low to indicate a fault, or warning condition
Digital PWM output current control.
Pin driven either by open Drain or push-pull 3.3V or 5V logic levels.
Drive with frequency higher than 100Hz to gate output ‘on’ and ‘off’ during dimming control.
The device enters standby mode when PWM pin is driven with logic low level for more than 15ms
nominal (Refer to application section for more details)
Gain setting input.
Used to set the device in Buck mode or Boost, Buck-boost modes
Connect to ADJ in Buck mode operation
For Boost and Buck-boost modes, connect to resistive divider from ADJ to SGND. This defines the ratio
of switch current to LED current (see application section). The GI pin has an internal clamp that limits
the internal
, or auxiliary supply from 6V to 15V supply to reduce internal power dissipation (Refer
IN
node to less than 3V. This provides some failsafe should they get overdriven
www.diodes.com
< 2.5V) to adjust output current from 10% to 200% of set value.
Absolute Maximum Ratings (Note 5) (Voltages to GND, unless otherwise specified.)
Symbol Parameter Rating Unit
VIN
V
AUX
V
ISM
V
SENSE
V
GATE
I
GATE
V
FLAG
V
, V
PWM
ADJ
, VGI
V
TADJ
TJ
TST
Stresses greater than the 'Absolute Maximum Ratings' specified above, may cause permanent damage to the device. These are stress ratings only; functional
operation of the device at these or any other conditions exceeding those indicated in this specification is not implied. Device reliability may be affected by exposure to
absolute maximum rating conditions for extended periods of time.
Semiconductor devices are ESD sensitive and may be damaged by exposure to ESD events. Suitable ESD precautions should be taken when handling and
transporting these devices.
Input Supply Voltage Relative to GND -0.3 to +65 V
Auxiliary Supply Voltage Relative to GND -0.3 to +65 V
Current Monitor Input Relative to GND -0.3 to +65 V
Current Monitor Sense Voltage (VIN-V
Gate Driver Output Voltage -0.3 to +20 V
ISM
)
-0.3 to +5 V
Gate Driver Continuous Output Current 18 mA
Flag Output Voltage -0.3 to 40 V
,
Other Input Pins -0.3 to +5.5 V
Maximum Junction Temperature 150 °C
Storage Temperature -55 to +150 °C
Package Thermal Data
Thermal Resistance Package Typical Unit
Junction-to-Ambient,
(Note 6)
JA
Junction-to-Case, JC
Notes: 5. For correct operation SGND and PGND should always be connected together.
6. Measured on High Effective Thermal Conductivity Test Board" according JESD51.
GI Gain setting ratio for boost and buck-boost modes
Notes: 7. Device starts up above 6V and as such the minimum applied supply voltage has to be above 6.5V (plus any noise margin). The ZXLD1370 will, however, continue to function when the input voltage is reduced from 8V down to 6.3V.
When operating with input voltages below 8V the output current and device parameters may deviate from their normal values; and is dependent on
power MOSFET switch, load and ambient temperature conditions. To ensure best operation in Boost and Buck-Boost modes with input voltages, V
between 6.3 and 8V a suitable boot-strap network on V
Performance in Buck mode will be reduced at input voltages (V
8. V
not be applied to V
9. The device contains circuitry to control the switching frequency to approximately 400kHz. The maximum and minimum operating frequency is not
tested in production.
Input supply voltage range
Auxiliary supply voltage range (Note 8)
Current sense monitor input range 6.3 60 V
Differential input voltage
External dc control voltage applied to ADJ
pin to adjust output current
Reference external load current REF sourcing current 1 mA
Recommended switching frequency range
(Note 9)
Temperature adjustment (T
) input voltage range
ADJ
Recommended PWM dimming frequency range
PWM pulse width in dimming mode PWM input high or low 0.002 10 ms
PWM pin high level input voltage 2 5.5 V
PWM pin low level input voltage 0 0.4 V
Operating Junction Temperature Range -40 125 °C
can be driven from a voltage higher than VIN to provide higher efficiency at low VIN voltages, but to avoid false operation; a voltage should
AUX
in the absence of a voltage at VIN.
AUX
= +25°C, unless otherwise specified.)
A
Normal operation 8
Reduced performance operation
(Note 7)
Normal operation 8
Reduced performance operation
(Note 7)
V
VIN-VISM
, with 0 V
ADJ
DC brightness control mode
from 10% to 200%
300 1000 kHz
0
To achieve 1000:1 resolution 100 500 Hz
To achieve 500:1 resolution 100 1000 Hz
Ratio = V
pin is recommended.
AUX
, V
) below 8V. – a boot-strap network cannot be implemented in buck mode.
Notes: 10. The ADJ and GI pins have an internal clamp that limits the internal node to less than 3V. This provides some failsafe should those pins get overdriven.
11. Initial sense voltage in Boost and Buck-Boost modes at maximum duty cycle.
ZXLD1370
Document number: DS32165 Rev. 5 - 2
Under-Voltage detection threshold
Normal operation to switch disabled
Under-Voltage detection threshold
Switch disabled to normal operation
Quiescent current into VIN
Quiescent current into V
AUX
Standby current into VIN.
Standby current into V
Internal reference voltage No load 1.237 1.250 1.263 V
Change in reference voltage with output
current
Reference voltage line regulation
Reference temperature coefficient +/-50 ppm/°C
External dc control voltage applied to ADJ pin
to adjust output current (Note 8)
ADJ input current (Note 10)
AUX
.
GI Voltage threshold for boost and buck-boost
modes selection (Note 8)
Notes: 12. In the event of more than one fault/warning condition occurring, the higher priority condition will take precedence. E.g. ‘Excessive coil current’ and
‘Out of regulation’ occurring together will produce an output of 0.9V on the STATUS pin. The voltage levels on the STATUS output assume the
Internal regulator to be in regulation and V
minimum value of 6V.
13. Flag is asserted if V
14. GATE is switched to the supply voltage V
internally to prevent it exceeding 15V.
15. GATE is switched to PGND by an NMOS transistor
16. If t
grounded internally and the SHP pin is switched to its nominal operating voltage, before operation is allowed to resume. Restart cycles will be
repeated automatically until the operating conditions are such that normal operation can be sustained. If t
until normal operation is possible.
ZXLD1370
Document number: DS32165 Rev. 5 - 2
FLAG pin low level output voltage Output sinking 1mA 0.5 V
FLAG pin open-drain leakage current
STATUS Flag no-load output voltage
(Note 12)
Output impedance of STATUS output Normal operation 10 k
High level output voltage
Low level output voltage Sinking 1mA, (Note 15) 0.5 V
High level GATE CLAMP voltage
Dynamic peak current available during rise
or fall of output voltage
Time to assert ‘STALL’ flag and
warning on STATUS output
(Note 16)
) parameters
ADJ
Upper threshold voltage
Lower threshold voltage
T
pin Input current V
ADJ
<2.5V or V
exceeds t
ON
SHP
, the device will force GATE low to turn off the external switch and then initiate a restart cycle. During this phase, ADJ is
STALL
SHP
= V
IN
<=V
ADJ
>3.5V
for low values of V
AUX
=12V, TA = +25°C, unless otherwise specified.)
AUX
V
FLAG
=40V
1 µA
Normal operation 4.2 4.5 4.8
Out of regulation (V
(Note 13)
VIN under-voltage (V
Switch stalled (tON or t
Over-temperature (TJ > +125°C)
Excess sense resistor current
(V
> 0.32V)
SENSE
No load Sourcing 1mA
(Note 14)
V
= V
AU X
= 1mA
= V
IN
I
GATE
Charging or discharging gate of external
switch with Q
G
out of range)
SHP
< 5.6V)
IN
> 100µs)
OFF
= 18V
ISM
= 10nC and 400kHz
3.3 3.6 3.9
3.3 3.6 3.9
3.3 3.6 3.9
1.5 1.8 2.1
0.6 0.9 1.2
10 11 V
12.8 15.0 V
±300 mA
GATE low or high 100 170 µs
Onset of output current reduction
(V
falling)
TADJ
Output current reduced to <10% of set
value (V
TADJ
. A reduction of the voltage on the STATUS pin will occur when the voltage on VIN is near the