Diodes ZABG6002 User Manual
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ZABG6002
LOW POWER 6 STAGE FET LNA AND MIXER BIAS CONTROLLER
Summary
The ZABG6002 is a programmable low power depletion mode FET bias and mixer controller intended primarily for
satellite Low Noise Blocks (LNBs). Designed to provide system flexibility the ZABG6002 can be programmed to bias
six low noise amplifier (LNA) stages or four LNA and two active mixer stages, allowing the ZABG6002 to be used in
several system designs.
Combining advanced IC process and packaging techniques, the ZABG6002 operates with minimal current over a
wide supply voltage. The small package and reduced component count minimizes the PCB area whilst enhancing
overall LNB reliability.
Features
• Six stage FET bias controller, two configurable as
mixer stages
• Operating range of 3.0V to 8.0V
• Amplifier FET drain voltages set at 2.0V, mixer
drain voltage set at 0.25V
• Amplifier FET drain current selectable from 0 to
15mA, mixer current from 0 to 7.5mA
• Switchable FET’s for power management
• FET drain voltages and currents held stable over
temperature and V
variations
CC
• FETs protected against overstress during powerup and power-down.
• Internal negative supply generator allowing single
supply operation (available for external use)
• Low quiescent supply current, 1.6mA typical
• Low external component count
Applications
• Twin LNB’s
• Quad LNB’s
• US LNB’s
• Microwave links
• PMR and Cellular telephone systems
Pin Assignments
1
1
G2
G2
G2
D3
D3
D3
G3
G3
G3
1
G
G
G
d
d
d
n
n
n
G
G
G
D1
D1
D1
Cnb1
Cnb1
Cnb1
D1
D1
G1
G1
D2
D2
G2
G2
D3
D3
G3
G3
RcalM
RcalM
Gnd
Gnd
Cnb1
Cnb1
Vcc
Vcc
Vcc
Cnb2
Cnb2
Cnb2
1
1
QFN2044
4
4
4
D
D
D
G4
G4
G4
D5D2
D5D2
D5D2
G5
G5
G5
D6
D6
D6
G6
G6
G6
Rcal1RcalM
Rcal1RcalM
Rcal1RcalM
ub
ub
ub
s
s
s
C
Rcal2
C
Rcal2
C
Rcal2
QSOP20
CsubCsubCsub
Vcc
Vcc
D4
D4
G4
G4
D5
D5
G5
G5
D6
D6
G6
G6
Rcal1
Rcal1
Rcal2
Rcal2
CsubCnb2
CsubCnb2
Twin LNB System Diagrams
Vertical
Vertical
ZXHF
ZABG
ZABG
6002
6002
Horizontal
Horizontal
ZABG6002
Document number: DS32078 Rev. 1 - 2
ZXHF
5002
5002
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Left
Left
Right
Right
ZABG
ZABG
6002
6002
2x2 MUX
2x2 MUX
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ZLNB
ZLNB
102
102
May 2010
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ZABG6002
Device Description
The ZABG series of devices are designed to meet the bias requirements of GaAs and HEMT FETs commonly used
in satellite receiver LNBs with a minimum of external components whilst operating from a minimal voltage supply
and using minimal current.
The ZABG6002 has six FET bias stages that can be user programmed to provide either a two plus four
arrangement of amplifier FET stages or a two plus two arrangement of amplifier FET stages along with two active
mixer FET stages. Programming of the FET bias stage arrangement and the operating currents of each FET group
is achieved by resistors connected to the Rcal1, Rcal2 and RcalM pins, allowing input FETs to be biased for
optimum noise, amplifier FETs for optimum gain and mixer FETs (if used) for optimum conversion gain. Amplifier
FETs can be operated at currents in the range 0 to 15mA and mixer FETs in the range 0.5 to 7.5mA.
Drain voltages of amplifier stages are set at 2.0V and mixer stages at 0.3V. The drain supplies are current limited to
approximately 5% above the operating currents set by their associated Rcal resistors.
As an additional feature the Rcal pins can also be used as logic inputs to disable pairs of FETs as part of a power
management scheme or simply an alternative to LNA switching. Driven to a logic high (>3.0V), the inputs disable
their associated FET bias stages by switching gate feeds to -2.5V and drain feeds open circuit.
Depletion mode FETs require a negative voltage bias supply when operated in grounded source circuits. The
ZABG6002 includes an integrated low noise switched capacitor DC-DC converter generating a regulated output of -
2.5V to allow single supply operation. To aid efficiency and 3.3V systems the ZABG6002 has been design to used
with supply rails of 3.3V to 8V
It is possible to use less than the devices full complement of FET bias controls, unused drain and gate connections
can be left open circuit without affecting operation of the remaining bias circuits.
To protect the external FETs the circuits have been designed to ensure that, under any conditions including power
up/down transients, the gate drive from the bias circuits cannot exceed -3V. Additionally each stage has its own
individual current limiter. Furthermore if the negative rail experiences a fault condition, such as overload or short
circuit, the drain supply to the FETs will shut down avoiding excessive current flow.
The ZABG6002 is available in the 20 pin 4mm x 4mm QFN or QSOP20 package.
Device operating temperature is -40°C to 85°C to suit a wide range of environmental conditions.
ZABG6002
Document number: DS32078 Rev. 1 - 2
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Maximum Ratings
Parameter Rating Unit
Supply Voltage -0.6 to +10 V
Supply Current 100 mA
Power Dissipation 600 mW
Operating Temperature Range -40 to +85 °C
Storage Temperature Range -40 to 150 °C
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ZABG6002
Electrical Characteristics Measured at T
R
= 68K (setting I
CALM
to 5mA) unless otherwise stated
D3/6
= 25°C, VCC = 3.3V (Note 1), R
AMB
CAL1
= R
CAL2
= 36K (setting I
D1/2/4/5
to 10mA),
Parameter Conditions Symbol Min. Typ. Max. Unit
Operating Voltage Range VCC 3.0 8.0 V
I
= 0 ICC 1.6 4.0 mA
Supply Current
Substrate Voltage
Oscillator Frequency F
D1-6
I
= 10mA, no R
D1-6
I
= 0 V
CSUB
I
= -200uA V
CSUB
CALM
I
CC(L)
CSUB
CSUB(L)
OSC
62 64 mA
-3.0 -2.65 -2.0 V
-2.55 -2.0 V
150 260 600 kHz
Gate Characteristics
Gate (G1 to G6, resistor R
not present)
CALM
Current Range IG -100 +500 uA
Voltage Low ID = 12mA, IG = -10uA V
Voltage High ID = 8mA, IG = 0 V
I
Voltage Disabled
(*1)
= 0, IG = -10uA,
D
RCAL1-2
= 3.0V
V
-3.0 -2.5 -2.0 V
G(L)
0 0.7 1.0 V
G(H)
V
-3.0 -2.5 -2.0 V
G(DIS)
Gate (G3 and G6, resistor R
CALM
present)
Current Range IG -100 +500 uA
Voltage Low ID = 6mA, IG = -10uA V
Voltage High ID = 4mA, IG = 0 V
I
Voltage Disabled
(*1)
= 0, IG = -10uA,
D
= V
V
RCAL2
RCALM
3.0V
-3.0 -2.5 -2.0 V
G(L)
0 0.7 1.0 V
G(H)
V
-3.0 -2.5 -2.0 V
G(DIS)
Drain Characteristics
Drain (D1 to D6, resistor R
M not present)
CAL
Current Range ID 0 15 mA
Current Operating
Current Disabled
(*1)
V
Voltage Operating ID = 10mA V
Standard Application
Circuit
= 0, V
D
= 3.0V I
RCAL
I
8 10 12 mA
D(OP)
10 uA
D(DIS)
1.8 2.0 2.2 V
D(OP)
ZABG6002
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ZABG6002
Electrical Characteristics (Cont.) Measured at T
10mA), R
= 68K (setting I
CALM
to 5mA) unless otherwise stated
D3/6
= 25°C, VCC = 3.3V (Note 1), R
AMB
CAL1
= R
CAL2
= 36K (setting I
D1/2/4/5
to
Parameter Conditions Symbol Min. Typ. Max. Unit
Drain Characteristics
Drain (D3 and D6, resistor R
M present)
CAL
Current Range IDM 0.5 7.5 mA
Current Operating
Current Disabled
(*1)
Voltage Operating ID = 5mA V
Standard Application
Circuit
V
R
D
CALM
= 0, V
not present
RCAL
= 3.0V,
I
4 5 6 mA
DM(OP)
I
10 uA
DM(DIS)
0.25 0.3 0.35 V
DM(OP)
R
(1 and 2)
CAL
Disable Threshold
Input Current V
(*1)
V
= 3.0V I
RCAL
RCAL(DIS)
RCAL(DIS)
1.8 2.7 3.0 V
1.7 10 uA
R
CALM
Disable Threshold
R
Range R
CALM
(*1)
R
CALM(DIS)
CALM
1.5M 3.3M 5.0M
39k 390k
Ω
Ω
Voltage and Temperature dependence (R
delta ID vs VCC V
delta ID vs TOP T
delta VD vs VCC V
delta VD vs TOP T
M not present)
CAL
= 3.3 to 8.0V dID/dVCC 1.2 %/V
CC
= -40°C to +85°C dID/dTOP 0.05 %/°C
OP
= 3.3 to 8.0V dVD/dVCC 0.05 %/V
CC
= -40°C to +85°C dVD/dTOP 50 ppm/°C
OP
Output Noise
C
Drain Voltage
Gate Voltage
Notes: 1. To disable FET stages 3 and 6, pin R
further information.
2. The characteristics are measured using up to three external reference resistors, R
Resistor R
is present, resistor R
3. The negative bias voltages are generated on-chip using an internal oscillator. Two external capacitors, C
this purpose.
4. The QFN2044 exposed pad must either be connected to Csub or left open circuit.
5. Noise voltage measurements are made with FETs and gate and drain capacitors of value 10nF in place. Noise voltages are not measured in production.
6. ESD sensitive, handling precautions are recommended.
sets the drain current of FETs 1 and 4. If R
CAL1
sets the drain currents of FETs 2 and 5 and R
CAL2
GATE-GND
C
DRAIN-GND
C
GATE-GND
C
DRAIN-GND
must be set to 3V or above and pin R
CAL2
ZABG6002
Document number: DS32078 Rev. 1 - 2
= 10nF,
= 10nF
= 10nF,
= 10nF
is not present, resistor R
CALM
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sets the drain currents of FETs 3 and 6.
CALM
4 of 12
V
V
should be open circuit. See applications section for
CALM
, R
CAL1
0.02 Vpk-pk
D(NOISE)
0.005 Vpk-pk
G(NOISE)
and R
CAL2
sets the drain currents of FETs 2, 3, 5 and 6. If R
CAL2
, wired from pins R
CALM
and C
NB
CAL1/2/M
of value 47nF are required for
SUB
to ground.
© Diodes Incorporated
CALM
May 2010
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