The AUR9718B is a high efficiency step-down
DC-DC voltage converter. The chip operation is
optimized by peak-current mode architecture with
built-in synchronous power MOSFET switchers.
The oscillator and timing capacitors are all built-in
providing an internal switching frequency of 1.5MHz
that allows the use of small surface mount inductors
and capacitors for portable product implementations.
Additional features including Soft Start (SS), Under
Voltage Lock Out (UVLO), Thermal Shutdown
Detection (TSD) and short circuit protection are
integrated to provide reliable product applications.
The device is available in adjustable output voltage
versions ranging from 0.8V to V
voltage range is from 2.7V to 5.5V, and is able to
deliver up to 2.5A.
Thermal Resistance (Junction to Ambient, Simulation) θJA
Operating Junction Temperature TJ
Operating Temperature TOP
Storage Temperature T
ESD (Human Body Model) V
ESD (Machine Model) VMM
Note 1: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. These are stress ratings only, and functional operation of the device at these or any other conditions
beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to “Absolute
Maximum Ratings” for extended periods may affect device reliability.
The basic AUR9718B application circuit is shown in
Figure 34.
1. Inductor Selection
For most applications, the value of inductor is chosen
based on the required ripple current with the range of
1.0µH to 6.8µH.
I−
1
=∆
V
OUTL
Lf
×
The largest ripple current occurs at the highest input
voltage. Having a small ripple current reduces the ESR
loss in the output capacitor and improves the efficiency.
The highest efficiency is realized at low operating
frequency with small ripple current. However, larger
value inductors will be required. A reasonable starting
point for ripple current setting is △I
maximum ripple current stays below a specified
value, the inductor should be chosen according to the
following equation:
V
[
=
L
OUT
MAXIf
∆×
L
The DC current rating of the inductor should be at
least equal to the maximum output current plus half
the highest ripple current to prevent inductor core
saturation. For better efficiency, a lower
DC-resistance inductor should be selected.
2. Capacitor Selection
The input capacitance, CIN, is needed to filter the
trapezoidal current at the source of the top MOSFET.
To prevent large ripple voltage, a low ESR input
capacitor sized for the maximum RMS current must
be used. The maximum RMS capacitor current is
given by:
deviations do not much relieve. The selection of C
is determined by the Effective Series Resistance
(ESR) that is required to minimize output voltage
ripple and load step transients, as well as the amount
of bulk capacitor that is necessary to ensure that the
control loop is stable. The output ripple, △V
determined by:
[
ESRIV
LOUT
+∆≤∆
1
8
××
]
Cf
OUT
The output ripple is the highest at the maximum input
voltage since △I
increases with input voltage.
L
3. Load Transient
A switching regulator typically takes several cycles to
respond to the load current step. When a load step
occurs, V
to △I
resistance of output capacitor. △I
charge or discharge C
signal used by the regulator to return V
immediately shifts by an amount equal
OUT
×ESR, where ESR is the effective series
LOAD
also begins to
LOAD
generating a feedback error
OUT
OUT
steady-state value. During the recovery time, V
can be monitored for overshoot or ringing that would
indicate a stability problem.
4. Output Voltage Setting
The output voltage of AUR9718B can be adjusted by a
resistive divider according to the following formula:
OUT
VV
REF
R
1
R
2
V
The resistive divider senses the fraction of the output
voltage as shown in Figure 30.
FB
AUR9718B
GND
VOUT
R1
R2
Figure 30. Setting the Output Voltage
13
R
1
+×=+×=
R
2
OUT
, is
OUT
to its
OUT
)1(8.0)1(
Page 14
+×=
Data Sheet
1.5MHz, 2.5A, Step-down DC-DC Converter AUR9718B
Application Information (Continued)
the V
and this effect will be more serious at higher
5.Short Circuit Protection
When AUR9718B output node is shorted to GND, as
V
drops under 0.4V, the chip will enter soft-start to
FB
protect itself; when short circuit is removed, and V
FB
rises over 0.4V, the chip will enter normal operation
again. If AUR9718B reaches OCP threshold while
short circuit, it will enter soft-start cycle and last until
the current drops under OCP threshold.
6.
Efficiency Considerations
The efficiency of switching regulator is equal to the
output power divided by the input power times 100%.
It is usually useful to analyze the individual losses to
determine what is limiting efficiency and which
change could produce the largest improvement.
Efficiency can be expressed as:
Efficiency=100%-L1-L2-…..
Where L1, L2, etc. are the individual losses as a
percentage of input power.
Although all dissipative elements in the regulator
produce losses, two major sources usually account for
most of the power losses: V
2
I
R losses. The VIN quiescent current loss dominates
the efficiency loss at very light load currents and the
2
R loss dominates the efficiency loss at medium to
I
heavy load currents.
6.1 The V
quiescent current loss comprises two
IN
parts: the DC bias current as given in the electrical
characteristics and the internal MOSFET switch gate
charge currents. The gate charge current results from
switching the gate capacitance of the internal power
MOSFET switches. Each cycle the gate is switched
from high to low, then to high again, and the packet
of charge, dQ moves from V
resulting dQ/dt is the current out of V
typically larger than the internal DC bias current. In
continuous mode,
QQfI+×=
Where Q
and QN are the gate charge of power
P
PMOSFET and NMOSFET switches. Both the DC
bias current and gate charge losses are proportional to
In continuous mode, the average output current
flowing through the inductor is chopped between
power PMOSFET switch and NMOSFET switch.
Then, the series resistance looking into the SW pin is
a function of both PMOSFET R
NMOSFET R
DS(ON)N
resistance and the duty cycle
DS(ON)P
and
(D):
Therefore, to obtain the I
R
and multiply the result by the square of the
L
()()
2
R losses, simply add RSW to
NONDSPONDSSW
)(
DRDRR
−×
1
average output current.
Other losses including C
and C
IN
ESR dissipative
OUT
losses and inductor core losses generally account for
less than 2% of total additional loss.
7. Thermal Characteristics
In most applications, the part does not dissipate much
heat due to its high efficiency. However, in some
conditions when the part is operating in high ambient
temperature with high R
resistance and high
DS(ON)
duty cycles, such as in LDO mode, the heat
dissipated may exceed the maximum junction
temperature. To avoid the part from exceeding
maximum junction temperature, the user should do
some thermal analysis. The maximum power
dissipation depends on the layout of PCB, the thermal
resistance of IC package, the rate of surrounding
airflow and the temperature difference between
junction and ambient.
8. Input Over Voltage Protection
When the input voltage of AUR9718B exceeds V
the IC would enter the mode of Input Over Voltage
Protection. It will be shutdown and there will be no
output voltage. As the input voltage goes down below
5.5V, the IC would leave input OVP mode and the
output voltage will be recovered.
OVP
9. PC Board Layout Considerations
When laying out the printed circuit board, the
following checklist should be used to optimize the
,
Page 15
Data Sheet
1.5MHz, 2.5A, Step-down DC-DC Converter AUR9718B
Application Information (Continued)
performance of AUR9718B.
1. The power traces, including the GND trace, the SW
trace and the VIN trace should be kept direct, short and
wide.
2. Put the input capacitor as close as possible to the
VIN_SW, VIN_A and GND pins.
3. The FB pin should be connected directly to the
feedback resistor divider.
4. Keep the switching node SW away from the
sensitive FB pin and the node should be kept small
area.
The following is an example of 2-layer PCB layout as
shown in Figure 32 and Figure 33 for reference.