Diodes AUR9707 User Manual

Dual High-efficiency PWM Step-down DC-DC Converter with OVP AUR9707

Data Sheet

General Description

The AUR9707 is a high efficiency step-down DC-DC voltage converter. The chip operation is optimized using constant frequency, peak-current mode architecture with built-in synchronous power MOSFET switchers and internal compensators to reduce external part counts. It is automatically switching between the normal PWM mode and LDO mode to offer improved system power efficiency covering a wide range of loading conditions.

The oscillator and timing capacitors are all built-in providing an internal switching frequency of 1.5MHz that allows the use of small surface mount inductors and capacitors for portable product implementations. Additional features included Soft Start (SS), Under Voltage Lock Out (UVLO), Input Over Voltage Protection (IOVP) and Thermal Shutdown Detection (TSD) are integrated to provide reliable product applications.

The device is available in adjustable output voltage versions ranging from 1V to 3.3V, and is able to deliver up to 1A.

The AUR9707 is available in WDFN-3×3-12 package.

Features

• Dual Channel High Efficiency Buck Power Converter

• Low Quiescent Current

• Output Current: 1A

• Adjustable Output Voltage from 1V to 3.3V

• Wide Operating Voltage Range: 2.5V to 5.5V

•

Built-in Power Switches for Synchronous

Rectification with High Efficiency

• Feedback Voltage: 600mV

• 1.5MHz Constant Frequency Operation

• Automatic PWM/LDO Mode Switching Control

• Thermal Shutdown Protection

• Low Drop-out Operation at 100% Duty Cycle

• No Schottky Diode Required

• Internal Input Over Voltage Protection

Applications

• Mobile Phone, Digital Camera and MP3 Player

• Headset, Radio and Other Hand-held Instrument

• Post DC-DC Voltage Regulation

• PDA and Notebook Computer

WDFN-3×3-12

Figure 1. Package Type of AUR9707

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Data Sheet

Dual High-efficiency PWM Step-down DC-DC Converter with OVP AUR9707

Pin Configuration

D Package

(WDFN-3×3-12)

Pin 1 Dot

by Marking

1

2

3

Exposed

4

5

6

Pad

12

11

10

9

8

7

Figure 2. Pin Configuration of AUR9707 (Top View)

Pin Description

Pin Number Pin Name Function

1 VIN2 Power supply input of channel 2

2 LX2 Connection from power MOSFET of channel 2 to inductor

3, 9 GND

4 FB1 Feedback voltage of channel 1

5, 11 NC1,NC2 No internal connection (floating or connecting to GND)

6 EN1 Enable signal input of channel 1, active high

7 VIN1 Power supply input of channel 1

8 LX1 Connection from power MOSFET of channel 1 to inductor

10 FB2 Feedback voltage of channel 2

12 EN2 Enable signal input of channel 2, active high

This pin is the GND reference for the NMOSFET power stage. It must be connected to the system ground

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Data Sheet

Dual High-efficiency PWM Step-down DC-DC Converter with OVP AUR9707

Functional Block Diagram

FB1, FB2

EN 1, EN2

6, 12

Generator

4, 1 0

Bandgap

Reference

Over Current

Comparator

Bias

Saw-tooth Generator

Oscillator

+

Soft

Start

-

+

Error

Amplifier

-

+

Figure 3. Functional Block Diagram of AUR9707

+

-

Modulator

Over Voltage

Comparator

Control

Logic

Reverse Inductor

Current Comparator

Thermal

Shutdown

Current Sensing

Buffer &

Dead Time

Control

Logic

VIN 1, VIN 2

-

+

7, 1

3, 9

GND

8, 2

LX1, LX 2

Ordering Information

AUR9707 A

Circuit Type

A: Adjustable Output

5

Package

WDFN-3×3-12 -40 to 80°C AUR9707AGD 9707A Tape & Reel

Temperature

Range

Part Number Marking ID Packing Type

BCD Semiconductor's Pb-free products, as designated with "G" in the part number, are RoHS compliant and green.

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Package D: WDFN-3×3-12 G: Green

Data Sheet

Dual High-efficiency PWM Step-down DC-DC Converter with OVP AUR9707

Absolute Maximum Ratings (Note 1)

Parameter Symbol Value Unit

Supply Input Voltage VIN

Enable Input Voltage VEN

Output Voltage V

V

IN1-VIN2

Power Dissipation (On PCB, TA=30°C) PD Thermal Resistance (Junction to Ambient, Simulation) θJA Thermal Resistance (Junction to Case, Simulation) θJC

Operating Junction Temperature TJ

Operating Temperature TO

Storage Temperature TS

ESD (Human Body Model) V

ESD (Machine Model) VMM

Note 1: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to “Absolute Maximum Ratings” for extended periods may affect device reliability. Note 2:│V

Voltage (Note 2) VDF

IN1-VIN2

│voltage difference can not exceed 0.3V, otherwise, the chip will be damaged.

OUT

HBM

0 to 6.5

-0.3 to VIN+0.3

-0.3 to 0.3

2.31

41

4.2

160

-40 to 85

-55 to 150

2000

200

V

W

°C/W

°C

V

Recommended Operating Conditions

Parameter Symbol Min Max Unit

Supply Input Voltage VIN 2.5 5.5 V

Junction Temperature Range TJ -20 125 °C

Ambient Temperature Range TA -40 80 °C

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Data Sheet

Dual High-efficiency PWM Step-down DC-DC Converter with OVP AUR9707

Electrical Characteristics

VIN=3.6V, V

Parameter Symbol Conditions Min Typ Max Unit

Input Voltage Range VIN 2.5 5.5 V

=2.5V, V

OUT

=0.6V, L=2.2µH, CIN=4.7µF, C

REF

=10µF, TA=25°C, I

OUT

MAX

=1A.

Shutdown Current I Regulated1Feedback

Voltage Regulated Output Voltage Accuracy

∆V

Peak Inductor Current

Oscillator Frequency f

PMOSFET RON R

NMOSFET RON R

Input DC Bias Current

LX Leakage Current ILX

V

OFF

For Adjustable Output Voltage 0.585 0.6 0.615 V

V

FB

OUT/VOUT

I

OSC

ON(P)

ON(N)

I

V

PK

V

VIN=3.6V, I

VIN=2.5V, I

S

=0 0.1 1 µA

EN

=2.5V to 5.5V;

V

IN

=0 to 1A

I

OUT

=3V, VFB=0.5V 1.5 A

IN

=3.6V 1.2 1.5 1.8 MHz

IN

=200mA 0.28 Ω

OUT

=200mA 0.38 Ω

OUT

VIN=3.6V, I

=2.5V, I

V

IN

=5V, VEN=0V, VLX=0V or

V

IN

=200mA 0.25

OUT

=200mA

OUT

5V

-3 3 %

0.35

0.01 0.1 µA

µA

Feedback Current IFB 30 nA Input Over Voltage

Protection

6 V

V

LOVP

EN Leakage Current IEN 0.01 0.1 µA EN High-level Input

Voltage EN Low-Level Input Voltage Under Voltage Lock Out

VIN=2.5V to 5.5V 1.5 V

V

EN_H

V

EN_L

=2.5V to 5.5V 0.6 V

IN

1.8 V

Hysteresis 0.1 V

Thermal Shutdown TSD 150 °C

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Data Sheet

Dual High-efficiency PWM Step-down DC-DC Converter with OVP AUR9707

Typical Performance Characteristics

Figure 4. Efficiency vs. Output Current Figure 5. Efficiency vs. Load Current

Figure 6. Efficiency vs. Load Current Figure 7. LDO Mode Efficiency vs. Load Current

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Data Sheet

Dual High-efficiency PWM Step-down DC-DC Converter with OVP AUR9707

Typical Performance Characteristics (Continued)

Figure 8. Output Voltage vs. Output Current

Figure 10. Output Voltage vs. Output Current Figure 11. Frequency vs. Temperature

Figure 9. UVLO Threshold vs. Temperature

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Data Sheet

Dual High-efficiency PWM Step-down DC-DC Converter with OVP AUR9707

Typical Performance Characteristics (Continued)

Figure 12. Output Current Limit vs. Input Voltage Figure 13. Output Voltage vs. Temperature

Figure 14. Frequency vs. Input Voltage Figure 15. Output Current Limit vs. Temperature

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Data Sheet

Dual High-efficiency PWM Step-down DC-DC Converter with OVP AUR9707

Typical Performance Characteristics (Continued)

V

200mV/div

OUT

VLX

2V/div

VEN

2V/div

Time 400ns/div

Figure 16. Temperature vs. Load Current Figure 17. Waveform of VIN=4.5V, V

=1.5V, L=2.2µH

OUT

V

EN

2V/div

V

OUT

1V/div

V

LX

2V/div

Time 200µs/div

Figure 18. Soft Start

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Data Sheet

Dual High-efficiency PWM Step-down DC-DC Converter with OVP AUR9707

Application Information

The basic AUR9707 application circuit is shown in Figure 23, external components selection is determined by the load current and is critical with the selection of inductor and capacitor values.

1. Inductor Selection

For most applications, the value of inductor is chosen based on the required ripple current with the range of

2.2µH to 4.7µH.

I −

1

=∆

V

OUTL

Lf

×

The largest ripple current occurs at the highest input voltage. Having a small ripple current reduces the ESR loss in the output capacitor and improves the efficiency. The highest efficiency is realized at low operating frequency with small ripple current. However, larger value inductors will be required. A reasonable starting point for ripple current setting is △I maximum ripple current stays below a specified value, the inductor should be chosen according to the following equation:

=

L

V

[

OUT

MAXIf

∆×

L

The DC current rating of the inductor should be at least equal to the maximum output current plus half the highest ripple current to prevent inductor core saturation. For better efficiency, a lower DC-resistance inductor should be selected.

2. Capacitor Selection

The input capacitance, CIN, is needed to filter the trapezoidal current at the source of the top MOSFET. To prevent large ripple voltage, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by:

It indicates a maximum value at V I

RMS=IOUT

commonly used for design because even significant

Feb. 2012 Rev. 1. 1 BCD Semiconductor Manufacturing Limited

II

×=

OMAXRMS

/2. This simple worse-case condition is

V

OUT

)1(

V

IN

=40%I

L

V

1][

)(

V

OUT

−

MAXV

IN

VVV

)]([ −

OUTINOUT

IN

=2V

IN

1

2

MAX

]

)(

OUT

. For a

, where

qw

deviations do not much relieve. The selection of C is determined by the Effective Series Resistance (ESR) that is required to minimize output voltage ripple and load step transients, as well as the amount of bulk capacitor that is necessary to ensure that the control loop is stable. Loop stability can be also checked by viewing the load step transient response as described in the following section. The output ripple, △V

, is determined by:

OUT

[

ESRIV

LOUT

+∆≤∆

8

1

××

]

Cf

OUT

The output ripple is the highest at the maximum input voltage since △I

increases with input voltage.

L

3. Load Transient

A switching regulator typically takes several cycles to respond to the load current step. When a load step occurs, V to △I resistance of output capacitor. △I charge or discharge C signal used by the regulator to return V

immediately shifts by an amount equal

OUT

×ESR, where ESR is the effective series

LOAD

also begins to

LOAD

generating a feedback error

OUT

steady-state value. During the recovery time, V can be monitored for overshoot or ringing that would indicate a stability problem.

4. Output Voltage Setting

The output voltage of AUR9707 can be adjusted by a resistive divider according to the following formula:

VV

REFOUT

R

1

R

2

V

The resistive divider senses the fraction of the output voltage as shown in Figure 19.

FB

VOUT

R1

R2

AUR9707

GND

Figure 19. Setting the Output Voltage

10

R

1

+×=+×=

R

2

OUT

to its

OUT

)1(6.0)1(

+×=

Data Sheet

Dual High-efficiency PWM Step-down DC-DC Converter with OVP AUR9707

Application Information (Continued)

5. Efficiency Considerations

The efficiency of switching regulator is equal to the output power divided by the input power times 100%. It is usually useful to analyze the individual losses to determine what is limiting efficiency and which change could produce the largest improvement. Efficiency can be expressed as:

Efficiency=100%-L1-L2-…..

Where L1, L2, etc. are the individual losses as a percentage of input power.

Although all dissipative elements in the regulator produce losses, two major sources usually account for most of the power losses: V

2

I

R losses. The VIN quiescent current loss dominates

the efficiency loss at very light load currents and the

2

I

R loss dominates the efficiency loss at medium to

heavy load currents.

5.1 The V

quiescent current loss comprises two

IN

parts: the DC bias current as given in the electrical characteristics and the internal MOSFET switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each cycle the gate is switched from high to low, then to high again, and the packet of charge, dQ moves from V resulting dQ/dt is the current out of V typically larger than the internal DC bias current. In

continuous mode,

QQfI +×=

Where Q

and QN are the gate charge of power

P

PMOSFET and NMOSFET switches. Both the DC bias current and gate charge losses are proportional to the V input voltages.

5.2 I

resistance, R

and this effect will be more serious at higher

IN

2

R losses are calculated from internal switch

and external inductor resistance RL.

SW

In continuous mode, the average output current flowing through the inductor is chopped between power PMOSFET switch and NMOSFET switch. Then, the series resistance looking into the LX pin is a function of both PMOSFET R

quiescent current and

IN

to ground. The

IN

)(

NPGATE

and NMOSFET

DS(ON)

that is

IN

R

Therefore, to obtain the I R

resistance and the duty cycle (D):

DS(ON)

)(

DRDRR

−×

() ()

2

R losses, simply add RSW to

and multiply the result by the square of the

L

1

NONDSPONDSSW

average output current.

Other losses including C

and C

IN

ESR dissipative

OUT

losses and inductor core losses generally account for

less than 2 % of total additional loss.

6. Thermal Characteristics

In most applications, the part does not dissipate much heat due to its high efficiency. However, in some conditions when the part is operating in high ambient temperature with high R

resistance and high

DS(ON)

duty cycles, such as in LDO mode, the heat dissipated may exceed the maximum junction temperature. To avoid the part from exceeding maximum junction temperature, the user should do some thermal analysis. The maximum power dissipation depends on the layout of PCB, the thermal resistance of IC package, the rate of surrounding airflow and the temperature difference between junction and ambient.

7. PCB Layout Considerations

When laying out the printed circuit board, the following checklist should be used to optimize the performance of AUR9707.

1) The power traces, including the GND trace, the LX

trace and the VIN trace should be kept direct, short and wide.

2) Put the input capacitor as close as possible to the

VIN and GND pins.

3) The FB pin should be connected directly to the

feedback resistor divider.

4) Keep the switching node, LX, away from the

sensitive FB pin and the node should be kept small area.

5) The following is an example of 2-layer PCB layout

as shown in Figure 21 and Figure 22 for reference.

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Data Sheet

Dual High-efficiency PWM Step-down DC-DC Converter with OVP AUR9707

Application Information (Continued)

Figure 20. The Evaluation Board Schematic

Figure 21. Top Layer Layout Figure 22. Bottom Layer Layout

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Data Sheet

Dual High-efficiency PWM Step-down DC-DC Converter with OVP AUR9707

Typical Application

R

Note 3:

When R2 or R4=300kΩ to 60 kΩ, the I

-6

3×10

and 6×10-6 for component selection.

VV

REFOUT

1

)1(

+×= ; )

R

2

Figure 23. Typical Appl ication Circuit of AUR9707

V

OUT1

or V

OUT2

(V)

R1 or R3(kΩ) R2 or R4(kΩ)

3.3 240 53 20 2.2

2.5 240 75 20 2.2

1.8 240 120 20 2.2

1.5 240 160 20 2.2

1.2 240 240 20 2.2

R

3

1(VV

REF2OUT

or IR3=2µA to 10µA, and R1×C1 or R3×C2 should be in the range between

R2

+×=

R

4

C1 or C2(pF)

L1 or L2(µH)

1.0 240 300 20 2.2

Table 1. Component Guide

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Data Sheet

Dual High-efficiency PWM Step-down DC-DC Converter with OVP AUR9707

Mechanical Dimensions

WDFN-3×3-12 Unit: mm(inch)

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