Diodes AP7215 User Manual

AP7215

600mA CMOS LDO

Features

• Very Low Dropout Voltage

• Low Current Consumption: Typ. 50μA

• Output Voltage: 3.3V

• Guaranteed 600mA Output

• Input Range up to 5.5V

• Current Limit Protection

• Stable with either electrolytic capacitor or low-ESR

MLCC (multi-layer ceramic capacitor) Low
Temperature Coefficient

• SOP-8L and SOT89-3L: Available in “Green” Molding
Compound (No Br, Sb)

• Lead Free Finish / RoHS Compliant (Note 1)

Applications

• HD/Blue-Ray DVD & MP3/4 Players

• Mobile Handsets and Smart Phones

• Digital Still Camera

• Hand-Held Computers

Ordering Information

General Description

The AP7215 low-dropout linear regulator operates from a 3.3V to

5.5V supply and delivers a guaranteed 600mA continuous load
current.

The high-accuracy output voltage is preset to an internally
trimmed voltage. An active-low open-drain reset output remains
asserted for at least 20ms (TYP) after input voltage rises above
the reset threshold.

The space-saving SOP-8L and SOT89-3L package are suitable
for “pocket” and hand-held applications.

AP7215 - 33 X G - 13

Output voltage

33 : 3.3V

Package

S : SOP-8L

G : Green

PackingGreen

13 : Tape & Reel

Y : SOT89-3L

Device

Package

Code

Packaging

(Note 2)

Quantity Part Number Suffix

13” Tape and Reel

AP7215-33SG-13 S SOP-8L 2500/Tape & Reel -13
AP7215-33YG-13 Y SOT89-3L 2500/Tape & Reel -13

Notes: 1. EU Directive 2002/95/EC (RoHS). All applicable RoHS exemptions applied, see EU Directive 2002/95/EC Annex Notes.

2. Pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be on our website at

http://www.diodes.com/datasheets/ap02001.pdf

.

AP7215 Rev. 1 1 of 11 FEBRUARY 2009

www.diodes.com © Diodes Incorporated

Pin Assignments

(1) SOP-8L (2) SOT89-3L

( Top View )

NC

1

OUT

NC

V

2

3

4

IN

VR

Pin Descriptions

Pin Name

NC 1, 3 , 5 - No Connection

VR

2 3 Voltage Output

OUT

VIN 4 2 Supply Voltage

VD

6 - VD Output Voltage (Reset Output)

OUT

GND 7 1 Ground

EN 8 - Enable (VR

SOP-8L SOT89-3L

Pin No.

EN

8

GND

7

VD

6

OUT

5

NC

OUT

( Top View )

Tab is V

Description

ON/OFF)

AP7215

600mA CMOS LDO

3

2

1

IN

VR

OUT

V

IN

GND

AP7215 Rev. 1 2 of 11 FEBRUARY 2009

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)

Block Diagram

AP7215

600mA CMOS LDO

Off

VD

EN

On

OUT

Enable

Bandgap

1.2V

+

R3

-

ERROR

AMP

+

Current

Limit

R1

R2

-

VD Comp.

R4

Absolute Maximum Ratings

Symbol Parameter Rating Unit

ESD HBM Human Body Model ESD Protection 2 KV

ESD MM Machine Model ESD Protection 350 V

VIN Input Voltage +6 V

VR

Output Voltage GND - 0.3 ~ VIN+ 0.3 V

OUT

T

Maximum Junction Temperature 150 ºC

J(MAX

PD Power Dissipation

SOP-8L 1.2 W
SOT89-3L 0.79 W

Recommended Operating Conditions

Symbol Parameter Min Max Unit

VIN Input Voltage 3.3 5.5 V

I

Output Current 0 600 mA

OUT

TJ Operating Junction Temperature Range -40 125 ºC

TA Operating Ambient Temperature -40 85 ºC

V

IN

VR

GND

OUT

AP7215 Rev. 1 3 of 11 FEBRUARY 2009

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AP7215

600mA CMOS LDO

Electrical Characteristics

= 25°C, C

(T

A

Symbol Parameter Test Conditions Min Typ. Max Unit

I

I

VR

ΔVR

/ΔTA/VR

OUT

VDO Dropout Voltage

I

I

I

SHORT

ΔVR

OUT

ΔVR

PSRR

VEH

V

IVD

Notes: 3. Test conditions for SOP-8L, SOT89-3L: Device mounted on FR-4 substrate, single sided PC board, 2oz copper, with minimum recommended

AP7215 Rev. 1 4 of 11 FEBRUARY 2009

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= 1µF, C

IN

Quiescent Current I

CCQ

Standby Current

STBY

OUT

OUT

Current Limit V

LIMIT

Output Voltage
Accuracy
VR

OUT

Coefficient

Maximum Output
Current

= 1µF, VIN=5.0V, V

OUT

Temperature

OUT

= VIN, unless otherwise noted)

EN

= 0mA - 50 80 μA

OUT

V

= GND

EN

= 5.0V

V

IN

= 30mA, V

I

OUT

=-40°C to 85°C, I

T

A

= 30mA 60 100 mV

I

OUT

I

= 100mA 100 250 mV

OUT

= 5.3V 600 mA

V

IN

= 5.3V 750 mA

IN

= 5V 3.234 3.300 3.366 V

IN

= 30mA

OUT

15 30

±100

ppm /

μA

Short Circuit Current VIN= 5.3V 50 mA

/ΔVIN/VR

T

VEL Output OFF 0.25 V

OUT

OU

Line Regulation 4.3V ≤ V
Load Regulation 1mA ≤ I

Power Supply
Rejection

EN Input Threshold

≤ 5.5V, I

IN

≤ 100mA, V

OUT

= 4.3V+ 0.5Vp-pAC,

V

IN

I

= 50mA

OUT

= 30mA 0.01 ±0.2 %/V

OUT

= 5.3V 15 50 mV

IN

F= 1KHz 55 dB

Output ON 1.6 V

IEN Enable Pin Current -0.1 0.1 μA

VDF

HYS

VD

OUT

tRP VD

θ

JA

θ

JC

pad layout.

VIN Detection Voltage Detect VD
VDF Hysteresis
Range

Sink Current

OUT

Delay Time 10 20 40 ms

OUT

Thermal Resistance

Junction-to-Ambient

Thermal Resistance

Junction-to-Case

VD

OUT

VD

OUT

SOP-8L (Note 3) 124
SOT89-3L (Note 3) 173
SOP-8L (Note 3) 25
SOT89-3L (Note 3) 42

fall 3.83 3.91 3.98 V

OUT

= 0.5V, V
= 0.5V, V

= 2.0V

IN

= 3.0V

IN

V

x1.02

V

DF

DF

x1.05

20 mA

30

V

DF

x1.08

V

ºC/W
ºC/W

o

C

Typical Application

V

IN

AP7215

600mA CMOS LDO

U1

4

V

IN

VR

OUT

2

VR

OUT

C

IN

1uF

Timing Diagram

t

RP

20mSec-TYP.

V

HYS

VD

OUT

100K

AP7215

ON

6

VD

OUT

GND

EN

8

OFF

C

1uF

OUT

7

V

DF

V

IN

VD

OUT

EN

VR

OUT

AP7215 Rev. 1 5 of 11 FEBRUARY 2009

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Typical Performance Characteristics

AP7215

600mA CMOS LDO

Quiescent Current vs Input Voltage

90
80
70
60
50

(uA)

40

CCQ

I

30
20
10

0

3.0 3.5 4.0 4.5 5.0 5.5 6.0
(V)

V

IN

STBY

Delay Time vs Ambient Temperatu re

28
27
26
25
24
23
22

Delay Time (ms)

21
20

-40 -20 0 20 40 60 80 100 120
Ambient Temperatur e ( C)

(mV)

DO

V

Current Limit vs Ambient Temperature

960
940
920
900
880
860
840
820
800

Current Limit (mA)

780
760

-40 -20 0 20 40 60 80 100 120
Ambient Temperatu r e

(mA)

SHORT

I

Sta ndby Current vs Input Voltage

80
70
60
50

(uA)

40
30

I

20
10

0

3.0 3.5 4.0 4.5 5.0 5.5 6.0
V

(V)

IN

Dropout Voltage vs Out put Current

700
600
500
400
300
200
100

0

0 100 200 300 400 500 600 700

I

OUT

(mA)

Short Circuit Current vs Input Voltage

90
85
80
75
70
65
60
55
50

3.0 3.5 4.0 4.5 5.0 5.5 6.0
V

(V)

IN

AP7215 Rev. 1 6 of 11 FEBRUARY 2009

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Typical Performance Characteristics (Continued)

Load Transient Response

(V

=4.3V, I

IN

=10mA ~300mA)

OUT

(VIN=4.3V, I

AP7215

600mA CMOS LDO

Load Transient Response

=10mA ~600mA)

OUT

VR

VR

I

OUT

OUT

OUT

VIN

V

IN

V

IN

Load Transient Response

=5.5V, I

(V

IN

=10mA~300mA)

OUT

VR

VR

I

V

OUT

OUT

OUT

Load Transient Response

(VIN=5.5V, I

IN

=10mA~600mA)

OUT

I

I

OUT

OUT

AP7215 Rev. 1 7 of 11 FEBRUARY 2009

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Application Note

AP7215

600mA CMOS LDO

Input Capacitor

A 1μF ceramic capacitor is recommended to connect between V
and GND pins to de couple input po wer supply glitc h and noise.
The amount of the capacitance may be increased without limit.
A lower ESR (Equivalent Series Resistance) capacitor allows the
use of less capac itance, while higher ESR type r equires more
capacitance. This input capacitor must be located as close as
possible to the device to assure input stability and less noise. For
PCB layout, a wide copper trace is required for both V
GND.

and

IN

Suggested Input Capacitance
Vendor Capacitance Type Series
TAIYO YUDEN 1μF Ceramic LMK212B

Output Capacitor

The output capacitor is required to stabilize and help the transien t
response of the LDO. The AP72 15 i s des ign ed to ha ve e xcel lent
transient response for most applications with a small amount of
output capacitance. The AP7215 is stable with any small ceramic
output capacitors of 1.0μF or higher value, and the temperature
coefficients of X7R or X5R type. Additional capacitance helps to
reduce undershoot and overshoot during transient. For
PCB layout, the output capacitor must be placed as close as
possible to VR
possible.

and GND pins, and keep the leads as short as

OUT

Suggested Output C apacitance
Vendor Capacitance Type Series
TAIYO YUDEN 1μF Ceramic LMK212B

Suggested Resistance
Vendor Capacitance Type
YAGEO SMD FR-SK

ENABLE/SHUTDOWN Operation

IN

The AP7215 is turned on by setting the EN pin high, and is turned
off by pulling it low. If this feature is not used, the EN pin should
be tied to V
ensure proper operation, the signal source used to drive the

pin to keep the regulator output on at all time. To

IN

EN pin must be able to swing above and below the specified
turn-on/off voltage thresholds listed in the Electrical

OUT

and VEL.

EH

Characteristics section under V

VR

VD

OUT

EN=0 0V Φ
EN=1 3.3V Φ

Current Limit Protection

When output current at VR
threshold, the current limit protection will be triggered and clamp

pin is higher than current limit

OUT

the output current to approximately 750mA to prevent
over-current and protect the regulator from damage due to
overheating.

Short circuit protection

When VR
200mV, short circuit protection will be triggered and clamp the

pin is shorted to GND or VR

OUT

voltage is less than

OUT

output current to approximately 50mA.

(reset output)

VD

OUT

---Open-Drain Active-Low reset output--­In general, VD
AP7215 microprocessor (μP) supervisory circuitry asserts a

is pulled up by a resisto r (100K Ω) to VIN. The

OUT

guaranteed logic-low reset during power-up and power-down.
Reset is asserted when V
remain asserted for at least t
threshold.

is below the reset threshold and

IN

after VIN rises above the reset

RP

As long as V
logic "0". When V
asserted after a 20ms time delay defined by t

is lower than the reset threshold, VD

IN

becomes higher than V

IN

RP

, a logic "1" is

HYS

remains at

OUT

AP7215 Rev. 1 8 of 11 FEBRUARY 2009

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Marking Information

(1) SOP-8L

AP7215

600mA CMOS LDO

( Top View )

Part Number

(2) SOT89-3L

Logo

8

AP7215-33
YY

WW X

5

: Year : 08, 09,10~

YY

WW : Week : 01~52; 52

X

X

represents 52 and 53 week

: Internal Code

G : Green

41

( Top View )

XX : Identification code

X X
Y W

X

Y : Year : 0~9

W

: Week : A~Z : 1~26 week;

a~z : 27~52 week;

z represents 52 and 53 week

: Internal code

1 32

X

A~Z : Green

Device Package type Identification Code

AP7215Y SOT89-3L N8

AP7215 Rev. 1 9 of 11 FEBRUARY 2009

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Package Information (All Dimensions in mm)

(1) Package Type: SOP-8L

0.254

3.85/3.95

5.90/6.10

0.10/0.20

Detail "A"

0.62/0.82

Gauge Plane
Seating Plane

AP7215

600mA CMOS LDO

7°~9°

1.27typ

4.85/4.95

8x-0.60

6x-1.27

8x-1.55

Land Pattern Recommendation

(Unit: mm)

(2) Package Type: SOT89-3L

1.45/1.55
Typ 1.50

80(2x)

4.40/4.60 Typ 4.50

0.3/0.5

5.4

1.40/1.75
Typ 1.60

2.90/3.10
Typ 3.00

0.35max.

0.15/0.25

1.30/1.50

1.75max.

7°~9°

45°

Detail "A"

0°/8°

1.7

2.7

3.94/4.25

2.35/2.60 Typ 2.48

1.20

0.80/

Land Pattern Recommendation (Unit: mm)

0.9

0.4

50(2x)

1.5

1.9

1.3

Typ 1.50

1.40/1.60

0.36/0.48
Typ 0.42

0.41/0.53
Typ 0.47

0.36/0.48
Typ 0.42

0.35/0.43
Typ 0.39

AP7215 Rev. 1 10 of 11 FEBRUARY 2009

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AP7215

600mA CMOS LDO

IMPORTANT NOTICE

Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes without further
notice to any product herein. Diodes Incorporated does not assume any liability arising out of the application or use of any product described herein; neither
does it convey any license under its patent rights, nor the rights of others. The user of products in such applications shall assume all risks of such use and will
agree to hold Diodes Incorporated and all the companies whose products are represented on our website, harmless against all damages.

LIFE SUPPORT

Diodes Incorporated products are not authorized for use as critical components in life support devices or systems without the expressed written approval of the
President of Diodes Incorporated.

AP7215 Rev. 1 11 of 11 FEBRUARY 2009

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