The 74LVC1G58 is a single 3-input positive configurable multiple
function gate with a standard push-pull output. The output state is
determined by eight patterns of 3-bit input. The user can chose the
logic functions AND, OR, NAND, NOR, XOR, inverter or non-inverting
buffer. All inputs can be connected to ground or V
The device is designed for operation with a power supply range of
1.65V to 5.5V. The inputs are tolerant to 5.5V allowing this device to
be used in a mixed voltage environment. The device is fully specified
for partial power down applications using IOFF. The IOFF circuitry
disables the output preventing damaging current backflow when the
device is powered down. The user is reminded that the device can
simulate several types of logic gates, but may respond differently due
to the Schmitt action at the inputs.
NEW PRODUCT
Features
as required.
CC
74LVC1G58
CONFIGURABLE MULTIPLE-FUNCTION GATE
Pin Assignments
(Top View)
1
IN1
2
GND
3
IN0
SOT26
(Top View)
IN1
1
GND
2
3
IN0
X2-DFN1410-6
Applications
6
IN2
CC
GND
5
V
4
Y
6
IN2
V
5
CC
4
Y
(Top View)
1
IN1
2
3
IN0
SOT363
(Top View)
1
IN1
2
GND
3
IN0
X2-DFN1010-6
6
IN2
5
V
CC
4
Y
6
IN2
5
V
CC
4
Y
• Wide Supply Voltage Range from 1.65V to 5.5V
• ± 24mA Output Drive at 3.3V
• CMOS low power consumption
• IOFF Supports Partial-Power-Down Mode Operation
• Inputs accept up to 5.5V
• ESD Protection Exceeds JESD 22
200-V Machine Model (A115-A)
2000-V Human Body Model (A114-A)
• Latch-Up Exceeds 100mA per JESD 78, Class II
• Range of Package Options
• SOT26, SOT363, DF1410, and DFN1010: Available in “Green”
Molding Compound (no Br, Sb)
2-Input AND Gate with A Input Inverted
2-Input NOR Gate with B input Inverted
Configuration 2
2-input NAND 1
2-input NAND with both inputs inverted 4
2-input AND with inverted input 2, 3
2-input NOR with inverted input 2, 3
2-input OR 4
2-input OR with both inputs inverted 1
2-input XOR 5
1-input Buffer 6
VI
VO Voltage applied to output in high impedance or I
VO
IIK Input Clamp Current VI < 0
IOK
IO
Continuous current through Vdd or GND ±100 mA
TJ
T
NEW PRODUCT
Notes: 4. Stresses beyond the absolute maximum may result in immediate failure or reduced reliability. These are stress values and device
operation should be within recommend values
STG
Supply Voltage Range -0.5 to 6.5 V
Input Voltage Range -0.5 to 6.5 V
state
OFF
Voltage applied to output in high or low state
Output Clamp Current -50 mA
Continuous output current ±50 mA
Operating Junction Temperature -40 to +150 °C
Storage Temperature -65 to +150 °C
.
-0.5 to 6.5 V
-0.3 to VCC +0.5
Recommended Operating Conditions (Note 5)
Symbol Parameter Min Max Unit
VCC
VI
VO
IOH
IOL
Δt/ΔV Input transition rise or fall rate
TA
Notes: 5. Unused inputs should be held at VCC or Ground.
Electrical Characteristics (All typical values are at V
Symbol Parameter Test Conditions
CI
Input Capacitance
θ
θ
Notes: 6. Test condition for SOT26, SOT363, X2-DFN1410-6 and X2-DFN1010-6: Device mounted on FR-4 substrate PC board, 2oz copper, with minimum
recommended pad layout.
Switching Characteristics
NEW PRODUCT
T
= -40°C to +85°C, CL = 30 or 50pF as noted (see Figure 1)
A
Parameter
T
= -40°C to +125°C, CL = 30 or 50pF as noted (see Figure 1)
A
Parameter
Thermal Resistance Junction-
JA
to-Ambient
Thermal Resistance Junction-
JC
to-Case
From
(Input)
tpd
tpd
Any Y 1.0 14.4 0.7 8.3 0.7 6.3 0.7 5.1 ns
From
(Input)
Any Y 1.0 18.0 0.7 10.4 0.7 7.9 0.7 6.4 ns
Operating Characteristics
T
= +25°C
A
Parameter
Cpd
Power dissipation
capacitance
74LVC1G58
Document number DS35126 Rev. 4 - 2
VI = V
SOT26
SOT363 371
X2-DFN1410-6
X2-DFN1010-6
SOT26
SOT363 143
X2-DFN1410-6
X2-DFN1010-6
Notes: 7. Pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be found on our website at
http://www.diodes.com/datasheets/ap02001.pdf.
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