Diodes 74HCT595 User Manual

Page 1
8-BIT SHIFT REGISTER WITH 8-BIT OUTPUT REGISTER
Description
The 74HCT595 is an high speed CMOS device that is designed to
be pin compatable with 74LS low power Schottky types.
An eight bit shift register accpets data from the serial input (DS)
on each positive transition of the shift register clock (STCP).
When asserted low the reset function (MR
values to zero and is indepent of all clocks.
Data from the input serial shift register is placed in the output
register with a rising pulse on the storages resister clock (SHCP).
With the output enable (OE
Q7 become active and present th
All registers capture data on rising edge and change output on the
Preliminary
falling edge. If both clocks are connected together the input shift
register is always one clock cycle ahead of the output register.
Features
• Supply Voltage Range from 4.5V to 5.5V
• Sinks or sources 8mA at V
• CMOS low power consumption
• Schmitt Trigger Action at All Inputs
• Inputs accept up to 6.0V
• ESD Protection Tested per JESD 22
Exceeds 200-V Machine Model (A115-A)
Exceeds 2000-V Human Body Model (A114-A)
Exceeds 1000-V Charged Device Model (C101C)
• Latch-Up Exceeds 250mA per JESD 78, Class II
• Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
• Halogen and Antimony Free. “Green” Device (Note 3)
) sets all shift register
ሻ asserted low the 3-state outputs Q0-
= 4.5V
CC
Pin Assignments
Applications
• General Purpose Logic
• Serial to Parallel Data conversion
• Capture and hold data for extended periods of time.
• Allow simple serial bit streams from a microcontroller to
control as many peripheral lines as needed.
• Wide array of products such as:
o Computer peripherals o Appliances o Industrial control
Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free,
"Green" and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000 ppm antimony compounds.
Click for Ordering Information
74HCT595
Document number: DS35493 Rev. 3 - 2
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Pin Descriptions
Functional Diagram
Pin Number Pin Name Description
1 Q1 Parallel Data Output 1
2 Q2 Parallel Data Output 2
3 Q3 Parallel Data Output 3
4 Q4 Parallel Data Output 4
5 Q5 Parallel Data Output 5
6 Q6 Parallel Data Output 6
7 Q7 Parallel Data Output 7
8 GND Ground
9 Q7S Serial Data Output
10 MR Master Reset Input
11 SHCP Shift Register Clock Input
12 STCP Storage Register Clock Input
Preliminary
13 OE Output Enable Input
14 DS Serial Data Input
15 Q0 Parallel Data Output 0
16 Vcc Supply Voltage
Logic Diagram
DS
SHCP
MR
STCP
OE
74HCT595
Document number: DS35493 Rev. 3 - 2
STAGE 0
DQ
FF0
CP
R
DQ
LATCH
CP
Q0
STAGES 1 TO 6
DQ
Q1 Q2
Q3Q5Q4
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Q6
STAGE 7
DQ
FF7
CP
R
DQ
LATCH
CP
Q7
Q7S
July 2013
© Diodes Incorporated
Page 3
Functional Description and Timing Diagram
Control Input Output
SHCP STCP OE MR DS Q7S Qn
X X L L
X ↑ L L
X X H L
↑ X L H
X ↑ L H
Preliminary
↑ ↑ L H
H=HIGH voltage state L=LOW voltage state ↑=LOW to HIGH transition X= don’t care – high or low (not floating) NC= No change Z= high-impedance state
L NC
L L Empty shift register transferred to storage register
L Z Shift register remains clear; All Q ouputs in Z state
Q6S NC
NC QnS
Q6S QnS
Low-level asserted on MR clears shift register
Storage register is unchanged
HIGH is shifted into first stage of Shift Register Contents of each
register shifted to next register
The content of Q6S has been shifted to Q7S and now appears on
device pin Q7S
Contents of shift register copied to storage register
With output now in active state, the storage resister contents
appear on Q outputs
Contents of shift register copied to output register then shift register
shifted.
Function
74HCT595
Document number: DS35493 Rev. 3 - 2
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Page 4
Absolute Maximum Ratings (Note 4) (@T
= +25°C°C, unless otherwise specified.)
A
Symbol Description Rating Unit
ESD HBM Human Body Model ESD Protection 2 kV
ESD CDM Charged Device Model ESD Protection 1 kV
ESD MM Machine Model ESD Protection 200 V
VCC
VI
Vo
IIK Input Clamp Current VI < -0.5V
IIK Input Clamp Current VI > Vcc +0.5V
IOK Output Clamp Current VO < -0.5V
IOK Output Clamp Current VO > VCC + 0.5V
IO
Preliminary
Note: 4. Stresses beyond the absolute maximum may result in immediate failure or reduced reliability. These are stress values, and device operation should be within recommend values.
ICC Continuous current through VCC or GND
I
Continuous current through VCC or GND
GND
TJ
T
STG
P
TOT
Supply Voltage Range -0.5 to +7.0 V
Input Voltage Range -0.5 to +7.0 V
Voltage applied to output in high or low state
Continuous output current
Operating Junction Temperature -40 to +150 °C
Storage Temperature -65 to +150 °C
Total Power Dissipation 500 mW
Q7 standard output +/- 25 mA
Qn bus driver outputs +/- 35 mA
-0.3 to VCC +0.5
Recommended Operating Conditions (Note 5) (@T
= +25°C°C, unless otherwise specified.)
A
Symbol Parameter Conditions Min Max Unit
VCC
VI
VO
t/V Input transition rise or fall rate VCC = 4.5V to 5.5V
TA
Note: 5. Unused inputs should be held at Vcc or Ground.
74HCT595
Document number: DS35493 Rev. 3 - 2
Supply Voltage
Input Voltage
Output Voltage Active Mode 0
Operating free-air temperature
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4.5 5.5 V
-40 125 °C
0 5.5 V
V
-20 mA
20 mA
-20 mA
20 mA
70 mA
-70 mA
VCC
100 ns/V
© Diodes Incorporated
V
July 2013
Page 5
Electrical Characteristics (@T
Symbol Parameter Test Conditions VCC
High-Level
V
IH
Input Voltage
Low-Level
VIL
Input Voltage
High-Level
Output Voltage
VOH
Preliminary
VOL
∆ICC
II
IOZ
ICC
Ci
Q7S output
Qn Bus
Outputs
Low-Level
Output Voltage
Q7S output
Qn Bus
Outputs
Input Current
OFF-state
output current
Supply Current
Additional
Supply Current
per Input
Input
Capacitance
Operating Characteristics (@T
Parameter
= +25°C°C, unless otherwise specified.)
A
= +25°C°C
T
A
Min Typ Max Min Max Min Max
4.5V to
5.5V
4.5V to
5.5V
I
= -20μA
OH
All outputs
I
= -4mA
OH
I
= -6.0mA
OH
I
= 20μA
OL
All outputs
I
= 4mA
OL
I
= 6.0mA
OL
=GND to
V
I
5.5V
4.5V 4.4 4.5
4.5V
4.5V
4.5V
4.5V
4.5V
5.5V
2.0
3.84 4.32
3.7 4.32
0 0.1
0.15 0.33
.016 0.33
±0.1
Qn internal high or
low.
V
=Vcc or Gnd
o
= GND or VCC
V
I
=0
I
O
V
= Vcc -2.1V
I
I
=0
O
V
= V
or GND
i
CC
5.5V
5.5V
4.5V to
5.5V
5.5V
= +25°C°C, unless otherwise specified.)
A
100 450
4 10
Test Conditions
0.8
± 5
8.0
T
= -40°C°C to
A
2.0
4.4
4.32
4.32
V
= 5V
CC
TYP
+85°C°C
0.8
0.1
0.33
0.33
± 1
± 5
80
450
10
Unit
TA = -40°C°C to
+125°C°C
2.0
4.4
3.7
3.7
0.8 V
0.1
0.4
0.4
± 1 μA
± 10 μA
160 μA
490 μA
10 pF
Unit
V
V
V
Cpd
Power dissipation
capacitance
74HCT595
Document number: DS35493 Rev. 3 - 2
f = 1 MHz all outputs switching-no load 42 pF
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Page 6
Switching Characteristics
Symbol /
Parameter
f
MAX
Maximum
Frequency
t
W
Pulse Width
Pins
SHCP or
STCP
SHCP
HIGH or
LOW
STCP
HIGH or
LOW
Test
Conditions
Figure 1 4.5V to 5.5V 30 52
Figure 1 4.5V to 5.5V 16 6
Figure 1 4.5V to 5.5V 16 5
= +25°C°C
T
V
CC
A
-40°C°C to
+85°C°C
Min Typ. Max Min Max Min Max
24
20
20
-40°C°C to
+125°C°C
20
24
24
Unit
MHz
ns
Preliminary
t
SU
Set-up Time
t
H
Hold Time
t
REC
Recovery Time
t
PD
Propagation
Delay
t
EN
Enable Time
t
DIS
Disable Time
74HCT595
Document number: DS35493 Rev. 3 - 2
MR LOW Figure 1 4.5V to 5.5V 20 8
DS to SHCP Figure 1 4.5V to 5.5V 16 5
SHCP to
STCP
Figure 1 4.5V to 5.5V 16 8
DS to SHCP Figure 1 4.5V to 5.5V 3 -2
to SHCP Figure 1 4.5V to 5.5V 10 -7
MR
SHCP to
Q7S
STCP to Qn
MR to Q7S
to Qn
OE
to Qn
OE
Figure 1
C
=50pF
L
Figure 1
=50pF
C
L
Figure 1
=50pF
C
L
Figure 1
=50pF
C
L
Figure 1
=50pF
C
L
4.5V to 5.5V
4.5V to 5.5V
4.5V to 5.5V
4.5V to 5.5V
4.5V to 5.5V
25 42
24 40
23 40
21 35
18 30
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25
20
20
3
13
53
50
50
44
38
30
24
24
3
15
© Diodes Incorporated
ns
ns
ns
ns
63 ns
60 ns
60 ns
53 ns
45 ns
July 2013
Page 7
Parameter Measurement Information
VCC
4.5V to 5.5V 3.0V 3ns 1.5V VCC/2 15pF, 50pF
Inputs
VI t
1/f
Preliminary
Input
t
M
V
MAX
W
TEST Vload
t
PLH/tPHL
t
V
PLZ/tPZL
t
r/tf
V
Input Output
PHZ/tPZH
M
C
L
l
V
M
V
0 V
Open
CC
GND
MR
rec
t
Voltage Waveform
Pulse Duration and Recovery Time
Voltage Waveform
Propagation Delay Times
Inverting and Non Inverting Outputs
Notes: A . Includes test lead and test apparatus capacitance. B. Output Waveform 1 depends on the internal Q Output Waveform 2 depends on the internal Q C. All pulses are supplied at pulse repetition rate ≤ 10 MHz D. Inputs are measured separately one transition per measurement E. t
PLH
and t
PHL
are the same as t
PD
Figure 1. Load Circuit and Voltage Waveforms
node being low and behaves in this manner based on OE pin.
N
node being high and behaves in this manner based on OE pin.
N
Voltage Waveform
Set-up and Hold Times
Voltage Waveform
Enable and Disable Times
74HCT595
Document number: DS35493 Rev. 3 - 2
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Ordering Information
Device Package Code
74HCT595S16-13 S16 SO-16 2500/Tape & Reel -13
74HCT595T16-13 T16 TSSOP-16 2500/Tape & Reel -13
Notes: 6. . The taping orientation is located on our website at http://www.diodes.com/datasheets/ap02007.pdf
Preliminary
Packaging
Quantity Part Number Suffix
7” Tape and Reel(Note 6)
Marking Information
(1) SO-16, TSSOP-16
Part Number Package
74HCT595S16 SO-16
74HCT595T16 TSSOP-16
74HCT595
Document number: DS35493 Rev. 3 - 2
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Preliminary
Package Outline Dimensions (All Dimensions in mm)
Please see AP02002 at http://www.diodes.com/datasheets/ap02002.pdf for latest version.
(1) Package Type: SO-16
B
D
e
A2
H
E
L
Detail ‘A’
A
C
A1
Detail ‘A’
Gauge Plane
Dim Min Max
SO-16
A 1.40 1.75 A1 0.10 0.25 A2 1.30 1.50
B 0.33 0.51
C 0.19 0.25
D 9.80 10.00
E 3.80 4.00
e 1.27 Typ H 5.80 6.20 L 0.38 1.27
Θ
0 8
All Dimensions in mm
(2) Package Type: TSSOP-16
E/2
E
A
Y
PIN 1
Ø0.760Depth0.050±0.02
A2
X
e
D
E1
b
C
SEATIN G PLANE
SEE DETAIL 'A'

L
Dim Min Max Typ
x)

R1
L2
R
GAUGE PLAN E
A1
L1
74HCT595
Document number: DS35493 Rev. 3 - 2
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TSSOP-16
A - 1.08
A1 0.05 0.15
-
-
A2 0.80 0.93 -
b 0.19 0.30
c 0.09 0.20
-
-
D 4.90 5.10 -
E 6.40 BSC
E1 4.30 4.50 -
e 0.65 BSC
L 0.45 0.75 -
L1 1.00 REF
L2 0.25 BSC
R 0.09
R1 0.09
- -
- -
X - - 1.350
Y - - 1.050
Θ
Θ1
Θ2
0° 8°
5° 15°
0° -
-
-
-
All Dimensions in mm
July 2013
© Diodes Incorporated
Page 10
Suggested Pad Layout
Please see AP02001 at http://www.diodes.com/datasheets/ap02001.pdf for the latest version.
Package Type: SO-16
X1
Preliminary
Package Type: TSSOP-16
Y1
Pin 1
Y
X
X1
C
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Y1
1
X (16x)
74HCT595
Document number: DS35493 Rev. 3 - 2
Y (16x)
C
Dimensions Value (in mm)
C 1.270 X 0.670
X1 9.560
Y 1.450
Y1 6.400
Dimensions Value (in mm)
C 0.650
X 0.350
X1 4.900
Y 1.400
Y1 6.800
July 2013
© Diodes Incorporated
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This document is written in English but may be translated into multiple languages for reference. Only the English version of this document is the
Preliminary
final and determinative format released by Diodes Incorporated.
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1. are intended to implant into the body, or
labeling can be reasonably expected to result in significant injury to the user.
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Copyright © 2013, Diodes Incorporated
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2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the
IMPORTANT NOTICE
LIFE SUPPORT
74HCT595
Document number: DS35493 Rev. 3 - 2
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