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The GL823K is a USB 2.0 Single-LUN card reader controller which can support SD/MMC/MSPRO Flash
Memory Cards. It supports USB 2.0 high-speed transmission to Secure DigitalTM (SD), SDHC, SDXC,
miniSDTM, microSDTM(T-Flash), MultiMediaCardTM (MMC), RS MultiMediaCardTM (RS MMC), MMCmicro ,
HS-MMC, MMCmobile, Memory Stick PROTM (MS PRO), Memory Stick PROTM Duo (MS PRO Duo),
Memory Stick PRO-HGTM (MS PRO-HG), MS Micro (M2) on one chip. As a single chip solution for USB 2.0
flash card reader, the GL823K complies with Universal Serial Bus specification rev. 2.0, USB Storage Class
Specification ver.1.0, and each flash card interface specification.
The GL823K integrates a high speed 8051 microprocessor and a high efficiency hardware engine for the best
data transfer performance between USB and flash card interfaces. Its pin assignment design fits to card sockets
to provide easier PCB layout. Inside the chip, it integrates 5V to 3.3V regulator, 3.3V to 1.8V regulator and
power MOSFETs and it enables the function of on-chip clock source (OCCS) which means no external 12MHz
XTAL is needed and that effectively reduces the total BOM cost.
The GL823K implements USB disconnect function; it can be used for Mobile cable/ OTG reader/ PC card reader
application
Memory Stick PRO / Memory Stick PRO Duo / Memory Stick PRO-HG / MS Micro (M2)
- Compliant with Memory Stick Series Specification: MS PRO v1.05, MS PRO-HG Duo 1.03, MS
Micro (M2) v1.06
- Support 4bit data bus
TM
(MMC)
Support boost mode for SD3.0 for better performance
Support non-SD Card Detect pin, non-MS Insertion/Removal pin design to save BOM cost
Support non-SD Write Protection pin design to save BOM cost
Support LED function to indicate power and access status
On chip clock source and no need of 12MHz Crystal Clock input
On-Chip 5V to 3.3V and 3.3V to 1.8V regulators
On-Chip power MOSFET for supplying flash media card power
Support USB disconnection by memory card unplug or manual switch for Mobile cable/ OTG reader/ PC
The USB 2.0 Transceiver Macrocell is the analog circuitry that handles the low level USB protocol and signaling,
and shifts the clock domain of the data from the USB 2.0 rate to one that is compatible with the general logic. On
chip clock source and no need of 12MHz Crystal Clock input.
4.2 SIE
The Serial Interface Engine, which contains the USB PID and address recognition logic, and other sequencing
and state machine logic to handle USB packets and transactions.
4.3 EPFIFO
Endpoint FIFO includes Control FIFO (FIFO0) and Bulk In/Out FIFO
EP0 FIFO FIFO of control endpoint 0. It is 64-byte FIFO and used for endpoint 0 data transfer.
Interrupt FIFO 64-byte depth FIFO of endpoint 3 for status interrupt
Bulk FIFO It can be in the TX mode or RX mode:
1. It contains ping-pong FIFO (512 bytes each bank) for transmit/receive data continuously.
2. It can be directly accessed by micro-controller
4.4 MCU
8051 micro-controller inside.
8051 Core Compliant with Intel 8051 high speed micro-controller
ROM FW code on ROM
SRAM Internal RAM area for MCU access